From 5d9092605288d411dfe457e1197f497cb4c8d065 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Sat, 1 Feb 2014 01:10:15 -0800 Subject: [PATCH] i965: Delete stale "pre-gen4" comment in texture validation code. In commit 16060c5adcd4d809f97e874fcde763260c17ac18, Eric changed the code to not relayout just for baselevel changes - only if the range of miplevels actually increases. So this comment is now wrong. Notably, the i915 version of the code actually does what the comment says. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_tex_validate.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index 07f3174..38cee2a 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c @@ -107,11 +107,6 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit) /* Check tree can hold all active levels. Check tree matches * target, imageFormat, etc. - * - * For pre-gen4, we have to match first_level == tObj->BaseLevel, - * because we don't have the control that gen4 does to make min/mag - * determination happen at a nonzero (hardware) baselevel. Because - * of that, we just always relayout on baselevel change. */ if (intelObj->mt && (!intel_miptree_match_image(intelObj->mt, &firstImage->base.Base) || -- 2.7.4