From 5d78760a789c5310f9b6402e833671daa2a4646e Mon Sep 17 00:00:00 2001 From: "xianjun.liu" Date: Fri, 12 Oct 2018 15:35:51 +0800 Subject: [PATCH] mtd: nand: tl1: add support slc nand driver [1/1] PD#172587 Problem: Bringup slc nand for TL1. Solution: Add mtd driver for TL1. Verify: Just coding for tl1 and test later. Change-Id: I910a8047394e0ff8fa7e617b90502910e1186c68 Signed-off-by: xianjun.liu --- arch/arm/boot/dts/amlogic/mesontl1.dtsi | 59 +++++++++++++++++++++++++++++ arch/arm/boot/dts/amlogic/tl1_pxp.dts | 67 +++++++++++++++++++++++++++++++++ drivers/amlogic/mtd/m3_nand.c | 6 ++- 3 files changed, 130 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/amlogic/mesontl1.dtsi b/arch/arm/boot/dts/amlogic/mesontl1.dtsi index 183fc8f..26cafb0 100644 --- a/arch/arm/boot/dts/amlogic/mesontl1.dtsi +++ b/arch/arm/boot/dts/amlogic/mesontl1.dtsi @@ -811,6 +811,36 @@ spifc-io-width = <4>; }; }; + + slc_nand: nand-controller@0xFFE07800 { + compatible = "amlogic, aml_mtd_nand"; + status = "okay"; + reg = <0x0 0xFFE07800 0x0 0x200>; + interrupts = <0 34 1>; + + pinctrl-names = "nand_rb_mod", "nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>; + clock-names = "core", "clkin"; + + device_id = <0>; + /*fip/tpl configurations, must be same + *with uboot if bl_mode was set as 1 + *bl_mode: 0 compact mode;1 descrete mode + *if bl_mode was set as 1,fip configuration will work + */ + bl_mode = <1>; + /*copy count of fip*/ + fip_copies = <4>; + /*size of each fip copy*/ + fip_size = <0x200000>; + nand_clk_ctrl = <0xFFE07000>; + /*partions defined in dts*/ + }; + }; /* end of / */ &pinctrl_aobus { @@ -1054,6 +1084,35 @@ }; }; + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "nand_ce0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr"; + function = "nand"; + input-enable; + drive-strength = <3>; + }; + }; + + nand_cs_pins:nand_cs { + mux { + groups = "nand_ce0"; + function = "nand"; + drive-strength = <3>; + }; + }; + /* sdemmc portA */ sdio_clk_cmd_pins: sdio_clk_cmd_pins { mux { diff --git a/arch/arm/boot/dts/amlogic/tl1_pxp.dts b/arch/arm/boot/dts/amlogic/tl1_pxp.dts index 11beb62..b56c2de 100644 --- a/arch/arm/boot/dts/amlogic/tl1_pxp.dts +++ b/arch/arm/boot/dts/amlogic/tl1_pxp.dts @@ -67,6 +67,73 @@ status = "disabled"; spi-nor@0 { cs_gpios = <&gpio BOOT_13 GPIO_ACTIVE_HIGH>; + }; + }; + +&slc_nand { + status = "disabled"; + plat-names = "bootloader", "nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad = "ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad = "ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; }; }; diff --git a/drivers/amlogic/mtd/m3_nand.c b/drivers/amlogic/mtd/m3_nand.c index a007576..d6d95dc 100644 --- a/drivers/amlogic/mtd/m3_nand.c +++ b/drivers/amlogic/mtd/m3_nand.c @@ -309,14 +309,16 @@ void get_sys_clk_rate_mtd(struct hw_controller *controller, int *rate) #else if ((get_cpu_type() == MESON_CPU_MAJOR_ID_AXG) || (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) - || (get_cpu_type() == MESON_CPU_MAJOR_ID_G12B)) + || (get_cpu_type() == MESON_CPU_MAJOR_ID_G12B) + || (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)) always_on = 0x1 << 28; #endif if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) || (get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) || (get_cpu_type() == MESON_CPU_MAJOR_ID_AXG) || (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) - || (get_cpu_type() == MESON_CPU_MAJOR_ID_G12B)) { + || (get_cpu_type() == MESON_CPU_MAJOR_ID_G12B) + || (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)) { switch (clk_freq) { case 24: clk = 0x80000201; -- 2.7.4