From 5d0d5108d733a0b7938d18e828c95ef7d985b9bc Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Wed, 3 May 2023 19:39:46 +0200 Subject: [PATCH] ir3/a7xx: cat5 mode1 has swapped tex/samp ids Though blob is not seen to even use mode1 on a740, it uses S2EN variant instead. Fixes: dEQP-VK.binding_model.descriptor_buffer.multiple.* dEQP-VK.binding_model.descriptor_buffer.embedded_imm_samplers.* dEQP-VK.pipeline.monolithic.descriptor_limits.compute_shader.* Adapted from Jonathan Marek's changes. Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/ir3/ir3_compiler_nir.c | 13 +++++++++-- src/freedreno/ir3/ir3_parser.y | 2 ++ src/freedreno/ir3/tests/disasm.c | 2 ++ src/freedreno/isa/ir3-cat5.xml | 45 ++++++++++++++++++++++++++++++++++-- 4 files changed, 58 insertions(+), 4 deletions(-) diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index e2accd2..7b211e3 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -1359,7 +1359,11 @@ get_image_ssbo_samp_tex_src(struct ir3_context *ctx, nir_src *src, bool image) info.base = info.tex_base; } else { info.base = info.tex_base; - info.a1_val = info.tex_idx << 3; + if (ctx->compiler->gen <= 6) { + info.a1_val = info.tex_idx << 3; + } else { + info.a1_val = info.samp_idx << 3; + } info.flags |= IR3_INSTR_A1EN; } info.samp_tex = NULL; @@ -2819,7 +2823,12 @@ get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex) info.base = info.tex_base; } else { info.base = info.tex_base; - info.a1_val = info.tex_idx << 3 | info.samp_base; + if (ctx->compiler->gen <= 6) { + info.a1_val = info.tex_idx << 3 | info.samp_base; + } else { + info.a1_val = info.samp_idx << 3 | info.samp_base; + } + info.flags |= IR3_INSTR_A1EN; } info.samp_tex = NULL; diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y index 9d0616f..431995c 100644 --- a/src/freedreno/ir3/ir3_parser.y +++ b/src/freedreno/ir3/ir3_parser.y @@ -1099,11 +1099,13 @@ cat5_instr: cat5_opc_dsxypp cat5_flags dst_reg ',' src_reg | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' src_reg | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' cat5_samp ',' cat5_tex | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' cat5_samp ',' cat5_a1 +| cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' cat5_tex ',' cat5_a1 | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' cat5_samp | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' cat5_tex | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' cat5_samp ',' cat5_tex | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' cat5_samp ',' cat5_a1 +| cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' cat5_tex ',' cat5_a1 | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' cat5_samp | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' cat5_tex | cat5_opc cat5_flags cat5_type dst_reg ',' src_reg diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c index fe8fa00..d86991b 100644 --- a/src/freedreno/ir3/tests/disasm.c +++ b/src/freedreno/ir3/tests/disasm.c @@ -180,6 +180,8 @@ static const struct test { INSTR_6XX(a048d107_cc080a07, "isaml.base3 (s32)(x)r1.w, r0.w, r1.y, s#0, t#6"), INSTR_6XX(a048d107_e0080a07, "isaml.base3 (s32)(x)r1.w, r0.w, r1.y, s#0, a1.x"), + INSTR_7XX(a0081f02_e2000001, "isam.base0 (f32)(xyzw)r0.z, r0.x, t#16, a1.x"), + INSTR_7XX(a148310d_e028302c, "saml.base2 (u32)(x)r3.y, hr5.z, hr6.x, t#1, a1.x"), /* dEQP-VK.subgroups.arithmetic.compute.subgroupadd_float */ INSTR_6XX(a7c03102_00100003, "brcst.active.w8 (u32)(x)r0.z, r0.y"), /* brcst.active.w8 (u32)(xOOO)r0.z, r0.y */ diff --git a/src/freedreno/isa/ir3-cat5.xml b/src/freedreno/isa/ir3-cat5.xml index ef4d7c7..9ca1567 100644 --- a/src/freedreno/isa/ir3-cat5.xml +++ b/src/freedreno/isa/ir3-cat5.xml @@ -637,7 +637,7 @@ SOFTWARE. - s2en (indirect) / bindless case with a1.x has 8b samp + s2en (indirect) / bindless case with tex in a1.x {HAS_SAMP} @@ -652,6 +652,22 @@ SOFTWARE. + + s2en (indirect) / bindless case with samp in a1.x + + {HAS_TEX} + + , t#{TEX} + + + + + 00000000 + + src->cat5.tex + + + {HAS_TEX} @@ -790,6 +806,20 @@ SOFTWARE. ({DESC_MODE} == 7) /* CAT5_BINDLESS_A1_IMM */ + + ISA_GPU_ID() >= 600 && ISA_GPU_ID() < 700 && + (({DESC_MODE} == 1) /* CAT5_BINDLESS_A1_UNIFORM */ || + ({DESC_MODE} == 3) /* CAT5_BINDLESS_A1_NONUNIFORM */ || + ({DESC_MODE} == 7))/* CAT5_BINDLESS_A1_IMM */ + + + + ISA_GPU_ID() >= 700 && + (({DESC_MODE} == 1) /* CAT5_BINDLESS_A1_UNIFORM */ || + ({DESC_MODE} == 3) /* CAT5_BINDLESS_A1_NONUNIFORM */ || + ({DESC_MODE} == 7))/* CAT5_BINDLESS_A1_IMM */ + + ({DESC_MODE} == 0) /* CAT5_UNIFORM */ || @@ -815,7 +845,7 @@ SOFTWARE. !{BINDLESS} - + In the case that a1.x is used, all 8 bits encode sampler @@ -826,6 +856,17 @@ SOFTWARE. + + + In the case that a1.x is used, all 8 bits encode texture + + + {TEX} + + + + + {SAMP}{TEX} -- 2.7.4