From 5d06f17b8a4717dea5c75d36c26c4927e6633a01 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Mon, 27 Aug 2018 13:20:42 +0000 Subject: [PATCH] [PowerPC] Revert commit r339779 This commit has caused failures in some internal benchmarks. Temporarily reverting this patch until the issue can be diagnosed and fixed. llvm-svn: 340740 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 8 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 10 ++- llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 4 -- llvm/lib/Target/PowerPC/PPCInstrVSX.td | 3 +- llvm/test/CodeGen/PowerPC/vec_select.ll | 103 ++-------------------------- llvm/test/CodeGen/PowerPC/vsx.ll | 4 +- 6 files changed, 23 insertions(+), 109 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 789d862..54239c2 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -4647,6 +4647,14 @@ void PPCDAGToDAGISel::Select(SDNode *N) { CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops); return; } + case ISD::VSELECT: + if (PPCSubTarget->hasVSX()) { + SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) }; + CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops); + return; + } + break; + case ISD::VECTOR_SHUFFLE: if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 || N->getValueType(0) == MVT::v2i64)) { diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 2b57531..2a1a2ae 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -586,8 +586,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); setOperationAction(ISD::SELECT, VT, Promote); AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); - setOperationAction(ISD::VSELECT, VT, Promote); - AddPromotedToType (ISD::VSELECT, VT, MVT::v4i32); setOperationAction(ISD::SELECT_CC, VT, Promote); AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); setOperationAction(ISD::STORE, VT, Promote); @@ -628,6 +626,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); setOperationAction(ISD::FPOW, VT, Expand); setOperationAction(ISD::BSWAP, VT, Expand); + setOperationAction(ISD::VSELECT, VT, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); setOperationAction(ISD::ROTL, VT, Expand); setOperationAction(ISD::ROTR, VT, Expand); @@ -650,7 +649,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::LOAD , MVT::v4i32, Legal); setOperationAction(ISD::SELECT, MVT::v4i32, Subtarget.useCRBits() ? Legal : Expand); - setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); setOperationAction(ISD::STORE , MVT::v4i32, Legal); setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); @@ -729,6 +727,12 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::FDIV, MVT::v2f64, Legal); setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); + setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); + setOperationAction(ISD::VSELECT, MVT::v8i16, Legal); + setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); + setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); + setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); + // Share the Altivec comparison restrictions. setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand); setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand); diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 587a290..24969d7 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -1051,10 +1051,6 @@ def : Pat<(v4f32 (ftrunc v4f32:$vA)), def : Pat<(v4f32 (fnearbyint v4f32:$vA)), (VRFIN $vA)>; -// Vector selection -def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)), - (VSEL $vC, $vB, $vA)>; - } // end HasAltivec def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">; diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 3a792d8..781a327 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -870,8 +870,7 @@ let Uses = [RM] in { "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>; def XXSEL : XX4Form<60, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC), - "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, - [(set v4i32:$XT, (vselect v4i32:$XC, v4i32:$XB, v4i32:$XA))]>; + "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>; def XXSLDWI : XX3Form_2<60, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW), diff --git a/llvm/test/CodeGen/PowerPC/vec_select.ll b/llvm/test/CodeGen/PowerPC/vec_select.ll index 3b4f390..cb2a12e 100644 --- a/llvm/test/CodeGen/PowerPC/vec_select.ll +++ b/llvm/test/CodeGen/PowerPC/vec_select.ll @@ -1,100 +1,7 @@ -; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX -; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX -; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX -; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-linux-gnu -mattr=+altivec | FileCheck %s -define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { -entry: - %m = fcmp oeq <4 x float> %c, %d - %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b - ret <4 x float> %v +; CHECK: vsel_float +define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { + %vsel = select <4 x i1> , <4 x float> %v1, <4 x float> %v2 + ret <4 x float> %vsel } -; CHECK-VSX-LABLE: test1 -; CHECK-VSX: xvcmpeqsp [[REG1:(vs|v)[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, [[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test1 -; CHECK-NOVSX: vcmpeqfp v[[REG1:[0-9]+]], v4, v5 -; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]] -; CHECK-NOVSX: blr - -define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) { -entry: - %m = fcmp oeq <2 x double> %c, %d - %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b - ret <2 x double> %v -} -; CHECK-VSX-LABLE: test2 -; CHECK-VSX: xvcmpeqdp [[REG1:(vs|v)[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, [[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test2 -; CHECK-NOVSX: fcmp -; CHECK-NOVSX: fcmp -; CHECK-NOVSX: blr - -define <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { -entry: - %m = icmp eq <16 x i8> %c, %d - %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b - ret <16 x i8> %v -} -; CHECK-VSX-LABLE: test3 -; CHECK-VSX: vcmpequb v[[REG1:[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test3 -; CHECK-NOVSX: vcmpequb v[[REG1:[0-9]+]], v4, v5 -; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]] -; CHECK-NOVSX: blr - -define <8 x i16> @test4(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { -entry: - %m = icmp eq <8 x i16> %c, %d - %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b - ret <8 x i16> %v -} -; CHECK-VSX-LABLE: test4 -; CHECK-VSX: vcmpequh v[[REG1:[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test4 -; CHECK-NOVSX: vcmpequh v[[REG1:[0-9]+]], v4, v5 -; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]] -; CHECK-NOVSX: blr - -define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { -entry: - %m = icmp eq <4 x i32> %c, %d - %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b - ret <4 x i32> %v -} -; CHECK-VSX-LABLE: test5 -; CHECK-VSX: vcmpequw v[[REG1:[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test5 -; CHECK-NOVSX: vcmpequw v[[REG1:[0-9]+]], v4, v5 -; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]] -; CHECK-NOVSX: blr - -define <2 x i64> @test6(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) { -entry: - %m = icmp eq <2 x i64> %c, %d - %v = select <2 x i1> %m, <2 x i64> %a, <2 x i64> %b - ret <2 x i64> %v -} -; CHECK-VSX-LABLE: test6 -; CHECK-VSX: vcmpequd v[[REG1:[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test6 -; CHECK-NOVSX: vcmpequd v[[REG1:[0-9]+]], v4, v5 -; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]] -; CHECK-NOVSX: blr diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll index 1659bc1..3df501d 100644 --- a/llvm/test/CodeGen/PowerPC/vsx.ll +++ b/llvm/test/CodeGen/PowerPC/vsx.ll @@ -525,8 +525,8 @@ entry: ret <2 x double> %v ; CHECK-LABEL: @test25 -; CHECK: xvcmpeqdp v4, v4, v5 -; CHECK: xxsel v2, v3, v2, v4 +; CHECK: xvcmpeqdp vs0, v4, v5 +; CHECK: xxsel v2, v3, v2, vs0 ; CHECK: blr ; CHECK-LE-LABEL: @test25 -- 2.7.4