From 5cde1ccb2998fe06e3930c1d5a8f3c4fb93e845d Mon Sep 17 00:00:00 2001 From: Javed Absar Date: Mon, 30 Oct 2017 13:51:56 +0000 Subject: [PATCH] [GlobalISel|ARM] : Allow legalizing G_FSUB Adding support for VSUB. Reviewed by: @rovka Differential Revision: https://reviews.llvm.org/D39261 llvm-svn: 316902 --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 4 + llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 10 ++- llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 7 +- .../ARM/GlobalISel/arm-instruction-select.mir | 63 +++++++++++++++ llvm/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll | 17 ++++ .../CodeGen/ARM/GlobalISel/arm-legalize-fp.mir | 90 ++++++++++++++++++++++ .../CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 55 +++++++++++++ 7 files changed, 238 insertions(+), 8 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index cd6684f..99f605a 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -91,6 +91,9 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { case TargetOpcode::G_FADD: assert((Size == 32 || Size == 64) && "Unsupported size"); return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32; + case TargetOpcode::G_FSUB: + assert((Size == 32 || Size == 64) && "Unsupported size"); + return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32; case TargetOpcode::G_FREM: return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32; case TargetOpcode::G_FPOW: @@ -146,6 +149,7 @@ LegalizerHelper::libcall(MachineInstr &MI) { break; } case TargetOpcode::G_FADD: + case TargetOpcode::G_FSUB: case TargetOpcode::G_FPOW: case TargetOpcode::G_FREM: { Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx); diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp index 695e0f6..309430b 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -103,8 +103,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({G_ICMP, 1, Ty}, Legal); if (!ST.useSoftFloat() && ST.hasVFP2()) { - setAction({G_FADD, s32}, Legal); - setAction({G_FADD, s64}, Legal); + for (unsigned BinOp : {G_FADD, G_FSUB}) + for (auto Ty : {s32, s64}) + setAction({BinOp, Ty}, Legal); setAction({G_LOAD, s64}, Legal); setAction({G_STORE, s64}, Legal); @@ -113,8 +114,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({G_FCMP, 1, s32}, Legal); setAction({G_FCMP, 1, s64}, Legal); } else { - for (auto Ty : {s32, s64}) - setAction({G_FADD, Ty}, Libcall); + for (unsigned BinOp : {G_FADD, G_FSUB}) + for (auto Ty : {s32, s64}) + setAction({BinOp, Ty}, Libcall); setAction({G_FCMP, s1}, Legal); setAction({G_FCMP, 1, s32}, Custom); diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index c01cc06..9915510 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -242,11 +242,10 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { : &ARM::ValueMappings[ARM::GPR3OpsIdx]; break; } - case G_FADD: { + case G_FADD: + case G_FSUB: { LLT Ty = MRI.getType(MI.getOperand(0).getReg()); - assert((Ty.getSizeInBits() == 32 || Ty.getSizeInBits() == 64) && - "Unsupported size for G_FADD"); - OperandsMapping = Ty.getSizeInBits() == 64 + OperandsMapping =Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] : &ARM::ValueMappings[ARM::SPR3OpsIdx]; break; diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir index 34a9937..0fdd485 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -12,6 +12,9 @@ define void @test_fadd_s32() #0 { ret void } define void @test_fadd_s64() #0 { ret void } + define void @test_fsub_s32() #0 { ret void } + define void @test_fsub_s64() #0 { ret void } + define void @test_sub_s32() { ret void } define void @test_mul_s32() #1 { ret void } @@ -321,6 +324,66 @@ body: | ; CHECK: BX_RET 14, _, implicit %d0 ... --- +name: test_fsub_s32 +# CHECK-LABEL: name: test_fsub_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: fprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1 + + %2(s32) = G_FSUB %0, %1 + ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, _ + + %s0 = COPY %2(s32) + ; CHECK: %s0 = COPY [[VREGSUM]] + + BX_RET 14, _, implicit %s0 + ; CHECK: BX_RET 14, _, implicit %s0 +... +--- +name: test_fsub_s64 +# CHECK-LABEL: name: test_fsub_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: fprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1 + + %2(s64) = G_FSUB %0, %1 + ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, _ + + %d0 = COPY %2(s64) + ; CHECK: %d0 = COPY [[VREGSUM]] + + BX_RET 14, _, implicit %d0 + ; CHECK: BX_RET 14, _, implicit %d0 +... +--- name: test_sub_s32 # CHECK-LABEL: name: test_sub_s32 legalized: true diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll index 3fd3de2..beda484 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll @@ -50,6 +50,23 @@ define arm_aapcscc double @test_add_double(double %x, double %y) { ret double %r } +define arm_aapcscc float @test_sub_float(float %x, float %y) { +; CHECK-LABEL: test_sub_float: +; HARD: vsub.f32 +; SOFT-AEABI: bl __aeabi_fsub +; SOFT-DEFAULT: bl __subsf3 + %r = fsub float %x, %y + ret float %r +} + +define arm_aapcscc double @test_sub_double(double %x, double %y) { +; CHECK-LABEL: test_sub_double: +; HARD: vsub.f64 +; SOFT-AEABI: bl __aeabi_dsub +; SOFT-DEFAULT: bl __subdf3 + %r = fsub double %x, %y + ret double %r +} define arm_aapcs_vfpcc i32 @test_cmp_float_ogt(float %x, float %y) { ; CHECK-LABEL: test_cmp_float_ogt ; HARD: vcmp.f32 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir index bdb064a..f665bfe 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir @@ -11,6 +11,9 @@ define void @test_fadd_float() { ret void } define void @test_fadd_double() { ret void } + define void @test_fsub_float() { ret void } + define void @test_fsub_double() { ret void } + define void @test_fcmp_true_s32() { ret void } define void @test_fcmp_false_s32() { ret void } @@ -327,6 +330,93 @@ body: | BX_RET 14, _, implicit %r0, implicit %r1 ... --- +name: test_fsub_float +# CHECK-LABEL: name: test_fsub_float +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; HARD: [[R:%[0-9]+]]:_(s32) = G_FSUB [[X]], [[Y]] + ; SOFT-NOT: G_FSUB + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_FSUB + %2(s32) = G_FSUB %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_fsub_double +# CHECK-LABEL: name: test_fsub_double +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]] + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]] + %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) + ; HARD: [[R:%[0-9]+]]:_(s64) = G_FSUB [[X]], [[Y]] + ; SOFT-NOT: G_FSUB + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] + ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] + ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]] + ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dsub, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; SOFT-DEFAULT: BL $__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_FSUB + %6(s64) = G_FSUB %4, %5 + ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64) + %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) + %r0 = COPY %7(s32) + %r1 = COPY %8(s32) + BX_RET 14, _, implicit %r0, implicit %r1 +... +--- name: test_fcmp_true_s32 # CHECK-LABEL: name: test_fcmp_true_s32 legalized: false diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index 6a0d857..4a72031 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -43,6 +43,9 @@ define void @test_fadd_s32() #0 { ret void } define void @test_fadd_s64() #0 { ret void } + define void @test_fsub_s32() #0 { ret void } + define void @test_fsub_s64() #0 { ret void } + define void @test_soft_fp_s64() #0 { ret void } attributes #0 = { "target-features"="+vfp2"} @@ -777,6 +780,58 @@ body: | ... --- +name: test_fsub_s32 +# CHECK-LABEL: name: test_fsub_s32 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: fprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } +# CHECK: - { id: 2, class: fprb, preferred-register: '' } + +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + %1(s32) = COPY %s1 + %2(s32) = G_FSUB %0, %1 + %s0 = COPY %2(s32) + BX_RET 14, _, implicit %s0 + +... +--- +name: test_fsub_s64 +# CHECK-LABEL: name: test_fsub_s64 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: fprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } +# CHECK: - { id: 2, class: fprb, preferred-register: '' } + +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + %1(s64) = COPY %d1 + %2(s64) = G_FSUB %0, %1 + %d0 = COPY %2(s64) + BX_RET 14, _, implicit %d0 + +... +--- name: test_soft_fp_s64 # CHECK-LABEL: name: test_soft_fp_s64 legalized: true -- 2.7.4