From 5c7069712c9be01d1bf9061a7ef5ce78df0af0a5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:47 +0100 Subject: [PATCH] dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern The SDX55 TLMM pin controller has GPIOs 0-107, so narrow the pattern. Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-6-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml index add3c7e..a401752 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml @@ -55,7 +55,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 -- 2.7.4