From 5b5f1c8efd676696f2f035f70bce0efc955b9019 Mon Sep 17 00:00:00 2001 From: Huihui Zhang Date: Mon, 23 Sep 2019 23:48:32 +0000 Subject: [PATCH] [NFC][InstCombine] Add tests for shifty implementation of clamping. Summary: Clamp negative to zero and clamp positive to allOnes are common operation in image saturation. Add tests for shifty implementation of clamping, as prepare work for folding: and(ashr(subNSW(Y, X), ScalarSizeInBits(Y)-1), X) --> X s> 0 ? X : 0; or(ashr(subNSW(Y, X), ScalarSizeInBits(Y)-1), X) --> X s> Y ? allOnes : X. Reviewers: lebedev.ri, efriedma, spatel, kparzysz, bcahoon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67798 llvm-svn: 372671 --- .../InstCombine/sub-ashr-and-to-icmp-select.ll | 223 ++++++++++++++++++ .../InstCombine/sub-ashr-or-to-icmp-select.ll | 250 +++++++++++++++++++++ 2 files changed, 473 insertions(+) create mode 100644 llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll create mode 100644 llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll diff --git a/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll b/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll new file mode 100644 index 0000000..2018e9f --- /dev/null +++ b/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll @@ -0,0 +1,223 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -instcombine %s -S -o - | FileCheck %s + +; Clamp negative to zero: +; E.g., clamp0 implemented in a shifty way, could be optimized as v > 0 ? v : 0, where sub hasNoSignedWrap. +; int32 clamp0(int32 v) { +; return ((-(v) >> 31) & (v)); +; } +; + +; Scalar Types + +define i8 @sub_ashr_and_i8(i8 %x, i8 %y) { +; CHECK-LABEL: @sub_ashr_and_i8( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i8 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i8 [[SUB]], 7 +; CHECK-NEXT: [[AND:%.*]] = and i8 [[SHR]], [[X]] +; CHECK-NEXT: ret i8 [[AND]] +; + %sub = sub nsw i8 %y, %x + %shr = ashr i8 %sub, 7 + %and = and i8 %shr, %x + ret i8 %and +} + +define i16 @sub_ashr_and_i16(i16 %x, i16 %y) { +; CHECK-LABEL: @sub_ashr_and_i16( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i16 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i16 [[SUB]], 15 +; CHECK-NEXT: [[AND:%.*]] = and i16 [[SHR]], [[X]] +; CHECK-NEXT: ret i16 [[AND]] +; + + %sub = sub nsw i16 %y, %x + %shr = ashr i16 %sub, 15 + %and = and i16 %shr, %x + ret i16 %and +} + +define i32 @sub_ashr_and_i32(i32 %x, i32 %y) { +; CHECK-LABEL: @sub_ashr_and_i32( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[AND]] +; + %sub = sub nsw i32 %y, %x + %shr = ashr i32 %sub, 31 + %and = and i32 %shr, %x + ret i32 %and +} + +define i64 @sub_ashr_and_i64(i64 %x, i64 %y) { +; CHECK-LABEL: @sub_ashr_and_i64( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i64 [[SUB]], 63 +; CHECK-NEXT: [[AND:%.*]] = and i64 [[SHR]], [[X]] +; CHECK-NEXT: ret i64 [[AND]] +; + %sub = sub nsw i64 %y, %x + %shr = ashr i64 %sub, 63 + %and = and i64 %shr, %x + ret i64 %and +} + +; nuw nsw + +define i32 @sub_ashr_and_i32_nuw_nsw(i32 %x, i32 %y) { +; CHECK-LABEL: @sub_ashr_and_i32_nuw_nsw( +; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[AND]] +; + %sub = sub nuw nsw i32 %y, %x + %shr = ashr i32 %sub, 31 + %and = and i32 %shr, %x + ret i32 %and +} + +; Commute + +define i32 @sub_ashr_and_i32_commute(i32 %x, i32 %y) { +; CHECK-LABEL: @sub_ashr_and_i32_commute( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[AND]] +; + %sub = sub nsw i32 %y, %x + %shr = ashr i32 %sub, 31 + %and = and i32 %x, %shr ; commute %x and %shr + ret i32 %and +} + +; Vector Types + +define <4 x i32> @sub_ashr_and_i32_vec(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: @sub_ashr_and_i32_vec( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], +; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]] +; CHECK-NEXT: ret <4 x i32> [[AND]] +; + %sub = sub nsw <4 x i32> %y, %x + %shr = ashr <4 x i32> %sub, + %and = and <4 x i32> %shr, %x + ret <4 x i32> %and +} + +define <4 x i32> @sub_ashr_and_i32_vec_nuw_nsw(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: @sub_ashr_and_i32_vec_nuw_nsw( +; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw <4 x i32> [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], +; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]] +; CHECK-NEXT: ret <4 x i32> [[AND]] +; + %sub = sub nuw nsw <4 x i32> %y, %x + %shr = ashr <4 x i32> %sub, + %and = and <4 x i32> %shr, %x + ret <4 x i32> %and +} + +define <4 x i32> @sub_ashr_and_i32_vec_commute(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: @sub_ashr_and_i32_vec_commute( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], +; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]] +; CHECK-NEXT: ret <4 x i32> [[AND]] +; + %sub = sub nsw <4 x i32> %y, %x + %shr = ashr <4 x i32> %sub, + %and = and <4 x i32> %x, %shr ; commute %x and %shr + ret <4 x i32> %and +} + +; Extra uses + +define i32 @sub_ashr_and_i32_extra_use_sub(i32 %x, i32 %y, i32* %p) { +; CHECK-LABEL: @sub_ashr_and_i32_extra_use_sub( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: store i32 [[SUB]], i32* [[P:%.*]], align 4 +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[AND]] +; + %sub = sub nsw i32 %y, %x + store i32 %sub, i32* %p + %shr = ashr i32 %sub, 31 + %and = and i32 %shr, %x + ret i32 %and +} + +define i32 @sub_ashr_and_i32_extra_use_and(i32 %x, i32 %y, i32* %p) { +; CHECK-LABEL: @sub_ashr_and_i32_extra_use_and( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]] +; CHECK-NEXT: store i32 [[AND]], i32* [[P:%.*]], align 4 +; CHECK-NEXT: ret i32 [[AND]] +; + %sub = sub nsw i32 %y, %x + %shr = ashr i32 %sub, 31 + %and = and i32 %shr, %x + store i32 %and, i32* %p + ret i32 %and +} + +; Negative Tests + +define i32 @sub_ashr_and_i32_extra_use_ashr(i32 %x, i32 %y, i32* %p) { +; CHECK-LABEL: @sub_ashr_and_i32_extra_use_ashr( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: store i32 [[SHR]], i32* [[P:%.*]], align 4 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[AND]] +; + %sub = sub nsw i32 %y, %x + %shr = ashr i32 %sub, 31 + store i32 %shr, i32* %p + %and = and i32 %shr, %x + ret i32 %and +} + +define i32 @sub_ashr_and_i32_no_nuw_nsw(i32 %x, i32 %y) { +; CHECK-LABEL: @sub_ashr_and_i32_no_nuw_nsw( +; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 7 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[AND]] +; + %sub = sub i32 %y, %x + %shr = ashr i32 %sub, 7 + %and = and i32 %shr, %x + ret i32 %and +} + +define <4 x i32> @sub_ashr_and_i32_vec_undef(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: @sub_ashr_and_i32_vec_undef( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], +; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]] +; CHECK-NEXT: ret <4 x i32> [[AND]] +; + %sub = sub nsw <4 x i32> %y, %x + %shr = ashr <4 x i32> %sub, + %and = and <4 x i32> %shr, %x + ret <4 x i32> %and +} + +define i32 @sub_ashr_and_i32_shift_wrong_bit(i32 %x, i32 %y) { +; CHECK-LABEL: @sub_ashr_and_i32_shift_wrong_bit( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 15 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[AND]] +; + %sub = sub nsw i32 %y, %x + %shr = ashr i32 %sub, 15 + %and = and i32 %shr, %x + ret i32 %and +} diff --git a/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll b/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll new file mode 100644 index 0000000..630a14f --- /dev/null +++ b/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll @@ -0,0 +1,250 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -instcombine %s -S -o - | FileCheck %s + +; Clamp positive to allOnes: +; E.g., clamp255 implemented in a shifty way, could be optimized as v > 255 ? 255 : v, where sub hasNoSignedWrap. +; int32 clamp255(int32 v) { +; return (((255 - (v)) >> 31) | (v)) & 255; +; } +; + +; Scalar Types + +define i32 @clamp255_i32(i32 %x) { +; CHECK-LABEL: @clamp255_i32( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 255, [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]] +; CHECK-NEXT: [[AND:%.*]] = and i32 [[OR]], 255 +; CHECK-NEXT: ret i32 [[AND]] +; + %sub = sub nsw i32 255, %x + %shr = ashr i32 %sub, 31 + %or = or i32 %shr, %x + %and = and i32 %or, 255 + ret i32 %and +} + +define i8 @sub_ashr_or_i8(i8 %x, i8 %y) { +; CHECK-LABEL: @sub_ashr_or_i8( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i8 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i8 [[SUB]], 7 +; CHECK-NEXT: [[OR:%.*]] = or i8 [[SHR]], [[X]] +; CHECK-NEXT: ret i8 [[OR]] +; + %sub = sub nsw i8 %y, %x + %shr = ashr i8 %sub, 7 + %or = or i8 %shr, %x + ret i8 %or +} + +define i16 @sub_ashr_or_i16(i16 %x, i16 %y) { +; CHECK-LABEL: @sub_ashr_or_i16( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i16 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i16 [[SUB]], 15 +; CHECK-NEXT: [[OR:%.*]] = or i16 [[SHR]], [[X]] +; CHECK-NEXT: ret i16 [[OR]] +; + %sub = sub nsw i16 %y, %x + %shr = ashr i16 %sub, 15 + %or = or i16 %shr, %x + ret i16 %or +} + +define i32 @sub_ashr_or_i32(i32 %x, i32 %y) { +; CHECK-LABEL: @sub_ashr_or_i32( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[OR]] +; + %sub = sub nsw i32 %y, %x + %shr = ashr i32 %sub, 31 + %or = or i32 %shr, %x + ret i32 %or +} + +define i64 @sub_ashr_or_i64(i64 %x, i64 %y) { +; CHECK-LABEL: @sub_ashr_or_i64( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i64 [[SUB]], 63 +; CHECK-NEXT: [[OR:%.*]] = or i64 [[SHR]], [[X]] +; CHECK-NEXT: ret i64 [[OR]] +; + %sub = sub nsw i64 %y, %x + %shr = ashr i64 %sub, 63 + %or = or i64 %shr, %x + ret i64 %or +} + +; nuw nsw + +define i32 @sub_ashr_or_i32_nuw_nsw(i32 %x, i32 %y) { +; CHECK-LABEL: @sub_ashr_or_i32_nuw_nsw( +; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[OR]] +; + %sub = sub nuw nsw i32 %y, %x + %shr = ashr i32 %sub, 31 + %or = or i32 %shr, %x + ret i32 %or +} + +; Commute + +define i32 @sub_ashr_or_i32_commute(i32 %x, i32 %y) { +; CHECK-LABEL: @sub_ashr_or_i32_commute( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[OR]] +; + %sub = sub nsw i32 %y, %x + %shr = ashr i32 %sub, 31 + %or = or i32 %x, %shr ; commute %shr and %x + ret i32 %or +} + +; Vector Types + +define <4 x i32> @sub_ashr_or_i32_vec(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: @sub_ashr_or_i32_vec( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], +; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]] +; CHECK-NEXT: ret <4 x i32> [[OR]] +; + %sub = sub nsw <4 x i32> %y, %x + %shr = ashr <4 x i32> %sub, + %or = or <4 x i32> %shr, %x + ret <4 x i32> %or +} + +define <4 x i32> @sub_ashr_or_i32_vec_nuw_nsw(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: @sub_ashr_or_i32_vec_nuw_nsw( +; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw <4 x i32> [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], +; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]] +; CHECK-NEXT: ret <4 x i32> [[OR]] +; + %sub = sub nuw nsw <4 x i32> %y, %x + %shr = ashr <4 x i32> %sub, + %or = or <4 x i32> %shr, %x + ret <4 x i32> %or +} + +define <4 x i32> @sub_ashr_or_i32_vec_commute(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: @sub_ashr_or_i32_vec_commute( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], +; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]] +; CHECK-NEXT: ret <4 x i32> [[OR]] +; + %sub = sub nsw <4 x i32> %y, %x + %shr = ashr <4 x i32> %sub, + %or = or <4 x i32> %x, %shr + ret <4 x i32> %or +} + +; Extra uses + +define i32 @sub_ashr_or_i32_extra_use_sub(i32 %x, i32 %y, i32* %p) { +; CHECK-LABEL: @sub_ashr_or_i32_extra_use_sub( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: store i32 [[SUB]], i32* [[P:%.*]], align 4 +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[OR]] +; + %sub = sub nsw i32 %y, %x + store i32 %sub, i32* %p + %shr = ashr i32 %sub, 31 + %or = or i32 %shr, %x + ret i32 %or +} + +define i32 @sub_ashr_or_i32_extra_use_or(i32 %x, i32 %y, i32* %p) { +; CHECK-LABEL: @sub_ashr_or_i32_extra_use_or( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]] +; CHECK-NEXT: store i32 [[OR]], i32* [[P:%.*]], align 4 +; CHECK-NEXT: ret i32 [[OR]] +; + %sub = sub nsw i32 %y, %x + %shr = ashr i32 %sub, 31 + %or = or i32 %shr, %x + store i32 %or, i32* %p + ret i32 %or +} + +; Negative Tests + +define i32 @sub_ashr_or_i32_extra_use_ashr(i32 %x, i32 %y, i32* %p) { +; CHECK-LABEL: @sub_ashr_or_i32_extra_use_ashr( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: store i32 [[SHR]], i32* [[P:%.*]], align 4 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[OR]] +; + %sub = sub nsw i32 %y, %x + %shr = ashr i32 %sub, 31 + store i32 %shr, i32* %p + %or = or i32 %shr, %x + ret i32 %or +} + +define i32 @sub_ashr_or_i32_no_nsw_nuw(i32 %x, i32 %y) { +; CHECK-LABEL: @sub_ashr_or_i32_no_nsw_nuw( +; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[OR]] +; + %sub = sub i32 %y, %x + %shr = ashr i32 %sub, 31 + %or = or i32 %shr, %x + ret i32 %or +} + +define <4 x i32> @sub_ashr_or_i32_vec_undef1(<4 x i32> %x) { +; CHECK-LABEL: @sub_ashr_or_i32_vec_undef1( +; CHECK-NEXT: [[SUB:%.*]] = sub <4 x i32> , [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], +; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]] +; CHECK-NEXT: ret <4 x i32> [[OR]] +; + %sub = sub <4 x i32> , %x + %shr = ashr <4 x i32> %sub, + %or = or <4 x i32> %shr, %x + ret <4 x i32> %or +} + +define <4 x i32> @sub_ashr_or_i32_vec_undef2(<4 x i32> %x) { +; CHECK-LABEL: @sub_ashr_or_i32_vec_undef2( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> , [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], +; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]] +; CHECK-NEXT: ret <4 x i32> [[OR]] +; + %sub = sub nsw <4 x i32> , %x + %shr = ashr <4 x i32> %sub, + %or = or <4 x i32> %shr, %x + ret <4 x i32> %or +} + +define i32 @sub_ashr_or_i32_shift_wrong_bit(i32 %x, i32 %y) { +; CHECK-LABEL: @sub_ashr_or_i32_shift_wrong_bit( +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 11 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]] +; CHECK-NEXT: ret i32 [[OR]] +; + %sub = sub nsw i32 %y, %x + %shr = ashr i32 %sub, 11 + %or = or i32 %shr, %x + ret i32 %or +} -- 2.7.4