From 5b44f1ba199d78bb3e5319fc7958d0a2ba90c168 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Tue, 7 Apr 2015 22:49:47 +0000 Subject: [PATCH] AArch64: disallow "fmov sD, #-0.0" during assembly. We weren't checking the sign of the floating point immediate before translating it to "fmov sD, wzr". Similarly for D-regs. Technically "movi vD.2s, #0x80, lsl #24" would work most of the time, but it's not a blessed alias (and I don't think it should be since people expect writing sD to zero out the high lanes, and there's no dD equivalent). So an error it is. rdar://20455398 llvm-svn: 234372 --- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 7 ++++--- llvm/test/MC/AArch64/arm64-fp-encoding-error.s | 8 ++++++++ 2 files changed, 12 insertions(+), 3 deletions(-) create mode 100644 llvm/test/MC/AArch64/arm64-fp-encoding-error.s diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 5eec0cd..e207003 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -2090,15 +2090,16 @@ AArch64AsmParser::tryParseFPImm(OperandVector &Operands) { const AsmToken &Tok = Parser.getTok(); if (Tok.is(AsmToken::Real)) { APFloat RealVal(APFloat::IEEEdouble, Tok.getString()); + if (isNegative) + RealVal.changeSign(); + uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); - // If we had a '-' in front, toggle the sign bit. - IntVal ^= (uint64_t)isNegative << 63; int Val = AArch64_AM::getFP64Imm(APInt(64, IntVal)); Parser.Lex(); // Eat the token. // Check for out of range values. As an exception, we let Zero through, // as we handle that special case in post-processing before matching in // order to use the zero register for it. - if (Val == -1 && !RealVal.isZero()) { + if (Val == -1 && !RealVal.isPosZero()) { TokError("expected compatible register or floating-point constant"); return MatchOperand_ParseFail; } diff --git a/llvm/test/MC/AArch64/arm64-fp-encoding-error.s b/llvm/test/MC/AArch64/arm64-fp-encoding-error.s new file mode 100644 index 0000000..ad30127 --- /dev/null +++ b/llvm/test/MC/AArch64/arm64-fp-encoding-error.s @@ -0,0 +1,8 @@ +; RUN: not llvm-mc -triple arm64-apple-ios8.0 %s -o /dev/null 2>&1 | FileCheck %s + + fmov s0, #-0.0 +; CHECK: error: expected compatible register or floating-point constant + + fmov d0, #-0.0 +; CHECK: error: expected compatible register or floating-point constant + -- 2.7.4