From 5b3d632dcc2feae42d1e702bf2abc02636d30cd5 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Tue, 28 Jul 2009 11:24:32 +0900 Subject: [PATCH] s5pc110: fix clocks set correct mask of MPLL, EPLL, VPLL get HCLKs: Msys, Dsys, Psys get PCLKs: Msys, Dsys, Psys Signed-off-by: Minkyu Kang --- cpu/arm_cortexa8/s5pc1xx/clock.c | 80 +++++++++++++++++++++++++++++++++---- cpu/arm_cortexa8/s5pc1xx/cpu_info.c | 23 +++++++++-- include/asm-arm/arch-s5pc1xx/clk.h | 13 +++++- 3 files changed, 103 insertions(+), 13 deletions(-) diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c index 102dc24..69709c5 100644 --- a/cpu/arm_cortexa8/s5pc1xx/clock.c +++ b/cpu/arm_cortexa8/s5pc1xx/clock.c @@ -100,10 +100,17 @@ unsigned long get_pll_clk(int pllreg) hang(); } - if (pllreg == APLL) - mask = 0x3ff; - else - mask = 0x0ff; + if (cpu_is_s5pc110()) { + if (pllreg == APLL || pllreg == MPLL) + mask = 0x3ff; + else + mask = 0x1ff; + } else { + if (pllreg == APLL) + mask = 0x3ff; + else + mask = 0x0ff; + } m = (r >> 16) & mask; p = (r >> 8) & 0x3f; @@ -162,7 +169,7 @@ unsigned long get_mclk(void) return get_pll_clk(MPLL); } -/* return HCLKD0 frequency */ +/* s5pc100: return HCLKD0 frequency */ unsigned long get_hclk(void) { unsigned long hclkd0; @@ -177,7 +184,7 @@ unsigned long get_hclk(void) return hclkd0; } -/* return PCLKD0 frequency */ +/* s5pc100: return PCLKD0 frequency */ unsigned long get_pclkd0(void) { unsigned long pclkd0; @@ -192,8 +199,8 @@ unsigned long get_pclkd0(void) return pclkd0; } -/* return PCLKD1 frequency */ -unsigned long get_pclk(void) +/* s5pc100: return PCLKD1 frequency */ +unsigned long get_pclkd1(void) { unsigned long d1_bus, pclkd1; uint div, d1_bus_ratio, pclkd1_ratio; @@ -211,6 +218,63 @@ unsigned long get_pclk(void) return pclkd1; } +/* s5pc110: return HCLKs frequency */ +unsigned long get_hclk_sys(int clk) +{ + unsigned long hclk; + unsigned int div; + unsigned int mask; + unsigned int offset; + unsigned int hclk_sys_ratio; + + if (clk == CLK_M) + return get_hclk(); + + div = s5p1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + + /* HCLK_MSYS_RATIO: [10:8] + * HCLK_DSYS_RATIO: [19:16] + * HCLK_PSYS_RATIO: [27:24] */ + offset = 8 + clk * 8; + + hclk_sys_ratio = (div >> offset) & 0xf; + + hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); + + return hclk; +} + +/* s5pc110: return PCLKs frequency */ +unsigned long get_pclk_sys(int clk) +{ + unsigned long pclk; + unsigned int div; + unsigned int offset; + unsigned int pclk_sys_ratio; + + div = s5p1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + + /* PCLK_MSYS_RATIO: [14:12] + * PCLK_DSYS_RATIO: [22:20] + * PCLK_PSYS_RATIO: [30:28] */ + offset = 12 + clk * 8; + + pclk_sys_ratio = (div >> offset) & 0x7; + + pclk = get_hclk_sys(clk) / (pclk_sys_ratio + 1); + + return pclk; +} + +/* return peripheral clock */ +unsigned long get_pclk(void) +{ + if (cpu_is_s5pc110()) + return get_pclk_sys(CLK_P); + else + return get_pclkd1(); +} + /* return UCLK frequency */ unsigned long get_uclk(void) { diff --git a/cpu/arm_cortexa8/s5pc1xx/cpu_info.c b/cpu/arm_cortexa8/s5pc1xx/cpu_info.c index 4726eb1..bf174a6 100644 --- a/cpu/arm_cortexa8/s5pc1xx/cpu_info.c +++ b/cpu/arm_cortexa8/s5pc1xx/cpu_info.c @@ -43,10 +43,25 @@ int arch_cpu_init(void) int print_cpuinfo(void) { printf("CPU:\tS5P%X@%luMHz\n", s5pc1xx_cpu_id, get_arm_clk() / 1000000); - printf("\tFclk = %luMHz, HclkD0 = %luMHz, PclkD0 = %luMHz," - " PclkD1 = %luMHz\n", - get_fclk() / 1000000, get_hclk() / 1000000, - get_pclkd0() / 1000000, get_pclk() / 1000000); + if (cpu_is_s5pc110()) { + printf("\tAPLL = %luMHz, MPLL = %luMHz, EPLL = %luMHz\n", + get_fclk() / 1000000, + get_mclk() / 1000000, + get_uclk() / 1000000); + printf("\tHclk: Msys %luMhz, Dsys %luMhz, Psys %luMhz\n", + get_hclk_sys(CLK_M) / 1000000, + get_hclk_sys(CLK_D) / 1000000, + get_hclk_sys(CLK_P) / 1000000); + printf("\tPclk: Msys %luMhz, Dsys %luMhz, Psys %luMhz\n", + get_pclk_sys(CLK_M) / 1000000, + get_pclk_sys(CLK_D) / 1000000, + get_pclk_sys(CLK_P) / 1000000); + } else { + printf("\tFclk = %luMHz, HclkD0 = %luMHz, PclkD0 = %luMHz," + " PclkD1 = %luMHz\n", + get_fclk() / 1000000, get_hclk() / 1000000, + get_pclkd0() / 1000000, get_pclkd1() / 1000000); + } return 0; } diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h index 14f965a..ceb1e7e 100644 --- a/include/asm-arm/arch-s5pc1xx/clk.h +++ b/include/asm-arm/arch-s5pc1xx/clk.h @@ -29,8 +29,19 @@ unsigned long get_arm_clk(void); unsigned long get_fclk(void); unsigned long get_mclk(void); unsigned long get_hclk(void); -unsigned long get_pclkd0(void); unsigned long get_pclk(void); unsigned long get_uclk(void); +/*s5pc110 */ +#define CLK_M 0 +#define CLK_D 1 +#define CLK_P 2 + +unsigned long get_hclk_sys(int clk); +unsigned long get_pclk_sys(int clk); + +/* s5pc100 */ +unsigned long get_pclkd0(void); +unsigned long get_pclkd1(void); + #endif -- 2.7.4