From 5b37d8b50cfc9a390f8320557a332a3c75b91953 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 13 Nov 2015 16:21:09 -0500 Subject: [PATCH] radeonsi: use proper GRBM_GFX_INDEX offset for CI+ MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The offset is different on CI and newer. Reviewed-by: Marek Olšák Signed-off-by: Alex Deucher --- src/gallium/drivers/radeonsi/si_state.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 93847d5..f0f87da 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3256,21 +3256,29 @@ si_write_harvested_raster_configs(struct si_context *sctx, } } - /* GRBM_GFX_INDEX is privileged on VI */ - if (sctx->b.chip_class <= CIK) + /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ + if (sctx->b.chip_class < CIK) si_pm4_set_reg(pm4, GRBM_GFX_INDEX, SE_INDEX(se) | SH_BROADCAST_WRITES | INSTANCE_BROADCAST_WRITES); + else + si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX, + S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) | + S_030800_INSTANCE_BROADCAST_WRITES(1)); si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se); if (sctx->b.chip_class >= CIK) si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } - /* GRBM_GFX_INDEX is privileged on VI */ - if (sctx->b.chip_class <= CIK) + /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ + if (sctx->b.chip_class < CIK) si_pm4_set_reg(pm4, GRBM_GFX_INDEX, SE_BROADCAST_WRITES | SH_BROADCAST_WRITES | INSTANCE_BROADCAST_WRITES); + else + si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX, + S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) | + S_030800_INSTANCE_BROADCAST_WRITES(1)); } static void si_init_config(struct si_context *sctx) -- 2.7.4