From 5b32102c87fb6dc3ca178eb310ee548d33e49ddf Mon Sep 17 00:00:00 2001 From: Weining Lu Date: Thu, 7 Apr 2022 15:16:59 +0800 Subject: [PATCH] [LoongArch] Improve td files indentation a little bit. NFC --- llvm/lib/Target/LoongArch/LoongArch.td | 40 ++++++++------ llvm/lib/Target/LoongArch/LoongArchInstrFormats.td | 63 ++++++++++++++-------- llvm/lib/Target/LoongArch/LoongArchInstrInfo.td | 3 +- llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td | 3 +- 4 files changed, 69 insertions(+), 40 deletions(-) diff --git a/llvm/lib/Target/LoongArch/LoongArch.td b/llvm/lib/Target/LoongArch/LoongArch.td index 3a211bd..bf465c2 100644 --- a/llvm/lib/Target/LoongArch/LoongArch.td +++ b/llvm/lib/Target/LoongArch/LoongArch.td @@ -30,27 +30,32 @@ defvar LA32 = DefaultMode; def LA64 : HwMode<"+64bit">; // Single Precision floating point -def FeatureBasicF : SubtargetFeature<"f", "HasBasicF", "true", - "'F' (Single-Precision Floating-Point)">; -def HasBasicF : Predicate<"Subtarget->hasBasicF()">, - AssemblerPredicate<(all_of FeatureBasicF), - "'F' (Single-Precision Floating-Point)">; +def FeatureBasicF + : SubtargetFeature<"f", "HasBasicF", "true", + "'F' (Single-Precision Floating-Point)">; +def HasBasicF + : Predicate<"Subtarget->hasBasicF()">, + AssemblerPredicate<(all_of FeatureBasicF), + "'F' (Single-Precision Floating-Point)">; // Double Precision floating point -def FeatureBasicD : SubtargetFeature<"d", "HasBasicD", "true", - "'D' (Double-Precision Floating-Point)", - [FeatureBasicF]>; -def HasBasicD : Predicate<"Subtarget->hasBasicD()">, - AssemblerPredicate<(all_of FeatureBasicD), - "'D' (Double-Precision Floating-Point)">; +def FeatureBasicD + : SubtargetFeature<"d", "HasBasicD", "true", + "'D' (Double-Precision Floating-Point)", + [FeatureBasicF]>; +def HasBasicD + : Predicate<"Subtarget->hasBasicD()">, + AssemblerPredicate<(all_of FeatureBasicD), + "'D' (Double-Precision Floating-Point)">; // Loongson SIMD eXtension (LSX) def FeatureExtLSX : SubtargetFeature<"lsx", "HasExtLSX", "true", "'LSX' (Loongson SIMD Extension)", [FeatureBasicD]>; -def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">, - AssemblerPredicate<(all_of FeatureExtLSX), - "'LSX' (Loongson SIMD Extension)">; +def HasExtLSX + : Predicate<"Subtarget->hasExtLSX()">, + AssemblerPredicate<(all_of FeatureExtLSX), + "'LSX' (Loongson SIMD Extension)">; // Loongson Advanced SIMD eXtension (LASX) def FeatureExtLASX @@ -66,9 +71,10 @@ def HasExtLASX def FeatureExtLVZ : SubtargetFeature<"lvz", "HasExtLVZ", "true", "'LVZ' (Loongson Virtualization Extension)">; -def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">, - AssemblerPredicate<(all_of FeatureExtLVZ), - "'LVZ' (Loongson Virtualization Extension)">; +def HasExtLVZ + : Predicate<"Subtarget->hasExtLVZ()">, + AssemblerPredicate<(all_of FeatureExtLVZ), + "'LVZ' (Loongson Virtualization Extension)">; // Loongson Binary Translation (LBT) def FeatureExtLBT diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td index 250fc45..7c01776 100644 --- a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td +++ b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td @@ -43,7 +43,8 @@ class Pseudo pattern = [], string asmstr = ""> // 2R-type // class Fmt2R op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<5> rj; bits<5> rd; @@ -56,7 +57,8 @@ class Fmt2R op, dag outs, dag ins, string asmstr, // // class Fmt3R op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<5> rk; bits<5> rj; bits<5> rd; @@ -68,7 +70,8 @@ class Fmt3R op, dag outs, dag ins, string asmstr, } class Fmt3FR op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<5> fk; bits<5> fj; bits<5> fd; @@ -82,7 +85,8 @@ class Fmt3FR op, dag outs, dag ins, string asmstr, // 4R-type // class Fmt4R op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<5> ra; bits<5> rk; bits<5> rj; @@ -98,7 +102,8 @@ class Fmt4R op, dag outs, dag ins, string asmstr, // 3RI2-type // class Fmt3RI2 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<2> imm2; bits<5> rk; bits<5> rj; @@ -114,7 +119,8 @@ class Fmt3RI2 op, dag outs, dag ins, string asmstr, // 3RI3-type // class Fmt3RI3 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<3> imm3; bits<5> rk; bits<5> rj; @@ -130,7 +136,8 @@ class Fmt3RI3 op, dag outs, dag ins, string asmstr, // 2RI5-type // class Fmt2RI5 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<5> imm5; bits<5> rj; bits<5> rd; @@ -144,7 +151,8 @@ class Fmt2RI5 op, dag outs, dag ins, string asmstr, // 2RI6-type // class Fmt2RI6 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<6> imm6; bits<5> rj; bits<5> rd; @@ -158,7 +166,8 @@ class Fmt2RI6 op, dag outs, dag ins, string asmstr, // 2RI8-type // class Fmt2RI8 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<8> imm8; bits<5> rj; bits<5> rd; @@ -172,7 +181,8 @@ class Fmt2RI8 op, dag outs, dag ins, string asmstr, // 2RI12-type // class Fmt2RI12 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<12> imm12; bits<5> rj; bits<5> rd; @@ -186,7 +196,8 @@ class Fmt2RI12 op, dag outs, dag ins, string asmstr, // 2RI14-type // class Fmt2RI14 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<14> imm14; bits<5> rj; bits<5> rd; @@ -200,7 +211,8 @@ class Fmt2RI14 op, dag outs, dag ins, string asmstr, // 2RI16-type // class Fmt2RI16 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<16> imm16; bits<5> rj; bits<5> rd; @@ -214,7 +226,8 @@ class Fmt2RI16 op, dag outs, dag ins, string asmstr, // 1RI20-type // class Fmt1RI20 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<20> imm20; bits<5> rd; @@ -226,7 +239,8 @@ class Fmt1RI20 op, dag outs, dag ins, string asmstr, // 1RI21-type // class Fmt1RI21 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<21> imm21; bits<5> rj; @@ -239,7 +253,8 @@ class Fmt1RI21 op, dag outs, dag ins, string asmstr, // I15-type // class FmtI15 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<15> imm15; let Inst{31-15} = op; @@ -249,7 +264,8 @@ class FmtI15 op, dag outs, dag ins, string asmstr, // I26-type // class FmtI26 op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<26> imm26; let Inst{31-26} = op; @@ -260,7 +276,8 @@ class FmtI26 op, dag outs, dag ins, string asmstr, // FmtBSTR_W // class FmtBSTR_W op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<5> msbw; bits<5> lsbw; bits<5> rj; @@ -277,7 +294,8 @@ class FmtBSTR_W op, dag outs, dag ins, string asmstr, // FmtBSTR_D // class FmtBSTR_D op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<6> msbd; bits<6> lsbd; bits<5> rj; @@ -293,7 +311,8 @@ class FmtBSTR_D op, dag outs, dag ins, string asmstr, // FmtASRT // class FmtASRT op, dag outs, dag ins, string asmstr, - list pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<5> rk; bits<5> rj; @@ -306,7 +325,8 @@ class FmtASRT op, dag outs, dag ins, string asmstr, // FmtPRELD // < 0b0010101011 | I12 | rj | I5> class FmtPRELD pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<12> imm12; bits<5> rj; bits<5> imm5; @@ -320,7 +340,8 @@ class FmtPRELD class FmtPRELDX pattern = []> : LAInst { + list pattern = []> + : LAInst { bits<5> rk; bits<5> rj; bits<5> imm5; diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td index 7f839f2..755e438 100644 --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td @@ -22,7 +22,8 @@ def loongarch_ret : SDNode<"LoongArchISD::RET", SDTNone, //===----------------------------------------------------------------------===// // Operand and SDNode transformation definitions. //===----------------------------------------------------------------------===// -class ImmAsmOperand : AsmOperandClass { +class ImmAsmOperand + : AsmOperandClass { let Name = prefix # "Imm" # width # suffix; let DiagnosticType = !strconcat("Invalid", Name); let RenderMethod = "addImmOperands"; diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td index 41bef68..d55b94b 100644 --- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td @@ -24,7 +24,8 @@ class LoongArchReg32 Enc, string n, list alt = []> } def sub_32 : SubRegIndex<32>; -class LoongArchReg64 : Register<""> { +class LoongArchReg64 + : Register<""> { let HWEncoding = subreg.HWEncoding; let SubRegs = [subreg]; let SubRegIndices = [sub_32]; -- 2.7.4