From 5b1efcb719199d54012b37288e48c10255907cab Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Sun, 11 Nov 2012 21:56:27 +0000 Subject: [PATCH] sparc.h (AS_NIAGARA3_FLAG): Tweak. * config/sparc/sparc.h (AS_NIAGARA3_FLAG): Tweak. * config/sparc/sol2.h (TARGET_CPU_niagara4 support): Fix pasto. From-SVN: r193416 --- gcc/ChangeLog | 5 +++++ gcc/config/sparc/sol2.h | 4 ++-- gcc/config/sparc/sparc.h | 6 +++--- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 58d401c..568b209 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,9 @@ 2012-11-11 Eric Botcazou + + * config/sparc/sparc.h (AS_NIAGARA3_FLAG): Tweak. + * config/sparc/sol2.h (TARGET_CPU_niagara4 support): Fix pasto. + +2012-11-11 Eric Botcazou H.J. Lu PR rtl-optimization/55247 diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index ba2ec35..90dfd89 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -136,9 +136,9 @@ along with GCC; see the file COPYING3. If not see #undef CPP_CPU64_DEFAULT_SPEC #define CPP_CPU64_DEFAULT_SPEC "" #undef ASM_CPU32_DEFAULT_SPEC -#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb" +#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus" AS_NIAGARA3_FLAG #undef ASM_CPU64_DEFAULT_SPEC -#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b" +#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA3_FLAG #undef ASM_CPU_DEFAULT_SPEC #define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC #endif diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 8f86100..52e0828 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1740,10 +1740,10 @@ extern int sparc_indent_opcode; #define TARGET_SUN_TLS TARGET_TLS #define TARGET_GNU_TLS 0 -#ifndef HAVE_AS_FMAF_HPC_VIS3 -#define AS_NIAGARA3_FLAG "b" -#else +#ifdef HAVE_AS_FMAF_HPC_VIS3 #define AS_NIAGARA3_FLAG "d" +#else +#define AS_NIAGARA3_FLAG "b" #endif /* We use gcc _mcount for profiling. */ -- 2.7.4