From 5b17263b6b9d25d02581c2e44efa0c4dcad5ecf4 Mon Sep 17 00:00:00 2001 From: Dmitry Preobrazhensky Date: Mon, 28 Dec 2020 14:59:49 +0300 Subject: [PATCH] [AMDGPU][MC][NFC] Parser refactoring See bug 48515 (https://bugs.llvm.org/show_bug.cgi?id=48515) Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D93756 --- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 170 ++++++++++----------- 1 file changed, 78 insertions(+), 92 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index f6b204f..c04ea4c 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -2529,11 +2529,11 @@ bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind, int64_t OldCount; if (!Sym->isVariable()) - return !Error(getParser().getTok().getLoc(), + return !Error(getLoc(), ".amdgcn.next_free_{v,s}gpr symbols must be variable"); if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount)) return !Error( - getParser().getTok().getLoc(), + getLoc(), ".amdgcn.next_free_{v,s}gpr symbols must be absolute expressions"); if (OldCount <= NewMax) @@ -2544,7 +2544,7 @@ bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind, std::unique_ptr AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) { - const auto &Tok = Parser.getTok(); + const auto &Tok = getToken(); SMLoc StartLoc = Tok.getLoc(); SMLoc EndLoc = Tok.getEndLoc(); RegisterKind RegKind; @@ -4058,7 +4058,7 @@ bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) { int64_t Tmp = -1; - if (getLexer().isNot(AsmToken::Integer) && getLexer().isNot(AsmToken::Identifier)) { + if (!isToken(AsmToken::Integer) && !isToken(AsmToken::Identifier)) { return true; } if (getParser().parseAbsoluteExpression(Tmp)) { @@ -4088,25 +4088,24 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() { std::string Target; - SMLoc TargetStart = getTok().getLoc(); + SMLoc TargetStart = getLoc(); if (getParser().parseEscapedString(Target)) return true; - SMRange TargetRange = SMRange(TargetStart, getTok().getLoc()); + SMRange TargetRange = SMRange(TargetStart, getLoc()); std::string ExpectedTarget; raw_string_ostream ExpectedTargetOS(ExpectedTarget); IsaInfo::streamIsaVersion(&getSTI(), ExpectedTargetOS); if (Target != ExpectedTargetOS.str()) - return getParser().Error(TargetRange.Start, "target must match options", - TargetRange); + return Error(TargetRange.Start, "target must match options", TargetRange); getTargetStreamer().EmitDirectiveAMDGCNTarget(Target); return false; } bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) { - return getParser().Error(Range.Start, "value out of range", Range); + return Error(Range.Start, "value out of range", Range); } bool AMDGPUAsmParser::calculateGPRBlocks( @@ -4191,11 +4190,11 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() { return TokError(".amdhsa_ directives cannot be repeated"); Seen.insert(ID); - SMLoc ValStart = getTok().getLoc(); + SMLoc ValStart = getLoc(); int64_t IVal; if (getParser().parseAbsoluteExpression(IVal)) return true; - SMLoc ValEnd = getTok().getLoc(); + SMLoc ValEnd = getLoc(); SMRange ValRange = SMRange(ValStart, ValEnd); if (IVal < 0) @@ -4260,8 +4259,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() { UserSGPRCount += 1; } else if (ID == ".amdhsa_wavefront_size32") { if (IVersion.Major < 10) - return getParser().Error(IDRange.Start, "directive requires gfx10+", - IDRange); + return Error(IDRange.Start, "directive requires gfx10+", IDRange); EnableWavefrontSize32 = Val; PARSE_BITS_ENTRY(KD.kernel_code_properties, KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, @@ -4303,15 +4301,13 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() { ReserveVCC = Val; } else if (ID == ".amdhsa_reserve_flat_scratch") { if (IVersion.Major < 7) - return getParser().Error(IDRange.Start, "directive requires gfx7+", - IDRange); + return Error(IDRange.Start, "directive requires gfx7+", IDRange); if (!isUInt<1>(Val)) return OutOfRangeError(ValRange); ReserveFlatScr = Val; } else if (ID == ".amdhsa_reserve_xnack_mask") { if (IVersion.Major < 8) - return getParser().Error(IDRange.Start, "directive requires gfx8+", - IDRange); + return Error(IDRange.Start, "directive requires gfx8+", IDRange); if (!isUInt<1>(Val)) return OutOfRangeError(ValRange); ReserveXNACK = Val; @@ -4336,26 +4332,22 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() { Val, ValRange); } else if (ID == ".amdhsa_fp16_overflow") { if (IVersion.Major < 9) - return getParser().Error(IDRange.Start, "directive requires gfx9+", - IDRange); + return Error(IDRange.Start, "directive requires gfx9+", IDRange); PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FP16_OVFL, Val, ValRange); } else if (ID == ".amdhsa_workgroup_processor_mode") { if (IVersion.Major < 10) - return getParser().Error(IDRange.Start, "directive requires gfx10+", - IDRange); + return Error(IDRange.Start, "directive requires gfx10+", IDRange); PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_WGP_MODE, Val, ValRange); } else if (ID == ".amdhsa_memory_ordered") { if (IVersion.Major < 10) - return getParser().Error(IDRange.Start, "directive requires gfx10+", - IDRange); + return Error(IDRange.Start, "directive requires gfx10+", IDRange); PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED, Val, ValRange); } else if (ID == ".amdhsa_forward_progress") { if (IVersion.Major < 10) - return getParser().Error(IDRange.Start, "directive requires gfx10+", - IDRange); + return Error(IDRange.Start, "directive requires gfx10+", IDRange); PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS, Val, ValRange); } else if (ID == ".amdhsa_exception_fp_ieee_invalid_op") { @@ -4389,8 +4381,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() { COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO, Val, ValRange); } else { - return getParser().Error(IDRange.Start, - "unknown .amdhsa_kernel directive", IDRange); + return Error(IDRange.Start, "unknown .amdhsa_kernel directive", IDRange); } #undef PARSE_BITS_ENTRY @@ -4454,7 +4445,7 @@ bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() { // If this directive has no arguments, then use the ISA version for the // targeted GPU. - if (getLexer().is(AsmToken::EndOfStatement)) { + if (isToken(AsmToken::EndOfStatement)) { AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); getTargetStreamer().EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping, @@ -4575,14 +4566,12 @@ bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() { } bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() { - if (getLexer().isNot(AsmToken::Identifier)) - return TokError("expected symbol name"); - - StringRef KernelName = Parser.getTok().getString(); + StringRef KernelName; + if (!parseId(KernelName, "expected symbol name")) + return true; getTargetStreamer().EmitAMDGPUSymbolType(KernelName, ELF::STT_AMDGPU_HSA_KERNEL); - Lex(); KernelScope.initialize(getContext()); return false; @@ -4590,19 +4579,19 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() { bool AMDGPUAsmParser::ParseDirectiveISAVersion() { if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) { - return Error(getParser().getTok().getLoc(), + return Error(getLoc(), ".amd_amdgpu_isa directive is not available on non-amdgcn " "architectures"); } - auto ISAVersionStringFromASM = getLexer().getTok().getStringContents(); + auto ISAVersionStringFromASM = getToken().getStringContents(); std::string ISAVersionStringFromSTI; raw_string_ostream ISAVersionStreamFromSTI(ISAVersionStringFromSTI); IsaInfo::streamIsaVersion(&getSTI(), ISAVersionStreamFromSTI); if (ISAVersionStringFromASM != ISAVersionStreamFromSTI.str()) { - return Error(getParser().getTok().getLoc(), + return Error(getLoc(), ".amd_amdgpu_isa directive does not match triple and/or mcpu " "arguments specified through the command line"); } @@ -4624,7 +4613,7 @@ bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() { HSAMD::AssemblerDirectiveEnd); if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) { - return Error(getParser().getTok().getLoc(), + return Error(getLoc(), (Twine(AssemblerDirectiveBegin) + Twine(" directive is " "not available on non-amdhsa OSes")).str()); } @@ -4636,10 +4625,10 @@ bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() { if (isHsaAbiVersion3(&getSTI())) { if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString)) - return Error(getParser().getTok().getLoc(), "invalid HSA metadata"); + return Error(getLoc(), "invalid HSA metadata"); } else { if (!getTargetStreamer().EmitHSAMetadataV2(HSAMetadataString)) - return Error(getParser().getTok().getLoc(), "invalid HSA metadata"); + return Error(getLoc(), "invalid HSA metadata"); } return false; @@ -4656,9 +4645,9 @@ bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin, getLexer().setSkipSpace(false); bool FoundEnd = false; - while (!getLexer().is(AsmToken::Eof)) { - while (getLexer().is(AsmToken::Space)) { - CollectStream << getLexer().getTok().getString(); + while (!isToken(AsmToken::Eof)) { + while (isToken(AsmToken::Space)) { + CollectStream << getTokenStr(); Lex(); } @@ -4675,7 +4664,7 @@ bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin, getLexer().setSkipSpace(true); - if (getLexer().is(AsmToken::Eof) && !FoundEnd) { + if (isToken(AsmToken::Eof) && !FoundEnd) { return TokError(Twine("expected directive ") + Twine(AssemblerDirectiveEnd) + Twine(" not found")); } @@ -4693,14 +4682,14 @@ bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() { auto PALMetadata = getTargetStreamer().getPALMetadata(); if (!PALMetadata->setFromString(String)) - return Error(getParser().getTok().getLoc(), "invalid PAL metadata"); + return Error(getLoc(), "invalid PAL metadata"); return false; } /// Parse the assembler directive for old linear-format PAL metadata. bool AMDGPUAsmParser::ParseDirectivePALMetadata() { if (getSTI().getTargetTriple().getOS() != Triple::AMDPAL) { - return Error(getParser().getTok().getLoc(), + return Error(getLoc(), (Twine(PALMD::AssemblerDirective) + Twine(" directive is " "not available on non-amdpal OSes")).str()); } @@ -4735,7 +4724,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() { return true; StringRef Name; - SMLoc NameLoc = getLexer().getLoc(); + SMLoc NameLoc = getLoc(); if (getParser().parseIdentifier(Name)) return TokError("expected identifier in directive"); @@ -4746,7 +4735,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() { unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI()); int64_t Size; - SMLoc SizeLoc = getLexer().getLoc(); + SMLoc SizeLoc = getLoc(); if (getParser().parseAbsoluteExpression(Size)) return true; if (Size < 0) @@ -4756,7 +4745,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() { int64_t Alignment = 4; if (trySkipToken(AsmToken::Comma)) { - SMLoc AlignLoc = getLexer().getLoc(); + SMLoc AlignLoc = getLoc(); if (getParser().parseAbsoluteExpression(Alignment)) return true; if (Alignment < 0 || !isPowerOf2_64(Alignment)) @@ -4907,7 +4896,7 @@ AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic, // are appending default values to the Operands list. This is only done // by custom parser, so we shouldn't continue on to the generic parsing. if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail || - getLexer().is(AsmToken::EndOfStatement)) + isToken(AsmToken::EndOfStatement)) return ResTy; SMLoc RBraceLoc; @@ -4987,7 +4976,7 @@ bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Msg = (Res == MatchOperand_ParseFail) ? "failed parsing operand." : "not a valid operand."; - Error(getLexer().getLoc(), Msg); + Error(getLoc(), Msg); } while (!trySkipToken(AsmToken::EndOfStatement)) { Parser.Lex(); @@ -5081,14 +5070,14 @@ OperandMatchResultTy AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy) { int64_t Bit = 0; - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); // We are at the end of the statement, and this is a default argument, so // use a default value. - if (getLexer().isNot(AsmToken::EndOfStatement)) { - switch(getLexer().getKind()) { + if (!isToken(AsmToken::EndOfStatement)) { + switch(getTokenKind()) { case AsmToken::Identifier: { - StringRef Tok = Parser.getTok().getString(); + StringRef Tok = getTokenStr(); if (Tok == Name) { if (Tok == "r128" && !hasMIMG_R128()) Error(S, "r128 modifier is not supported on this GPU"); @@ -5135,12 +5124,9 @@ static void addOptionalImmOperand( OperandMatchResultTy AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value) { - if (!trySkipId(Prefix)) + if (!trySkipId(Prefix, AsmToken::Colon)) return MatchOperand_NoMatch; - if (!trySkipToken(AsmToken::Colon)) - return MatchOperand_ParseFail; - return parseId(Value) ? MatchOperand_Success : MatchOperand_ParseFail; } @@ -5845,17 +5831,17 @@ bool AMDGPUOperand::isSendMsg() const { //===----------------------------------------------------------------------===// OperandMatchResultTy AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) { - if (getLexer().getKind() != AsmToken::Identifier) + if (!isToken(AsmToken::Identifier)) return MatchOperand_NoMatch; - StringRef Str = Parser.getTok().getString(); + StringRef Str = getTokenStr(); int Slot = StringSwitch(Str) .Case("p10", 0) .Case("p20", 1) .Case("p0", 2) .Default(-1); - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); if (Slot == -1) return MatchOperand_ParseFail; @@ -5866,10 +5852,10 @@ OperandMatchResultTy AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) { } OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) { - if (getLexer().getKind() != AsmToken::Identifier) + if (!isToken(AsmToken::Identifier)) return MatchOperand_NoMatch; - StringRef Str = Parser.getTok().getString(); + StringRef Str = getTokenStr(); if (!Str.startswith("attr")) return MatchOperand_NoMatch; @@ -5889,7 +5875,7 @@ OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) { if (Str.getAsInteger(10, Attr)) return MatchOperand_ParseFail; - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); Parser.Lex(); if (Attr > 63) { Error(S, "out of bounds attr"); @@ -5965,19 +5951,19 @@ OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str, } OperandMatchResultTy AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) { - if (!isToken(AsmToken::Identifier)) - return MatchOperand_NoMatch; - + StringRef Str; SMLoc S = getLoc(); + if (!parseId(Str)) + return MatchOperand_NoMatch; + uint8_t Val; - auto Res = parseExpTgtImpl(getTokenStr(), Val); + auto Res = parseExpTgtImpl(Str, Val); if (Res != MatchOperand_Success) { Error(S, "invalid exp target"); return Res; } - Parser.Lex(); Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, AMDGPUOperand::ImmTyExpTgt)); return MatchOperand_Success; @@ -6209,7 +6195,7 @@ AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op, if (!skipToken(AsmToken::Comma, "expected a comma")) { return false; } - Loc = Parser.getTok().getLoc(); + Loc = getLoc(); if (!parseExpr(Op)) { return false; } @@ -6332,7 +6318,7 @@ AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) { } StringRef Ctl; - SMLoc StrLoc = Parser.getTok().getLoc(); + SMLoc StrLoc = getLoc(); if (!parseString(Ctl)) { return false; } @@ -6373,7 +6359,7 @@ AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) { bool AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) { - SMLoc OffsetLoc = Parser.getTok().getLoc(); + SMLoc OffsetLoc = getLoc(); if (!parseExpr(Imm, "a swizzle macro")) { return false; @@ -6391,7 +6377,7 @@ AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) { if (skipToken(AsmToken::LParen, "expected a left parentheses")) { - SMLoc ModeLoc = Parser.getTok().getLoc(); + SMLoc ModeLoc = getLoc(); bool Ok = false; if (trySkipId(IdSymbolic[ID_QUAD_PERM])) { @@ -6416,7 +6402,7 @@ AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) { OperandMatchResultTy AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) { - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); int64_t Imm = 0; if (trySkipId("offset")) { @@ -6461,7 +6447,7 @@ int64_t AMDGPUAsmParser::parseGPRIdxMacro() { while (true) { unsigned Mode = 0; - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) { if (trySkipId(IdSymbolic[ModeId])) { @@ -6499,7 +6485,7 @@ AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) { using namespace llvm::AMDGPU::VGPRIndexMode; int64_t Imm = 0; - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); if (trySkipId("gpr_idx", AsmToken::LParen)) { Imm = parseGPRIdxMacro(); @@ -6946,7 +6932,7 @@ OperandMatchResultTy AMDGPUAsmParser::parseOptionalOpr(OperandVector &Operands) } OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) { - StringRef Name = Parser.getTok().getString(); + StringRef Name = getTokenStr(); if (Name == "mul") { return parseIntWithPrefix("mul", Operands, AMDGPUOperand::ImmTyOModSI, ConvertOmodMul); @@ -7249,7 +7235,7 @@ OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) { if (!isGFX10Plus()) return MatchOperand_NoMatch; - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); if (!trySkipId("dim", AsmToken::Colon)) return MatchOperand_NoMatch; @@ -7257,16 +7243,16 @@ OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) { // We want to allow "dim:1D" etc., but the initial 1 is tokenized as an // integer. std::string Token; - if (getLexer().is(AsmToken::Integer)) { - SMLoc Loc = getLexer().getTok().getEndLoc(); - Token = std::string(getLexer().getTok().getString()); + if (isToken(AsmToken::Integer)) { + SMLoc Loc = getToken().getEndLoc(); + Token = std::string(getTokenStr()); Parser.Lex(); - if (getLexer().getTok().getLoc() != Loc) + if (getLoc() != Loc) return MatchOperand_ParseFail; } - if (getLexer().isNot(AsmToken::Identifier)) + if (!isToken(AsmToken::Identifier)) return MatchOperand_ParseFail; - Token += getLexer().getTok().getString(); + Token += getTokenStr(); StringRef DimId = Token; if (DimId.startswith("SQ_RSRC_IMG_")) @@ -7284,7 +7270,7 @@ OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) { } OperandMatchResultTy AMDGPUAsmParser::parseDPP8(OperandVector &Operands) { - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); if (!isGFX10Plus() || !trySkipId("dpp8", AsmToken::Colon)) return MatchOperand_NoMatch; @@ -7326,12 +7312,12 @@ OperandMatchResultTy AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) { using namespace AMDGPU::DPP; - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); StringRef Prefix; int64_t Int; - if (getLexer().getKind() == AsmToken::Identifier) { - Prefix = Parser.getTok().getString(); + if (isToken(AsmToken::Identifier)) { + Prefix = getTokenStr(); } else { return MatchOperand_NoMatch; } @@ -7368,7 +7354,7 @@ AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) { return MatchOperand_NoMatch; Parser.Lex(); - if (getLexer().isNot(AsmToken::Colon)) + if (!isToken(AsmToken::Colon)) return MatchOperand_ParseFail; if (Prefix == "quad_perm") { @@ -7529,7 +7515,7 @@ AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix, AMDGPUOperand::ImmTy Type) { using namespace llvm::AMDGPU::SDWA; - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); StringRef Value; OperandMatchResultTy res; @@ -7561,7 +7547,7 @@ OperandMatchResultTy AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) { using namespace llvm::AMDGPU::SDWA; - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); StringRef Value; OperandMatchResultTy res; @@ -7791,7 +7777,7 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op, //===----------------------------------------------------------------------===// OperandMatchResultTy AMDGPUAsmParser::parseEndpgmOp(OperandVector &Operands) { - SMLoc S = Parser.getTok().getLoc(); + SMLoc S = getLoc(); int64_t Imm = 0; if (!parseExpr(Imm)) { -- 2.7.4