From 5ac9fd64a3fe21210cf17c0517a39feb0063c106 Mon Sep 17 00:00:00 2001 From: Dmitry Preobrazhensky Date: Wed, 12 Apr 2017 16:31:18 +0000 Subject: [PATCH] [AMDGPU][MC] Corrected parsing of v_cmp_class* and v_cmpx_class* Fixed bug 32565: https://bugs.llvm.org//show_bug.cgi?id=32565 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31820 llvm-svn: 300073 --- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 4 +++- llvm/lib/Target/AMDGPU/VOPCInstructions.td | 2 +- llvm/test/MC/AMDGPU/vop3.s | 24 ++++++++++++++++++++++ 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 4ba4474..961f718 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -3702,8 +3702,10 @@ void AMDGPUAsmParser::cvtVOP3Impl(MCInst &Inst, const OperandVector &Operands, AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) { Op.addRegOrImmWithFPInputModsOperands(Inst, 2); - } else if (Op.isImm()) { + } else if (Op.isImmModifier()) { OptionalIdx[Op.getImmTy()] = I; + } else if (Op.isRegOrImm()) { + Op.addRegOrImmOperands(Inst, 1); } else { llvm_unreachable("unhandled operand type"); } diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td index c64a18a..a3550a6 100644 --- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td @@ -563,7 +563,7 @@ multiclass VOPC_CLASS_F16 : VOPC_Class_Pseudos ; multiclass VOPCX_CLASS_F16 : - VOPC_Class_Pseudos ; + VOPC_Class_Pseudos ; multiclass VOPC_CLASS_F32 : VOPC_Class_Pseudos ; diff --git a/llvm/test/MC/AMDGPU/vop3.s b/llvm/test/MC/AMDGPU/vop3.s index e8a2c5d..98cc9cc 100644 --- a/llvm/test/MC/AMDGPU/vop3.s +++ b/llvm/test/MC/AMDGPU/vop3.s @@ -400,6 +400,30 @@ v_mad_i64_i32 v[5:6], s[12:13], s1, 0, v[254:255] // VI: v_mad_i64_i32 v[5:6], s[12:13], s1, 0, v[254:255] ; encoding: [0x05,0x0c,0xe9,0xd1,0x01,0x00,0xf9,0x07] // NOSI: error: instruction not supported on this GPU +v_cmp_class_f16_e64 s[10:11], v1, s2 +// NOSICI: error: instruction not supported on this GPU +// VI: v_cmp_class_f16_e64 s[10:11], v1, s2 ; encoding: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x00,0x00] + +v_cmp_class_f32_e64 s[10:11], -v1, s2 +// SICI: v_cmp_class_f32_e64 s[10:11], -v1, s2 ; encoding: [0x0a,0x00,0x10,0xd1,0x01,0x05,0x00,0x20] +// VI: v_cmp_class_f32_e64 s[10:11], -v1, s2 ; encoding: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x00,0x20] + +v_cmp_class_f64_e64 s[10:11], -v[254:255], s2 +// SICI: v_cmp_class_f64_e64 s[10:11], -v[254:255], s2 ; encoding: [0x0a,0x00,0x50,0xd1,0xfe,0x05,0x00,0x20] +// VI: v_cmp_class_f64_e64 s[10:11], -v[254:255], s2 ; encoding: [0x0a,0x00,0x12,0xd0,0xfe,0x05,0x00,0x20] + +v_cmpx_class_f16_e64 s[10:11], v255, s2 +// NOSICI: error: instruction not supported on this GPU +// VI: v_cmpx_class_f16_e64 s[10:11], v255, s2 ; encoding: [0x0a,0x00,0x15,0xd0,0xff,0x05,0x00,0x00] + +v_cmpx_class_f32_e64 s[10:11], 0, s101 +// SICI: v_cmpx_class_f32_e64 s[10:11], 0, s101 ; encoding: [0x0a,0x00,0x30,0xd1,0x80,0xca,0x00,0x00] +// VI: v_cmpx_class_f32_e64 s[10:11], 0, s101 ; encoding: [0x0a,0x00,0x11,0xd0,0x80,0xca,0x00,0x00] + +v_cmpx_class_f64_e64 s[10:11], -v[1:2], s2 +// SICI: v_cmpx_class_f64_e64 s[10:11], -v[1:2], s2 ; encoding: [0x0a,0x00,0x70,0xd1,0x01,0x05,0x00,0x20] +// VI: v_cmpx_class_f64_e64 s[10:11], -v[1:2], s2 ; encoding: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x00,0x20] + // // Modifier tests: // -- 2.7.4