From 5ab9ae12b703647d2482e71b0a98158ef3a41dea Mon Sep 17 00:00:00 2001 From: Nitin John Raj Date: Fri, 24 Feb 2023 13:31:15 -0800 Subject: [PATCH] [RISCV] Made vrgather.vv and vrgatherei16 pseudoinstructions SEW-aware --- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 87 +++++++++++++++++----- llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td | 8 +- llvm/lib/Target/RISCV/RISCVScheduleV.td | 13 ++-- 3 files changed, 77 insertions(+), 31 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 91390fd..c385224 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -1939,6 +1939,24 @@ multiclass VPseudoBinary { + let VLMul = MInfo.value in { + defvar suffix = "_" # MInfo.MX # "_E" # sew; + def suffix : VPseudoBinaryNoMask; + def suffix # "_TU" : VPseudoBinaryNoMaskTU; + def suffix # "_MASK" : VPseudoBinaryMaskPolicy, + RISCVMaskedPseudo; + } +} + multiclass VPseudoBinaryM { + let VLMul = lmul.value in { + defvar suffix = "_" # lmul.MX # "_E" # sew # "_" # emul.MX; + def suffix : VPseudoBinaryNoMask; + def suffix # "_TU" : VPseudoBinaryNoMaskTU; + def suffix # "_MASK" : VPseudoBinaryMaskPolicy, + RISCVMaskedPseudo; + } +} + multiclass VPseudoTiedBinary { defm _VV : VPseudoBinary; } +multiclass VPseudoBinaryV_VV_E { + defm _VV : VPseudoBinary_E; +} + // Similar to VPseudoBinaryV_VV, but uses MxListF. multiclass VPseudoBinaryFV_VV { defm _VV : VPseudoBinary; @@ -1995,10 +2036,6 @@ multiclass VPseudoBinaryFV_VV { multiclass VPseudoVGTR_VV_EEW { foreach m = MxList in { defvar mx = m.MX; - defvar WriteVRGatherVV_MX = !cast("WriteVRGatherVV_" # mx); - defvar ReadVRGatherVV_data_MX = !cast("ReadVRGatherVV_data_" # mx); - defvar ReadVRGatherVV_index_MX = !cast("ReadVRGatherVV_index_" # mx); - foreach sew = EEWList in { defvar octuple_lmul = m.octuple; // emul = lmul * eew / sew @@ -2006,9 +2043,14 @@ multiclass VPseudoVGTR_VV_EEW { if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { defvar emulMX = octuple_to_str.ret; defvar emul = !cast("V_" # emulMX); - defm _VV : VPseudoBinaryEmul, - Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_data_MX, - ReadVRGatherVV_index_MX]>; + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVRGatherVV_MX_E = !cast("WriteVRGatherVV_" # mx # "_E" # e); + defvar ReadVRGatherVV_data_MX_E = !cast("ReadVRGatherVV_data_" # mx # "_E" # e); + defvar ReadVRGatherVV_index_MX_E = !cast("ReadVRGatherVV_index_" # mx # "_E" # e); + defm _VV : VPseudoBinaryEmul_E, + Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E, ReadVRGatherVV_index_MX_E]>; + } } } } @@ -2404,23 +2446,27 @@ multiclass VPseudoBinaryM_VI { multiclass VPseudoVGTR_VV_VX_VI { foreach m = MxList in { defvar mx = m.MX; - defvar WriteVRGatherVV_MX = !cast("WriteVRGatherVV_" # mx); defvar WriteVRGatherVX_MX = !cast("WriteVRGatherVX_" # mx); defvar WriteVRGatherVI_MX = !cast("WriteVRGatherVI_" # mx); - defvar ReadVRGatherVV_data_MX = !cast("ReadVRGatherVV_data_" # mx); - defvar ReadVRGatherVV_index_MX = !cast("ReadVRGatherVV_index_" # mx); defvar ReadVRGatherVX_data_MX = !cast("ReadVRGatherVX_data_" # mx); defvar ReadVRGatherVX_index_MX = !cast("ReadVRGatherVX_index_" # mx); defvar ReadVRGatherVI_data_MX = !cast("ReadVRGatherVI_data_" # mx); - defm "" : VPseudoBinaryV_VV, - Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_data_MX, - ReadVRGatherVV_index_MX, ReadVMask]>; defm "" : VPseudoBinaryV_VX, Sched<[WriteVRGatherVX_MX, ReadVRGatherVX_data_MX, ReadVRGatherVX_index_MX, ReadVMask]>; defm "" : VPseudoBinaryV_VI, Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>; + + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVRGatherVV_MX_E = !cast("WriteVRGatherVV_" # mx # "_E" # e); + defvar ReadVRGatherVV_data_MX_E = !cast("ReadVRGatherVV_data_" # mx # "_E" # e); + defvar ReadVRGatherVV_index_MX_E = !cast("ReadVRGatherVV_index_" # mx # "_E" # e); + defm "" : VPseudoBinaryV_VV_E, + Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E, + ReadVRGatherVV_index_MX_E, ReadVMask]>; + } } } @@ -4457,18 +4503,19 @@ multiclass VPatBinaryV_VV; } -multiclass VPatBinaryV_VV_INT vtilist> { foreach vti = vtilist in { defvar ivti = GetIntVTypeInfo.Vti; - defm : VPatBinaryTA; } } -multiclass VPatBinaryV_VV_INT_EEW vtilist> { foreach vti = vtilist in { // emul = lmul * eew / sew @@ -4478,7 +4525,7 @@ multiclass VPatBinaryV_VV_INT_EEW.ret; defvar ivti = !cast("VI" # eew # emul_str); - defvar inst = instruction # "_VV_" # vti.LMul.MX # "_" # emul_str; + defvar inst = instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str; defm : VPatBinaryTA vtilist, Operand ImmType = simm5> - : VPatBinaryV_VV_INT, + : VPatBinaryV_VV_INT_E, VPatBinaryV_VX_INT, VPatBinaryV_VI; @@ -6455,14 +6502,14 @@ let Predicates = [HasVInstructionsAnyF] in { let Predicates = [HasVInstructions] in { defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER", AllIntegerVectors, uimm5>; - defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16", + defm : VPatBinaryV_VV_INT_E_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16", /* eew */ 16, AllIntegerVectors>; } // Predicates = [HasVInstructions] let Predicates = [HasVInstructionsAnyF] in { defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER", AllFloatVectors, uimm5>; - defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16", + defm : VPatBinaryV_VV_INT_E_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16", /* eew */ 16, AllFloatVectors>; } // Predicates = [HasVInstructionsAnyF] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 5087628..bca0511 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -2047,7 +2047,7 @@ foreach vti = AllIntegerVectors in { vti.RegClass:$merge, (vti.Mask V0), VLOpFrag)), - (!cast("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") + (!cast("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK") vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, @@ -2073,7 +2073,7 @@ foreach vti = AllIntegerVectors in { if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { defvar emul_str = octuple_to_str.ret; defvar ivti = !cast("VI16" # emul_str); - defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; + defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str; def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, @@ -2117,7 +2117,7 @@ foreach vti = AllFloatVectors in { vti.RegClass:$merge, (vti.Mask V0), VLOpFrag)), - (!cast("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") + (!cast("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK") vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, @@ -2143,7 +2143,7 @@ foreach vti = AllFloatVectors in { if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { defvar emul_str = octuple_to_str.ret; defvar ivti = !cast("VI16" # emul_str); - defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; + defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str; def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td index 44c7b9b..0bb9279 100644 --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -383,7 +383,7 @@ defm "" : LMULSchedWrites<"WriteVISlideI">; defm "" : LMULSchedWrites<"WriteVISlide1X">; defm "" : LMULSchedWrites<"WriteVFSlide1F">; // 16.4. Vector Register Gather Instructions -defm "" : LMULSchedWrites<"WriteVRGatherVV">; +defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">; defm "" : LMULSchedWrites<"WriteVRGatherVX">; defm "" : LMULSchedWrites<"WriteVRGatherVI">; // 16.5. Vector Compress Instruction @@ -605,8 +605,8 @@ defm "" : LMULSchedReads<"ReadVISlideX">; defm "" : LMULSchedReads<"ReadVFSlideV">; defm "" : LMULSchedReads<"ReadVFSlideF">; // 16.4. Vector Register Gather Instructions -defm "" : LMULSchedReads<"ReadVRGatherVV_data">; -defm "" : LMULSchedReads<"ReadVRGatherVV_index">; +defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">; +defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">; defm "" : LMULSchedReads<"ReadVRGatherVX_data">; defm "" : LMULSchedReads<"ReadVRGatherVX_index">; defm "" : LMULSchedReads<"ReadVRGatherVI_data">; @@ -800,7 +800,7 @@ defm "" : LMULWriteRes<"WriteVISlideX", []>; defm "" : LMULWriteRes<"WriteVISlideI", []>; defm "" : LMULWriteRes<"WriteVISlide1X", []>; defm "" : LMULWriteRes<"WriteVFSlide1F", []>; -defm "" : LMULWriteRes<"WriteVRGatherVV", []>; +defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>; defm "" : LMULWriteRes<"WriteVRGatherVX", []>; defm "" : LMULWriteRes<"WriteVRGatherVI", []>; defm "" : LMULSEWWriteRes<"WriteVCompressV", []>; @@ -958,13 +958,12 @@ defm "" : LMULReadAdvance<"ReadVISlideV", 0>; defm "" : LMULReadAdvance<"ReadVISlideX", 0>; defm "" : LMULReadAdvance<"ReadVFSlideV", 0>; defm "" : LMULReadAdvance<"ReadVFSlideF", 0>; -defm "" : LMULReadAdvance<"ReadVRGatherVV_data", 0>; -defm "" : LMULReadAdvance<"ReadVRGatherVV_index", 0>; +defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>; +defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>; defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>; defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>; defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>; defm "" : LMULReadAdvance<"ReadVGatherV", 0>; -defm "" : LMULReadAdvance<"ReadVGatherX", 0>; defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>; // These are already LMUL aware def : ReadAdvance; -- 2.7.4