From 5a7efccdc31c4c70895f9afad894e40b32c6699c Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Mon, 31 Jul 2023 12:30:41 +0100 Subject: [PATCH] radv/gfx11: re-enable 0001/1110 clear values Since 87444bb7ab4b27b1394af2ac2592110b6500352b, vi_alpha_is_on_msb always returned false here. The new version matches radeonsi. Signed-off-by: Rhys Perry Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/meta/radv_meta_clear.c | 48 +++++++++++++++++------------------ 1 file changed, 23 insertions(+), 25 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index 4ff822a..67b8667 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -1565,31 +1565,29 @@ gfx11_get_fast_clear_parameters(struct radv_device *device, const struct radv_im return true; } - if (vi_alpha_is_on_msb(device, iview->vk.format)) { - if (desc->nr_channels == 2 && desc->channel[0].size == 8) { - if (value.ub[0] == 0x00 && value.ub[1] == 0xff) { - *reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM; - return true; - } else if (value.ub[0] == 0xff && value.ub[1] == 0x00) { - *reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM; - return true; - } - } else if (desc->nr_channels == 4 && desc->channel[0].size == 8) { - if (value.ub[0] == 0x00 && value.ub[1] == 0x00 && value.ub[2] == 0x00 && value.ub[3] == 0xff) { - *reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM; - return true; - } else if (value.ub[0] == 0xff && value.ub[1] == 0xff && value.ub[2] == 0xff && value.ub[3] == 0x00) { - *reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM; - return true; - } - } else if (desc->nr_channels == 4 && desc->channel[0].size == 16) { - if (value.us[0] == 0x0000 && value.us[1] == 0x0000 && value.us[2] == 0x0000 && value.us[3] == 0xffff) { - *reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM; - return true; - } else if (value.us[0] == 0xffff && value.us[1] == 0xffff && value.us[2] == 0xffff && value.us[3] == 0x0000) { - *reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM; - return true; - } + if (desc->nr_channels == 2 && desc->channel[0].size == 8) { + if (value.ub[0] == 0x00 && value.ub[1] == 0xff) { + *reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM; + return true; + } else if (value.ub[0] == 0xff && value.ub[1] == 0x00) { + *reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM; + return true; + } + } else if (desc->nr_channels == 4 && desc->channel[0].size == 8) { + if (value.ub[0] == 0x00 && value.ub[1] == 0x00 && value.ub[2] == 0x00 && value.ub[3] == 0xff) { + *reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM; + return true; + } else if (value.ub[0] == 0xff && value.ub[1] == 0xff && value.ub[2] == 0xff && value.ub[3] == 0x00) { + *reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM; + return true; + } + } else if (desc->nr_channels == 4 && desc->channel[0].size == 16) { + if (value.us[0] == 0x0000 && value.us[1] == 0x0000 && value.us[2] == 0x0000 && value.us[3] == 0xffff) { + *reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM; + return true; + } else if (value.us[0] == 0xffff && value.us[1] == 0xffff && value.us[2] == 0xffff && value.us[3] == 0x0000) { + *reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM; + return true; } } -- 2.7.4