From 5a572f4b55ab8272d731fee31ecedf375e63f1de Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 1 Aug 2019 14:06:02 -0700 Subject: [PATCH] pan/midgard: Fix REGISTER_OFFSET r27 isn't the special one, usually. Signed-off-by: Alyssa Rosenzweig --- src/panfrost/midgard/helpers.h | 3 +-- src/panfrost/midgard/midgard_compile.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/panfrost/midgard/helpers.h b/src/panfrost/midgard/helpers.h index d3ae39a..9d04b05 100644 --- a/src/panfrost/midgard/helpers.h +++ b/src/panfrost/midgard/helpers.h @@ -170,8 +170,7 @@ quadword_size(int tag) #define REGISTER_UNUSED 24 #define REGISTER_CONSTANT 26 -#define REGISTER_VARYING_BASE 26 -#define REGISTER_OFFSET 27 +#define REGISTER_LDST_BASE 26 #define REGISTER_TEXTURE_BASE 28 #define REGISTER_SELECT 31 diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 7314e67..517eabe 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -662,7 +662,7 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src) .ssa_args = { .src0 = SSA_UNUSED_1, .src1 = offset, - .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET), + .dest = SSA_FIXED_REGISTER(REGISTER_LDST_BASE + 1), }, .alu = { .op = midgard_alu_op_imov, -- 2.7.4