From 5a1c6ec1041f19806f3e94c3cb750b9072087c14 Mon Sep 17 00:00:00 2001 From: eopXD Date: Sat, 14 Jan 2023 07:06:21 -0800 Subject: [PATCH] [8/15][Clang][RISCV][NFC] Always emit PolicyAttr in riscv_vector_builtin_cg.inc The extra logic here is redundant. Also sneaked in an one-liner for emitting `IsMasked`. This is the 8th commit of a patch-set that aims to change the default policy for RVV intrinsics from TAMU to TAMA. Please refer to the cover letter in the 1st commit (D141573) for an overview. Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D141762 --- clang/utils/TableGen/RISCVVEmitter.cpp | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 59a250a..39925cc 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -163,18 +163,11 @@ void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) { OS << " ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n"; if (RVVI->getNF() >= 2) OS << " NF = " + utostr(RVVI->getNF()) + ";\n"; - // We had initialized PolicyAttrs as TU/TUMU in CodeGen function. - if (!RVVI->getPolicyAttrs().isTUPolicy() && - !RVVI->getPolicyAttrs().isTUMUPolicy() && !RVVI->hasPassthruOperand() && - !RVVI->hasManualCodegen() && RVVI->hasVL()) - OS << " PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n"; + + OS << " PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n"; if (RVVI->hasManualCodegen()) { - OS << " PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n"; - if (RVVI->isMasked()) - OS << "IsMasked = true;\n"; - else - OS << "IsMasked = false;\n"; + OS << "IsMasked = " << (RVVI->isMasked() ? "true" : "false") << ";\n"; OS << RVVI->getManualCodegen(); OS << "break;\n"; return; -- 2.7.4