From 5a0f5d483177f9d4fd89227f9d272f4109c4e17f Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Wed, 12 Oct 2016 03:57:46 +0000 Subject: [PATCH] [AArch64][InstructionSelector] Fix typos in the related mir file. NFC. llvm-svn: 283971 --- llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index af4bde9..11a277f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -1290,6 +1290,7 @@ registers: # CHECK: %2 = ADDXrr %0, %1 body: | bb.0: + liveins: %x0 %0(p0) = COPY %x0 %1(s64) = G_CONSTANT 42 %2(p0) = G_GEP %0, %1(s64) @@ -1350,7 +1351,7 @@ registers: # CHECK: %3 = COPY %2 body: | bb.0: - liveins: %x0 + liveins: %w0 %0(s32) = COPY %w0 %1(s64) = G_ANYEXT %0 @@ -1384,7 +1385,7 @@ registers: # CHECK: %3 = UBFMWri %2, 0, 7 body: | bb.0: - liveins: %x0 + liveins: %w0 %0(s32) = COPY %w0 %1(s64) = G_ZEXT %0 @@ -1418,7 +1419,7 @@ registers: # CHECK: %3 = SBFMWri %2, 0, 7 body: | bb.0: - liveins: %x0 + liveins: %w0 %0(s32) = COPY %w0 %1(s64) = G_SEXT %0 -- 2.7.4