From 59f89aa8ed86740358a495bd5cee635a84857a54 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Thu, 30 Apr 2015 09:57:37 +0000 Subject: [PATCH] [mips][msa] Rename main check prefix to 'ALL' in basic operations tests. NFC Summary: The majority of the checks are subtarget independent. The few that aren't will be corrected shortly. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9340 llvm-svn: 236220 --- llvm/test/CodeGen/Mips/msa/basic_operations.ll | 568 ++++++++++----------- .../CodeGen/Mips/msa/basic_operations_float.ll | 218 ++++---- 2 files changed, 393 insertions(+), 393 deletions(-) diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations.ll b/llvm/test/CodeGen/Mips/msa/basic_operations.ll index dcff857..f1e0b7c 100644 --- a/llvm/test/CodeGen/Mips/msa/basic_operations.ll +++ b/llvm/test/CodeGen/Mips/msa/basic_operations.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-BE %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-LE %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-BE %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-LE %s @v4i8 = global <4 x i8> @v16i8 = global <16 x i8> @@ -10,21 +10,21 @@ @i64 = global i64 0 define void @const_v16i8() nounwind { - ; MIPS32-AE-LABEL: const_v16i8: + ; ALL-LABEL: const_v16i8: store volatile <16 x i8> , <16 x i8>*@v16i8 - ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0 + ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 store volatile <16 x i8> , <16 x i8>*@v16i8 - ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1 + ; ALL: ldi.b [[R1:\$w[0-9]+]], 1 store volatile <16 x i8> , <16 x i8>*@v16i8 - ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <16 x i8> , <16 x i8>*@v16i8 - ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <16 x i8> , <16 x i8>*@v16i8 ; MIPS32-BE: ldi.h [[R1:\$w[0-9]+]], 256 @@ -35,106 +35,106 @@ define void @const_v16i8() nounwind { ; MIPS32-LE-DAG: lui [[R2:\$[0-9]+]], 1027 ; MIPS32-BE-DAG: ori [[R2]], [[R2]], 772 ; MIPS32-LE-DAG: ori [[R2]], [[R2]], 513 - ; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] + ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] store volatile <16 x i8> , <16 x i8>*@v16i8 - ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void } define void @const_v8i16() nounwind { - ; MIPS32-AE-LABEL: const_v8i16: + ; ALL-LABEL: const_v8i16: store volatile <8 x i16> , <8 x i16>*@v8i16 - ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0 + ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 store volatile <8 x i16> , <8 x i16>*@v8i16 - ; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1 + ; ALL: ldi.h [[R1:\$w[0-9]+]], 1 store volatile <8 x i16> , <8 x i16>*@v8i16 - ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <8 x i16> , <8 x i16>*@v8i16 - ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 4 + ; ALL: ldi.b [[R1:\$w[0-9]+]], 4 store volatile <8 x i16> , <8 x i16>*@v8i16 ; MIPS32-BE-DAG: lui [[R2:\$[0-9]+]], 1 ; MIPS32-LE-DAG: lui [[R2:\$[0-9]+]], 2 ; MIPS32-BE-DAG: ori [[R2]], [[R2]], 2 ; MIPS32-LE-DAG: ori [[R2]], [[R2]], 1 - ; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] + ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] store volatile <8 x i16> , <8 x i16>*@v8i16 - ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void } define void @const_v4i32() nounwind { - ; MIPS32-AE-LABEL: const_v4i32: + ; ALL-LABEL: const_v4i32: store volatile <4 x i32> , <4 x i32>*@v4i32 - ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0 + ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 store volatile <4 x i32> , <4 x i32>*@v4i32 - ; MIPS32-AE: ldi.w [[R1:\$w[0-9]+]], 1 + ; ALL: ldi.w [[R1:\$w[0-9]+]], 1 store volatile <4 x i32> , <4 x i32>*@v4i32 - ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x i32> , <4 x i32>*@v4i32 - ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1 + ; ALL: ldi.b [[R1:\$w[0-9]+]], 1 store volatile <4 x i32> , <4 x i32>*@v4i32 - ; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1 + ; ALL: ldi.h [[R1:\$w[0-9]+]], 1 store volatile <4 x i32> , <4 x i32>*@v4i32 - ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x i32> , <4 x i32>*@v4i32 - ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void } define void @const_v2i64() nounwind { - ; MIPS32-AE-LABEL: const_v2i64: + ; ALL-LABEL: const_v2i64: store volatile <2 x i64> , <2 x i64>*@v2i64 - ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0 + ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 store volatile <2 x i64> , <2 x i64>*@v2i64 - ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1 + ; ALL: ldi.b [[R1:\$w[0-9]+]], 1 store volatile <2 x i64> , <2 x i64>*@v2i64 - ; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1 + ; ALL: ldi.h [[R1:\$w[0-9]+]], 1 store volatile <2 x i64> , <2 x i64>*@v2i64 - ; MIPS32-AE: ldi.w [[R1:\$w[0-9]+]], 1 + ; ALL: ldi.w [[R1:\$w[0-9]+]], 1 store volatile <2 x i64> , <2 x i64>*@v2i64 - ; MIPS32-AE: ldi.d [[R1:\$w[0-9]+]], 1 + ; ALL: ldi.d [[R1:\$w[0-9]+]], 1 store volatile <2 x i64> , <2 x i64>*@v2i64 - ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x i64> , <2 x i64>*@v2i64 - ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void } define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind { - ; MIPS32-AE-LABEL: nonconst_v16i8: + ; ALL-LABEL: nonconst_v16i8: %1 = insertelement <16 x i8> undef, i8 %a, i32 0 %2 = insertelement <16 x i8> %1, i8 %b, i32 1 @@ -152,26 +152,26 @@ define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 sign %14 = insertelement <16 x i8> %13, i8 %h, i32 13 %15 = insertelement <16 x i8> %14, i8 %h, i32 14 %16 = insertelement <16 x i8> %15, i8 %h, i32 15 - ; MIPS32-AE-DAG: insert.b [[R1:\$w[0-9]+]][0], $4 - ; MIPS32-AE-DAG: insert.b [[R1]][1], $5 - ; MIPS32-AE-DAG: insert.b [[R1]][2], $6 - ; MIPS32-AE-DAG: insert.b [[R1]][3], $7 - ; MIPS32-AE-DAG: lw [[R2:\$[0-9]+]], 16($sp) - ; MIPS32-AE-DAG: insert.b [[R1]][4], [[R2]] - ; MIPS32-AE-DAG: lw [[R3:\$[0-9]+]], 20($sp) - ; MIPS32-AE-DAG: insert.b [[R1]][5], [[R3]] - ; MIPS32-AE-DAG: lw [[R4:\$[0-9]+]], 24($sp) - ; MIPS32-AE-DAG: insert.b [[R1]][6], [[R4]] - ; MIPS32-AE-DAG: lw [[R5:\$[0-9]+]], 28($sp) - ; MIPS32-AE-DAG: insert.b [[R1]][7], [[R5]] - ; MIPS32-AE-DAG: insert.b [[R1]][8], [[R5]] - ; MIPS32-AE-DAG: insert.b [[R1]][9], [[R5]] - ; MIPS32-AE-DAG: insert.b [[R1]][10], [[R5]] - ; MIPS32-AE-DAG: insert.b [[R1]][11], [[R5]] - ; MIPS32-AE-DAG: insert.b [[R1]][12], [[R5]] - ; MIPS32-AE-DAG: insert.b [[R1]][13], [[R5]] - ; MIPS32-AE-DAG: insert.b [[R1]][14], [[R5]] - ; MIPS32-AE-DAG: insert.b [[R1]][15], [[R5]] + ; ALL-DAG: insert.b [[R1:\$w[0-9]+]][0], $4 + ; ALL-DAG: insert.b [[R1]][1], $5 + ; ALL-DAG: insert.b [[R1]][2], $6 + ; ALL-DAG: insert.b [[R1]][3], $7 + ; ALL-DAG: lw [[R2:\$[0-9]+]], 16($sp) + ; ALL-DAG: insert.b [[R1]][4], [[R2]] + ; ALL-DAG: lw [[R3:\$[0-9]+]], 20($sp) + ; ALL-DAG: insert.b [[R1]][5], [[R3]] + ; ALL-DAG: lw [[R4:\$[0-9]+]], 24($sp) + ; ALL-DAG: insert.b [[R1]][6], [[R4]] + ; ALL-DAG: lw [[R5:\$[0-9]+]], 28($sp) + ; ALL-DAG: insert.b [[R1]][7], [[R5]] + ; ALL-DAG: insert.b [[R1]][8], [[R5]] + ; ALL-DAG: insert.b [[R1]][9], [[R5]] + ; ALL-DAG: insert.b [[R1]][10], [[R5]] + ; ALL-DAG: insert.b [[R1]][11], [[R5]] + ; ALL-DAG: insert.b [[R1]][12], [[R5]] + ; ALL-DAG: insert.b [[R1]][13], [[R5]] + ; ALL-DAG: insert.b [[R1]][14], [[R5]] + ; ALL-DAG: insert.b [[R1]][15], [[R5]] store volatile <16 x i8> %16, <16 x i8>*@v16i8 @@ -179,7 +179,7 @@ define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 sign } define void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 signext %d, i16 signext %e, i16 signext %f, i16 signext %g, i16 signext %h) nounwind { - ; MIPS32-AE-LABEL: nonconst_v8i16: + ; ALL-LABEL: nonconst_v8i16: %1 = insertelement <8 x i16> undef, i16 %a, i32 0 %2 = insertelement <8 x i16> %1, i16 %b, i32 1 @@ -189,18 +189,18 @@ define void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 %6 = insertelement <8 x i16> %5, i16 %f, i32 5 %7 = insertelement <8 x i16> %6, i16 %g, i32 6 %8 = insertelement <8 x i16> %7, i16 %h, i32 7 - ; MIPS32-AE-DAG: insert.h [[R1:\$w[0-9]+]][0], $4 - ; MIPS32-AE-DAG: insert.h [[R1]][1], $5 - ; MIPS32-AE-DAG: insert.h [[R1]][2], $6 - ; MIPS32-AE-DAG: insert.h [[R1]][3], $7 - ; MIPS32-AE-DAG: lw [[R2:\$[0-9]+]], 16($sp) - ; MIPS32-AE-DAG: insert.h [[R1]][4], [[R2]] - ; MIPS32-AE-DAG: lw [[R2:\$[0-9]+]], 20($sp) - ; MIPS32-AE-DAG: insert.h [[R1]][5], [[R2]] - ; MIPS32-AE-DAG: lw [[R2:\$[0-9]+]], 24($sp) - ; MIPS32-AE-DAG: insert.h [[R1]][6], [[R2]] - ; MIPS32-AE-DAG: lw [[R2:\$[0-9]+]], 28($sp) - ; MIPS32-AE-DAG: insert.h [[R1]][7], [[R2]] + ; ALL-DAG: insert.h [[R1:\$w[0-9]+]][0], $4 + ; ALL-DAG: insert.h [[R1]][1], $5 + ; ALL-DAG: insert.h [[R1]][2], $6 + ; ALL-DAG: insert.h [[R1]][3], $7 + ; ALL-DAG: lw [[R2:\$[0-9]+]], 16($sp) + ; ALL-DAG: insert.h [[R1]][4], [[R2]] + ; ALL-DAG: lw [[R2:\$[0-9]+]], 20($sp) + ; ALL-DAG: insert.h [[R1]][5], [[R2]] + ; ALL-DAG: lw [[R2:\$[0-9]+]], 24($sp) + ; ALL-DAG: insert.h [[R1]][6], [[R2]] + ; ALL-DAG: lw [[R2:\$[0-9]+]], 28($sp) + ; ALL-DAG: insert.h [[R1]][7], [[R2]] store volatile <8 x i16> %8, <8 x i16>*@v8i16 @@ -208,16 +208,16 @@ define void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 } define void @nonconst_v4i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { - ; MIPS32-AE-LABEL: nonconst_v4i32: + ; ALL-LABEL: nonconst_v4i32: %1 = insertelement <4 x i32> undef, i32 %a, i32 0 %2 = insertelement <4 x i32> %1, i32 %b, i32 1 %3 = insertelement <4 x i32> %2, i32 %c, i32 2 %4 = insertelement <4 x i32> %3, i32 %d, i32 3 - ; MIPS32-AE: insert.w [[R1:\$w[0-9]+]][0], $4 - ; MIPS32-AE: insert.w [[R1]][1], $5 - ; MIPS32-AE: insert.w [[R1]][2], $6 - ; MIPS32-AE: insert.w [[R1]][3], $7 + ; ALL: insert.w [[R1:\$w[0-9]+]][0], $4 + ; ALL: insert.w [[R1]][1], $5 + ; ALL: insert.w [[R1]][2], $6 + ; ALL: insert.w [[R1]][3], $7 store volatile <4 x i32> %4, <4 x i32>*@v4i32 @@ -225,14 +225,14 @@ define void @nonconst_v4i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 } define void @nonconst_v2i64(i64 signext %a, i64 signext %b) nounwind { - ; MIPS32-AE-LABEL: nonconst_v2i64: + ; ALL-LABEL: nonconst_v2i64: %1 = insertelement <2 x i64> undef, i64 %a, i32 0 %2 = insertelement <2 x i64> %1, i64 %b, i32 1 - ; MIPS32-AE: insert.w [[R1:\$w[0-9]+]][0], $4 - ; MIPS32-AE: insert.w [[R1]][1], $5 - ; MIPS32-AE: insert.w [[R1]][2], $6 - ; MIPS32-AE: insert.w [[R1]][3], $7 + ; ALL: insert.w [[R1:\$w[0-9]+]][0], $4 + ; ALL: insert.w [[R1]][1], $5 + ; ALL: insert.w [[R1]][2], $6 + ; ALL: insert.w [[R1]][3], $7 store volatile <2 x i64> %2, <2 x i64>*@v2i64 @@ -240,524 +240,524 @@ define void @nonconst_v2i64(i64 signext %a, i64 signext %b) nounwind { } define i32 @extract_sext_v16i8() nounwind { - ; MIPS32-AE-LABEL: extract_sext_v16i8: + ; ALL-LABEL: extract_sext_v16i8: %1 = load <16 x i8>, <16 x i8>* @v16i8 - ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], %2 = add <16 x i8> %1, %1 - ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <16 x i8> %2, i32 1 %4 = sext i8 %3 to i32 - ; MIPS32-AE-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1] - ; MIPS32-AE-NOT: sll - ; MIPS32-AE-NOT: sra + ; ALL-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1] + ; ALL-NOT: sll + ; ALL-NOT: sra ret i32 %4 } define i32 @extract_sext_v8i16() nounwind { - ; MIPS32-AE-LABEL: extract_sext_v8i16: + ; ALL-LABEL: extract_sext_v8i16: %1 = load <8 x i16>, <8 x i16>* @v8i16 - ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], %2 = add <8 x i16> %1, %1 - ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <8 x i16> %2, i32 1 %4 = sext i16 %3 to i32 - ; MIPS32-AE-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1] - ; MIPS32-AE-NOT: sll - ; MIPS32-AE-NOT: sra + ; ALL-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1] + ; ALL-NOT: sll + ; ALL-NOT: sra ret i32 %4 } define i32 @extract_sext_v4i32() nounwind { - ; MIPS32-AE-LABEL: extract_sext_v4i32: + ; ALL-LABEL: extract_sext_v4i32: %1 = load <4 x i32>, <4 x i32>* @v4i32 - ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], %2 = add <4 x i32> %1, %1 - ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <4 x i32> %2, i32 1 - ; MIPS32-AE-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1] + ; ALL-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1] ret i32 %3 } define i64 @extract_sext_v2i64() nounwind { - ; MIPS32-AE-LABEL: extract_sext_v2i64: + ; ALL-LABEL: extract_sext_v2i64: %1 = load <2 x i64>, <2 x i64>* @v2i64 - ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], %2 = add <2 x i64> %1, %1 - ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <2 x i64> %2, i32 1 - ; MIPS32-AE-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2] - ; MIPS32-AE-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3] - ; MIPS32-AE-NOT: sll - ; MIPS32-AE-NOT: sra + ; ALL-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2] + ; ALL-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3] + ; ALL-NOT: sll + ; ALL-NOT: sra ret i64 %3 } define i32 @extract_zext_v16i8() nounwind { - ; MIPS32-AE-LABEL: extract_zext_v16i8: + ; ALL-LABEL: extract_zext_v16i8: %1 = load <16 x i8>, <16 x i8>* @v16i8 - ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], %2 = add <16 x i8> %1, %1 - ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <16 x i8> %2, i32 1 %4 = zext i8 %3 to i32 - ; MIPS32-AE-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1] - ; MIPS32-AE-NOT: andi + ; ALL-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1] + ; ALL-NOT: andi ret i32 %4 } define i32 @extract_zext_v8i16() nounwind { - ; MIPS32-AE-LABEL: extract_zext_v8i16: + ; ALL-LABEL: extract_zext_v8i16: %1 = load <8 x i16>, <8 x i16>* @v8i16 - ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], %2 = add <8 x i16> %1, %1 - ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <8 x i16> %2, i32 1 %4 = zext i16 %3 to i32 - ; MIPS32-AE-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1] - ; MIPS32-AE-NOT: andi + ; ALL-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1] + ; ALL-NOT: andi ret i32 %4 } define i32 @extract_zext_v4i32() nounwind { - ; MIPS32-AE-LABEL: extract_zext_v4i32: + ; ALL-LABEL: extract_zext_v4i32: %1 = load <4 x i32>, <4 x i32>* @v4i32 - ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], %2 = add <4 x i32> %1, %1 - ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <4 x i32> %2, i32 1 - ; MIPS32-AE-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1] + ; ALL-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1] ret i32 %3 } define i64 @extract_zext_v2i64() nounwind { - ; MIPS32-AE-LABEL: extract_zext_v2i64: + ; ALL-LABEL: extract_zext_v2i64: %1 = load <2 x i64>, <2 x i64>* @v2i64 - ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], %2 = add <2 x i64> %1, %1 - ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <2 x i64> %2, i32 1 - ; MIPS32-AE-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2] - ; MIPS32-AE-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3] - ; MIPS32-AE-NOT: andi + ; ALL-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2] + ; ALL-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3] + ; ALL-NOT: andi ret i64 %3 } define i32 @extract_sext_v16i8_vidx() nounwind { - ; MIPS32-AE-LABEL: extract_sext_v16i8_vidx: + ; ALL-LABEL: extract_sext_v16i8_vidx: %1 = load <16 x i8>, <16 x i8>* @v16i8 - ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)( - ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)( + ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = add <16 x i8> %1, %1 - ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <16 x i8> %2, i32 %3 %5 = sext i8 %4 to i32 - ; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] - ; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24 + ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] + ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24 ret i32 %5 } define i32 @extract_sext_v8i16_vidx() nounwind { - ; MIPS32-AE-LABEL: extract_sext_v8i16_vidx: + ; ALL-LABEL: extract_sext_v8i16_vidx: %1 = load <8 x i16>, <8 x i16>* @v8i16 - ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)( - ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)( + ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = add <8 x i16> %1, %1 - ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <8 x i16> %2, i32 %3 %5 = sext i16 %4 to i32 - ; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] - ; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16 + ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] + ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16 ret i32 %5 } define i32 @extract_sext_v4i32_vidx() nounwind { - ; MIPS32-AE-LABEL: extract_sext_v4i32_vidx: + ; ALL-LABEL: extract_sext_v4i32_vidx: %1 = load <4 x i32>, <4 x i32>* @v4i32 - ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)( - ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)( + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = add <4 x i32> %1, %1 - ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <4 x i32> %2, i32 %3 - ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] - ; MIPS32-AE-NOT: sra + ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] + ; ALL-NOT: sra ret i32 %4 } define i64 @extract_sext_v2i64_vidx() nounwind { - ; MIPS32-AE-LABEL: extract_sext_v2i64_vidx: + ; ALL-LABEL: extract_sext_v2i64_vidx: %1 = load <2 x i64>, <2 x i64>* @v2i64 - ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)( - ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)( + ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = add <2 x i64> %1, %1 - ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <2 x i64> %2, i32 %3 - ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] - ; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]] - ; MIPS32-AE-NOT: sra + ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] + ; ALL-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]] + ; ALL-NOT: sra ret i64 %4 } define i32 @extract_zext_v16i8_vidx() nounwind { - ; MIPS32-AE-LABEL: extract_zext_v16i8_vidx: + ; ALL-LABEL: extract_zext_v16i8_vidx: %1 = load <16 x i8>, <16 x i8>* @v16i8 - ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)( - ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)( + ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = add <16 x i8> %1, %1 - ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <16 x i8> %2, i32 %3 %5 = zext i8 %4 to i32 - ; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] - ; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24 + ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] + ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24 ret i32 %5 } define i32 @extract_zext_v8i16_vidx() nounwind { - ; MIPS32-AE-LABEL: extract_zext_v8i16_vidx: + ; ALL-LABEL: extract_zext_v8i16_vidx: %1 = load <8 x i16>, <8 x i16>* @v8i16 - ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)( - ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)( + ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = add <8 x i16> %1, %1 - ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <8 x i16> %2, i32 %3 %5 = zext i16 %4 to i32 - ; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] - ; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16 + ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] + ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16 ret i32 %5 } define i32 @extract_zext_v4i32_vidx() nounwind { - ; MIPS32-AE-LABEL: extract_zext_v4i32_vidx: + ; ALL-LABEL: extract_zext_v4i32_vidx: %1 = load <4 x i32>, <4 x i32>* @v4i32 - ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)( - ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)( + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = add <4 x i32> %1, %1 - ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <4 x i32> %2, i32 %3 - ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] - ; MIPS32-AE-NOT: srl + ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] + ; ALL-NOT: srl ret i32 %4 } define i64 @extract_zext_v2i64_vidx() nounwind { - ; MIPS32-AE-LABEL: extract_zext_v2i64_vidx: + ; ALL-LABEL: extract_zext_v2i64_vidx: %1 = load <2 x i64>, <2 x i64>* @v2i64 - ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)( - ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)( + ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = add <2 x i64> %1, %1 - ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <2 x i64> %2, i32 %3 - ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] - ; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]] - ; MIPS32-AE-NOT: srl + ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] + ; ALL-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]] + ; ALL-NOT: srl ret i64 %4 } define void @insert_v16i8(i32 signext %a) nounwind { - ; MIPS32-AE-LABEL: insert_v16i8: + ; ALL-LABEL: insert_v16i8: %1 = load <16 x i8>, <16 x i8>* @v16i8 - ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], %a2 = trunc i32 %a to i8 %a3 = sext i8 %a2 to i32 %a4 = trunc i32 %a3 to i8 - ; MIPS32-AE-NOT: andi - ; MIPS32-AE-NOT: sra + ; ALL-NOT: andi + ; ALL-NOT: sra %2 = insertelement <16 x i8> %1, i8 %a4, i32 1 - ; MIPS32-AE-DAG: insert.b [[R1]][1], $4 + ; ALL-DAG: insert.b [[R1]][1], $4 store <16 x i8> %2, <16 x i8>* @v16i8 - ; MIPS32-AE-DAG: st.b [[R1]] + ; ALL-DAG: st.b [[R1]] ret void } define void @insert_v8i16(i32 signext %a) nounwind { - ; MIPS32-AE-LABEL: insert_v8i16: + ; ALL-LABEL: insert_v8i16: %1 = load <8 x i16>, <8 x i16>* @v8i16 - ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], %a2 = trunc i32 %a to i16 %a3 = sext i16 %a2 to i32 %a4 = trunc i32 %a3 to i16 - ; MIPS32-AE-NOT: andi - ; MIPS32-AE-NOT: sra + ; ALL-NOT: andi + ; ALL-NOT: sra %2 = insertelement <8 x i16> %1, i16 %a4, i32 1 - ; MIPS32-AE-DAG: insert.h [[R1]][1], $4 + ; ALL-DAG: insert.h [[R1]][1], $4 store <8 x i16> %2, <8 x i16>* @v8i16 - ; MIPS32-AE-DAG: st.h [[R1]] + ; ALL-DAG: st.h [[R1]] ret void } define void @insert_v4i32(i32 signext %a) nounwind { - ; MIPS32-AE-LABEL: insert_v4i32: + ; ALL-LABEL: insert_v4i32: %1 = load <4 x i32>, <4 x i32>* @v4i32 - ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], - ; MIPS32-AE-NOT: andi - ; MIPS32-AE-NOT: sra + ; ALL-NOT: andi + ; ALL-NOT: sra %2 = insertelement <4 x i32> %1, i32 %a, i32 1 - ; MIPS32-AE-DAG: insert.w [[R1]][1], $4 + ; ALL-DAG: insert.w [[R1]][1], $4 store <4 x i32> %2, <4 x i32>* @v4i32 - ; MIPS32-AE-DAG: st.w [[R1]] + ; ALL-DAG: st.w [[R1]] ret void } define void @insert_v2i64(i64 signext %a) nounwind { - ; MIPS32-AE-LABEL: insert_v2i64: + ; ALL-LABEL: insert_v2i64: %1 = load <2 x i64>, <2 x i64>* @v2i64 - ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], - ; MIPS32-AE-NOT: andi - ; MIPS32-AE-NOT: sra + ; ALL-NOT: andi + ; ALL-NOT: sra %2 = insertelement <2 x i64> %1, i64 %a, i32 1 - ; MIPS32-AE-DAG: insert.w [[R1]][2], $4 - ; MIPS32-AE-DAG: insert.w [[R1]][3], $5 + ; ALL-DAG: insert.w [[R1]][2], $4 + ; ALL-DAG: insert.w [[R1]][3], $5 store <2 x i64> %2, <2 x i64>* @v2i64 - ; MIPS32-AE-DAG: st.w [[R1]] + ; ALL-DAG: st.w [[R1]] ret void } define void @insert_v16i8_vidx(i32 signext %a) nounwind { - ; MIPS32-AE-LABEL: insert_v16i8_vidx: + ; ALL-LABEL: insert_v16i8_vidx: %1 = load <16 x i8>, <16 x i8>* @v16i8 - ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], %2 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %a2 = trunc i32 %a to i8 %a3 = sext i8 %a2 to i32 %a4 = trunc i32 %a3 to i8 - ; MIPS32-AE-NOT: andi - ; MIPS32-AE-NOT: sra + ; ALL-NOT: andi + ; ALL-NOT: sra %3 = insertelement <16 x i8> %1, i8 %a4, i32 %2 - ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]] - ; MIPS32-AE-DAG: insert.b [[R1]][0], $4 - ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]] - ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: insert.b [[R1]][0], $4 + ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]] + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] store <16 x i8> %3, <16 x i8>* @v16i8 - ; MIPS32-AE-DAG: st.b [[R1]] + ; ALL-DAG: st.b [[R1]] ret void } define void @insert_v8i16_vidx(i32 %a) nounwind { - ; MIPS32-AE-LABEL: insert_v8i16_vidx: + ; ALL-LABEL: insert_v8i16_vidx: %1 = load <8 x i16>, <8 x i16>* @v8i16 - ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], %2 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %a2 = trunc i32 %a to i16 %a3 = sext i16 %a2 to i32 %a4 = trunc i32 %a3 to i16 - ; MIPS32-AE-NOT: andi - ; MIPS32-AE-NOT: sra + ; ALL-NOT: andi + ; ALL-NOT: sra %3 = insertelement <8 x i16> %1, i16 %a4, i32 %2 - ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 1 - ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] - ; MIPS32-AE-DAG: insert.h [[R1]][0], $4 - ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] - ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] + ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 1 + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] + ; ALL-DAG: insert.h [[R1]][0], $4 + ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] store <8 x i16> %3, <8 x i16>* @v8i16 - ; MIPS32-AE-DAG: st.h [[R1]] + ; ALL-DAG: st.h [[R1]] ret void } define void @insert_v4i32_vidx(i32 signext %a) nounwind { - ; MIPS32-AE-LABEL: insert_v4i32_vidx: + ; ALL-LABEL: insert_v4i32_vidx: %1 = load <4 x i32>, <4 x i32>* @v4i32 - ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], %2 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) - ; MIPS32-AE-NOT: andi - ; MIPS32-AE-NOT: sra + ; ALL-NOT: andi + ; ALL-NOT: sra %3 = insertelement <4 x i32> %1, i32 %a, i32 %2 - ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 - ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] - ; MIPS32-AE-DAG: insert.w [[R1]][0], $4 - ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] - ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] + ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] + ; ALL-DAG: insert.w [[R1]][0], $4 + ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] store <4 x i32> %3, <4 x i32>* @v4i32 - ; MIPS32-AE-DAG: st.w [[R1]] + ; ALL-DAG: st.w [[R1]] ret void } define void @insert_v2i64_vidx(i64 signext %a) nounwind { - ; MIPS32-AE-LABEL: insert_v2i64_vidx: + ; ALL-LABEL: insert_v2i64_vidx: %1 = load <2 x i64>, <2 x i64>* @v2i64 - ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], %2 = load i32, i32* @i32 - ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) - ; MIPS32-AE-NOT: andi - ; MIPS32-AE-NOT: sra + ; ALL-NOT: andi + ; ALL-NOT: sra %3 = insertelement <2 x i64> %1, i64 %a, i32 %2 ; TODO: This code could be a lot better but it works. The legalizer splits ; 64-bit inserts into two 32-bit inserts because there is no i64 type on ; MIPS32. The obvious optimisation is to perform both insert.w's at once while ; the vector is rotated. - ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 - ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] - ; MIPS32-AE-DAG: insert.w [[R1]][0], $4 - ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] - ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] - ; MIPS32-AE-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1 - ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2 - ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] - ; MIPS32-AE-DAG: insert.w [[R1]][0], $5 - ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] - ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] + ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] + ; ALL-DAG: insert.w [[R1]][0], $4 + ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] + ; ALL-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1 + ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2 + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] + ; ALL-DAG: insert.w [[R1]][0], $5 + ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] store <2 x i64> %3, <2 x i64>* @v2i64 - ; MIPS32-AE-DAG: st.w [[R1]] + ; ALL-DAG: st.w [[R1]] ret void } define void @truncstore() nounwind { - ; MIPS32-AE-LABEL: truncstore: + ; ALL-LABEL: truncstore: store volatile <4 x i8> , <4 x i8>*@v4i8 ; TODO: What code should be emitted? diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll index 3f81993..a35bde1 100644 --- a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll +++ b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL %s @v4f32 = global <4 x float> @v2f64 = global <2 x double> @@ -8,70 +8,70 @@ @f64 = global double 0.0 define void @const_v4f32() nounwind { - ; MIPS32-LABEL: const_v4f32: + ; ALL-LABEL: const_v4f32: store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0 + ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: lui [[R1:\$[0-9]+]], 16256 - ; MIPS32: fill.w [[R2:\$w[0-9]+]], [[R1]] + ; ALL: lui [[R1:\$[0-9]+]], 16256 + ; ALL: fill.w [[R2:\$w[0-9]+]], [[R1]] store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: lui [[R1:\$[0-9]+]], 18304 - ; MIPS32: ori [[R2:\$[0-9]+]], [[R1]], 128 - ; MIPS32: fill.w [[R3:\$w[0-9]+]], [[R2]] + ; ALL: lui [[R1:\$[0-9]+]], 18304 + ; ALL: ori [[R2:\$[0-9]+]], [[R1]], 128 + ; ALL: fill.w [[R3:\$w[0-9]+]], [[R2]] store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void } define void @const_v2f64() nounwind { - ; MIPS32-LABEL: const_v2f64: + ; ALL-LABEL: const_v2f64: store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0 + ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void } define void @nonconst_v4f32() nounwind { - ; MIPS32-LABEL: nonconst_v4f32: + ; ALL-LABEL: nonconst_v4f32: %1 = load float , float *@f32 %2 = insertelement <4 x float> undef, float %1, i32 0 @@ -79,236 +79,236 @@ define void @nonconst_v4f32() nounwind { %4 = insertelement <4 x float> %3, float %1, i32 2 %5 = insertelement <4 x float> %4, float %1, i32 3 store volatile <4 x float> %5, <4 x float>*@v4f32 - ; MIPS32: lwc1 $f[[R1:[0-9]+]], 0( - ; MIPS32: splati.w [[R2:\$w[0-9]+]], $w[[R1]] + ; ALL: lwc1 $f[[R1:[0-9]+]], 0( + ; ALL: splati.w [[R2:\$w[0-9]+]], $w[[R1]] ret void } define void @nonconst_v2f64() nounwind { - ; MIPS32-LABEL: nonconst_v2f64: + ; ALL-LABEL: nonconst_v2f64: %1 = load double , double *@f64 %2 = insertelement <2 x double> undef, double %1, i32 0 %3 = insertelement <2 x double> %2, double %1, i32 1 store volatile <2 x double> %3, <2 x double>*@v2f64 - ; MIPS32: ldc1 $f[[R1:[0-9]+]], 0( - ; MIPS32: splati.d [[R2:\$w[0-9]+]], $w[[R1]] + ; ALL: ldc1 $f[[R1:[0-9]+]], 0( + ; ALL: splati.d [[R2:\$w[0-9]+]], $w[[R1]] ret void } define float @extract_v4f32() nounwind { - ; MIPS32-LABEL: extract_v4f32: + ; ALL-LABEL: extract_v4f32: %1 = load <4 x float>, <4 x float>* @v4f32 - ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], %2 = fadd <4 x float> %1, %1 - ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <4 x float> %2, i32 1 ; Element 1 can be obtained by splatting it across the vector and extracting ; $w0:sub_lo - ; MIPS32-DAG: splati.w $w0, [[R1]][1] + ; ALL-DAG: splati.w $w0, [[R1]][1] ret float %3 } define float @extract_v4f32_elt0() nounwind { - ; MIPS32-LABEL: extract_v4f32_elt0: + ; ALL-LABEL: extract_v4f32_elt0: %1 = load <4 x float>, <4 x float>* @v4f32 - ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], %2 = fadd <4 x float> %1, %1 - ; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]] + ; ALL-DAG: fadd.w $w0, [[R1]], [[R1]] %3 = extractelement <4 x float> %2, i32 0 ; Element 0 can be obtained by extracting $w0:sub_lo ($f0) - ; MIPS32-NOT: copy_u.w - ; MIPS32-NOT: mtc1 + ; ALL-NOT: copy_u.w + ; ALL-NOT: mtc1 ret float %3 } define float @extract_v4f32_elt2() nounwind { - ; MIPS32-LABEL: extract_v4f32_elt2: + ; ALL-LABEL: extract_v4f32_elt2: %1 = load <4 x float>, <4 x float>* @v4f32 - ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], %2 = fadd <4 x float> %1, %1 - ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <4 x float> %2, i32 2 ; Element 2 can be obtained by splatting it across the vector and extracting ; $w0:sub_lo - ; MIPS32-DAG: splati.w $w0, [[R1]][2] + ; ALL-DAG: splati.w $w0, [[R1]][2] ret float %3 } define float @extract_v4f32_vidx() nounwind { - ; MIPS32-LABEL: extract_v4f32_vidx: + ; ALL-LABEL: extract_v4f32_vidx: %1 = load <4 x float>, <4 x float>* @v4f32 - ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( - ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = fadd <4 x float> %1, %1 - ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <4 x float> %2, i32 %3 - ; MIPS32-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]] ret float %4 } define double @extract_v2f64() nounwind { - ; MIPS32-LABEL: extract_v2f64: + ; ALL-LABEL: extract_v2f64: %1 = load <2 x double>, <2 x double>* @v2f64 - ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], %2 = fadd <2 x double> %1, %1 - ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = extractelement <2 x double> %2, i32 1 ; Element 1 can be obtained by splatting it across the vector and extracting ; $w0:sub_64 - ; MIPS32-DAG: splati.d $w0, [[R1]][1] - ; MIPS32-NOT: copy_u.w - ; MIPS32-NOT: mtc1 - ; MIPS32-NOT: mthc1 - ; MIPS32-NOT: sll - ; MIPS32-NOT: sra + ; ALL-DAG: splati.d $w0, [[R1]][1] + ; ALL-NOT: copy_u.w + ; ALL-NOT: mtc1 + ; ALL-NOT: mthc1 + ; ALL-NOT: sll + ; ALL-NOT: sra ret double %3 } define double @extract_v2f64_elt0() nounwind { - ; MIPS32-LABEL: extract_v2f64_elt0: + ; ALL-LABEL: extract_v2f64_elt0: %1 = load <2 x double>, <2 x double>* @v2f64 - ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], %2 = fadd <2 x double> %1, %1 - ; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]] + ; ALL-DAG: fadd.d $w0, [[R1]], [[R1]] %3 = extractelement <2 x double> %2, i32 0 ; Element 0 can be obtained by extracting $w0:sub_64 ($f0) - ; MIPS32-NOT: copy_u.w - ; MIPS32-NOT: mtc1 - ; MIPS32-NOT: mthc1 - ; MIPS32-NOT: sll - ; MIPS32-NOT: sra + ; ALL-NOT: copy_u.w + ; ALL-NOT: mtc1 + ; ALL-NOT: mthc1 + ; ALL-NOT: sll + ; ALL-NOT: sra ret double %3 } define double @extract_v2f64_vidx() nounwind { - ; MIPS32-LABEL: extract_v2f64_vidx: + ; ALL-LABEL: extract_v2f64_vidx: %1 = load <2 x double>, <2 x double>* @v2f64 - ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( - ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( + ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = fadd <2 x double> %1, %1 - ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] + ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <2 x double> %2, i32 %3 - ; MIPS32-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]] + ; ALL-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]] ret double %4 } define void @insert_v4f32(float %a) nounwind { - ; MIPS32-LABEL: insert_v4f32: + ; ALL-LABEL: insert_v4f32: %1 = load <4 x float>, <4 x float>* @v4f32 - ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], %2 = insertelement <4 x float> %1, float %a, i32 1 ; float argument passed in $f12 - ; MIPS32-DAG: insve.w [[R1]][1], $w12[0] + ; ALL-DAG: insve.w [[R1]][1], $w12[0] store <4 x float> %2, <4 x float>* @v4f32 - ; MIPS32-DAG: st.w [[R1]] + ; ALL-DAG: st.w [[R1]] ret void } define void @insert_v2f64(double %a) nounwind { - ; MIPS32-LABEL: insert_v2f64: + ; ALL-LABEL: insert_v2f64: %1 = load <2 x double>, <2 x double>* @v2f64 - ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], + ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], %2 = insertelement <2 x double> %1, double %a, i32 1 ; double argument passed in $f12 - ; MIPS32-DAG: insve.d [[R1]][1], $w12[0] + ; ALL-DAG: insve.d [[R1]][1], $w12[0] store <2 x double> %2, <2 x double>* @v2f64 - ; MIPS32-DAG: st.d [[R1]] + ; ALL-DAG: st.d [[R1]] ret void } define void @insert_v4f32_vidx(float %a) nounwind { - ; MIPS32-LABEL: insert_v4f32_vidx: + ; ALL-LABEL: insert_v4f32_vidx: %1 = load <4 x float>, <4 x float>* @v4f32 - ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( - ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( + ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = load i32, i32* @i32 - ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %3 = insertelement <4 x float> %1, float %a, i32 %2 ; float argument passed in $f12 - ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 - ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] - ; MIPS32-DAG: insve.w [[R1]][0], $w12[0] - ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] - ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] + ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] + ; ALL-DAG: insve.w [[R1]][0], $w12[0] + ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] store <4 x float> %3, <4 x float>* @v4f32 - ; MIPS32-DAG: st.w [[R1]] + ; ALL-DAG: st.w [[R1]] ret void } define void @insert_v2f64_vidx(double %a) nounwind { - ; MIPS32-LABEL: insert_v2f64_vidx: + ; ALL-LABEL: insert_v2f64_vidx: %1 = load <2 x double>, <2 x double>* @v2f64 - ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( - ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) + ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( + ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = load i32, i32* @i32 - ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( - ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) + ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %3 = insertelement <2 x double> %1, double %a, i32 %2 ; double argument passed in $f12 - ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3 - ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] - ; MIPS32-DAG: insve.d [[R1]][0], $w12[0] - ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] - ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] + ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3 + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] + ; ALL-DAG: insve.d [[R1]][0], $w12[0] + ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] + ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] store <2 x double> %3, <2 x double>* @v2f64 - ; MIPS32-DAG: st.d [[R1]] + ; ALL-DAG: st.d [[R1]] ret void } -- 2.7.4