From 59a2a4f87fa6a3ee8c08c8128e69f5b23e70914f Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 27 Mar 2023 14:18:57 +0200 Subject: [PATCH] radv: pass a shaders array to radv_get_shader() Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 20 ++++++------ src/amd/vulkan/radv_debug.c | 2 +- src/amd/vulkan/radv_device_generated_commands.c | 2 +- src/amd/vulkan/radv_pipeline.c | 41 +++++++++++++------------ src/amd/vulkan/radv_private.h | 2 +- 5 files changed, 34 insertions(+), 33 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 75ac3ed..202e0b7 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2461,7 +2461,7 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer) (cmd_buffer->state.tess_num_patches << 6) | d->vk.ts.patch_control_points); const struct radv_userdata_info *num_patches = radv_get_user_sgpr( - radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL), AC_UD_TES_NUM_PATCHES); + radv_get_shader(pipeline->base.shaders, MESA_SHADER_TESS_EVAL), AC_UD_TES_NUM_PATCHES); assert(num_patches->sgpr_idx != -1 && num_patches->num_sgprs == 1); base_reg = pipeline->base.user_data_0[MESA_SHADER_TESS_EVAL]; @@ -3902,7 +3902,7 @@ static void radv_emit_vertex_input(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty) { const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; - const struct radv_shader *vs_shader = radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX); + const struct radv_shader *vs_shader = radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX); assert(!cmd_buffer->state.mesh_shading); @@ -3932,7 +3932,7 @@ radv_emit_tess_domain_origin(struct radv_cmd_buffer *cmd_buffer) { const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device; const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; - const struct radv_shader *tes = radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL); + const struct radv_shader *tes = radv_get_shader(pipeline->base.shaders, MESA_SHADER_TESS_EVAL); const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; unsigned type = 0, partitioning = 0, distribution_mode = 0; unsigned topology; @@ -4631,7 +4631,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag } else { radv_foreach_stage(stage, internal_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) { - shader = radv_get_shader(pipeline, stage); + shader = radv_get_shader(pipeline->shaders, stage); if (!shader) continue; @@ -4674,7 +4674,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag prev_shader = NULL; radv_foreach_stage(stage, internal_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) { - shader = radv_get_shader(pipeline, stage); + shader = radv_get_shader(pipeline->shaders, stage); /* Avoid redundantly emitting the address for merged stages. */ if (shader && shader != prev_shader) { @@ -4705,7 +4705,7 @@ radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer, const struct radv_graphics_pipeline *pipeline, bool full_null_descriptors, void *vb_ptr) { - struct radv_shader *vs_shader = radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX); + struct radv_shader *vs_shader = radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX); enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level; enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family; unsigned desc_index = 0; @@ -4894,7 +4894,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer) va += vb_offset; radv_emit_userdata_address(cmd_buffer->device, cmd_buffer->cs, - radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX), + radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX), pipeline->base.user_data_0[MESA_SHADER_VERTEX], AC_UD_VS_VERTEX_BUFFERS, va); @@ -5215,7 +5215,7 @@ gfx10_emit_ge_cntl(struct radv_cmd_buffer *cmd_buffer) primgroup_size = state->tess_num_patches; if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id || - radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.uses_prim_id) { + radv_get_shader(pipeline->base.shaders, MESA_SHADER_TESS_EVAL)->info.uses_prim_id) { break_wave_at_eoi = true; } } else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) { @@ -6222,7 +6222,7 @@ static void radv_bind_vs_input_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_graphics_pipeline *pipeline) { - const struct radv_shader *vs_shader = radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX); + const struct radv_shader *vs_shader = radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX); const struct radv_vs_input_state *src = &pipeline->vs_input_state; /* Bind the vertex input state from the pipeline when the VS has a prolog and the state isn't @@ -7683,7 +7683,7 @@ radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index) struct radeon_cmdbuf *cs = cmd_buffer->cs; radv_foreach_stage(stage, pipeline->active_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) { - radv_emit_view_index_per_stage(cs, radv_get_shader(&pipeline->base, stage), + radv_emit_view_index_per_stage(cs, radv_get_shader(pipeline->base.shaders, stage), pipeline->base.user_data_0[stage], index); } diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c index a3eab7e..0a5fe51 100644 --- a/src/amd/vulkan/radv_debug.c +++ b/src/amd/vulkan/radv_debug.c @@ -455,7 +455,7 @@ radv_dump_vs_prolog(const struct radv_device *device, struct radv_graphics_pipel FILE *f) { struct radv_shader_part *vs_prolog = radv_get_saved_vs_prolog(device); - struct radv_shader *vs_shader = radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX); + struct radv_shader *vs_shader = radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX); if (!vs_prolog || !vs_shader || !vs_shader->info.vs.has_prolog) return; diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index 5a7c66b..7780cb6 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -1153,7 +1153,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, vtx_base_sgpr |= DGC_USES_BASEINSTANCE; const struct radv_shader *vertex_shader = - radv_get_shader(&graphics_pipeline->base, MESA_SHADER_VERTEX); + radv_get_shader(graphics_pipeline->base.shaders, MESA_SHADER_VERTEX); uint16_t vbo_sgpr = ((radv_get_user_sgpr(vertex_shader, AC_UD_VS_VERTEX_BUFFERS)->sgpr_idx * 4 + graphics_pipeline->base.user_data_0[MESA_SHADER_VERTEX]) - SI_SH_REG_OFFSET) >> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 4334590..d5544f8 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -779,7 +779,7 @@ radv_compute_ia_multi_vgt_param_helpers(const struct radv_device *device, if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) { /* SWITCH_ON_EOI must be set if PrimID is used. */ if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id || - radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.uses_prim_id) + radv_get_shader(pipeline->base.shaders, MESA_SHADER_TESS_EVAL)->info.uses_prim_id) ia_multi_vgt_param.ia_switch_on_eoi = true; } @@ -1412,24 +1412,24 @@ gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, } struct radv_shader * -radv_get_shader(const struct radv_pipeline *pipeline, gl_shader_stage stage) +radv_get_shader(struct radv_shader *const *shaders, gl_shader_stage stage) { if (stage == MESA_SHADER_VERTEX) { - if (pipeline->shaders[MESA_SHADER_VERTEX]) - return pipeline->shaders[MESA_SHADER_VERTEX]; - if (pipeline->shaders[MESA_SHADER_TESS_CTRL]) - return pipeline->shaders[MESA_SHADER_TESS_CTRL]; - if (pipeline->shaders[MESA_SHADER_GEOMETRY]) - return pipeline->shaders[MESA_SHADER_GEOMETRY]; + if (shaders[MESA_SHADER_VERTEX]) + return shaders[MESA_SHADER_VERTEX]; + if (shaders[MESA_SHADER_TESS_CTRL]) + return shaders[MESA_SHADER_TESS_CTRL]; + if (shaders[MESA_SHADER_GEOMETRY]) + return shaders[MESA_SHADER_GEOMETRY]; } else if (stage == MESA_SHADER_TESS_EVAL) { - if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) + if (!shaders[MESA_SHADER_TESS_CTRL]) return NULL; - if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) - return pipeline->shaders[MESA_SHADER_TESS_EVAL]; - if (pipeline->shaders[MESA_SHADER_GEOMETRY]) - return pipeline->shaders[MESA_SHADER_GEOMETRY]; + if (shaders[MESA_SHADER_TESS_EVAL]) + return shaders[MESA_SHADER_TESS_EVAL]; + if (shaders[MESA_SHADER_GEOMETRY]) + return shaders[MESA_SHADER_GEOMETRY]; } - return pipeline->shaders[stage]; + return shaders[stage]; } static const struct radv_shader * @@ -4268,7 +4268,7 @@ radv_pipeline_emit_vgt_vertex_reuse(const struct radv_device *device, struct rad unsigned vtx_reuse_depth = 30; if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL) && - radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.tes.spacing == + radv_get_shader(pipeline->base.shaders, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) { vtx_reuse_depth = 14; } @@ -4557,7 +4557,8 @@ radv_pipeline_init_vertex_input_state(const struct radv_device *device, const struct vk_graphics_pipeline_state *state) { const struct radv_physical_device *pdevice = device->physical_device; - const struct radv_shader_info *vs_info = &radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX)->info; + const struct radv_shader_info *vs_info = + &radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX)->info; if (state->vi) { u_foreach_bit(i, state->vi->attributes_valid) { @@ -4654,7 +4655,7 @@ radv_pipeline_get_streamout_shader(struct radv_graphics_pipeline *pipeline) int i; for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) { - struct radv_shader *shader = radv_get_shader(&pipeline->base, i); + struct radv_shader *shader = radv_get_shader(pipeline->base.shaders, i); if (shader && shader->info.so.num_outputs > 0) return shader; @@ -4691,16 +4692,16 @@ radv_pipeline_init_shader_stages_state(const struct radv_device *device, radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH) ? MESA_SHADER_MESH : MESA_SHADER_VERTEX; const struct radv_userdata_info *loc = - radv_get_user_sgpr(radv_get_shader(&pipeline->base, first_stage), + radv_get_user_sgpr(radv_get_shader(pipeline->base.shaders, first_stage), AC_UD_VS_BASE_VERTEX_START_INSTANCE); if (loc->sgpr_idx != -1) { pipeline->vtx_base_sgpr = pipeline->base.user_data_0[first_stage]; pipeline->vtx_base_sgpr += loc->sgpr_idx * 4; pipeline->vtx_emit_num = loc->num_sgprs; pipeline->uses_drawid = - radv_get_shader(&pipeline->base, first_stage)->info.vs.needs_draw_id; + radv_get_shader(pipeline->base.shaders, first_stage)->info.vs.needs_draw_id; pipeline->uses_baseinstance = - radv_get_shader(&pipeline->base, first_stage)->info.vs.needs_base_instance; + radv_get_shader(pipeline->base.shaders, first_stage)->info.vs.needs_base_instance; assert(first_stage != MESA_SHADER_MESH || !pipeline->uses_baseinstance); } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 2998ed3..547c6cb 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2360,7 +2360,7 @@ bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline); const struct radv_userdata_info *radv_get_user_sgpr(const struct radv_shader *shader, int idx); -struct radv_shader *radv_get_shader(const struct radv_pipeline *pipeline, gl_shader_stage stage); +struct radv_shader *radv_get_shader(struct radv_shader *const *shaders, gl_shader_stage stage); void radv_pipeline_emit_hw_cs(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs, const struct radv_shader *shader); -- 2.7.4