From 5966f2f9ca2c4fdf629443a0d1f2f90ba142bbf6 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sat, 28 Jan 2023 15:04:18 -0800 Subject: [PATCH] [Target] Use llvm::Log2_{32,64} (NFC) --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 +-- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index fd5962c0951a..ab2b53f9d060 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -15040,8 +15040,7 @@ bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, if (BitSize == 32) Val &= (1LL << 32) - 1; - unsigned LZ = llvm::countl_zero((uint64_t)Val); - unsigned Shift = (63 - LZ) / 16; + unsigned Shift = llvm::Log2_64((uint64_t)Val) / 16; // MOVZ is free so return true for one or fewer MOVK. return Shift < 3; } diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index a271dedb0162..b09d0f0689d3 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -3435,7 +3435,7 @@ bool ARMDAGToDAGISel::tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned) { // Shift must be the same as the ands lsb if (isInt32Immediate(N->getOperand(1), Srl_imm) && Srl_imm == LSB) { assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); - unsigned MSB = 31 - llvm::countl_zero(And_imm); + unsigned MSB = llvm::Log2_32(And_imm); // Note: The width operand is encoded as width-1. unsigned Width = MSB - LSB; SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); -- 2.34.1