From 594a35657ae16ce4390cbcd478e367a306762797 Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Thu, 2 Sep 2004 01:54:27 +0000 Subject: [PATCH] power4.md: Increase store latency to 12. * config/rs6000/power4.md: Increase store latency to 12. * config/rs6000/power5.md: Same. From-SVN: r86953 --- gcc/ChangeLog | 5 +++++ gcc/config/rs6000/power4.md | 12 ++++++------ gcc/config/rs6000/power5.md | 10 +++++----- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5d1334a..cfa6e35 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2004-09-01 David Edelsohn + + * config/rs6000/power4.md: Increase store latency to 12. + * config/rs6000/power5.md: Same. + 2004-09-01 James E Wilson PR target/14064 diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md index fabc1de..7c5676e 100644 --- a/gcc/config/rs6000/power4.md +++ b/gcc/config/rs6000/power4.md @@ -130,7 +130,7 @@ (eq_attr "cpu" "power4")) "lsq_power4") -(define_insn_reservation "power4-store" 1 +(define_insn_reservation "power4-store" 12 (and (eq_attr "type" "store") (eq_attr "cpu" "power4")) "(du1_power4,lsu1_power4,iu1_power4)\ @@ -138,7 +138,7 @@ |(du3_power4,lsu2_power4,nothing,iu2_power4)\ |(du4_power4,lsu1_power4,nothing,iu1_power4)") -(define_insn_reservation "power4-store-update" 1 +(define_insn_reservation "power4-store-update" 12 (and (eq_attr "type" "store_u") (eq_attr "cpu" "power4")) "(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\ @@ -146,13 +146,13 @@ |(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\ |(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)") -(define_insn_reservation "power4-store-update-indexed" 1 +(define_insn_reservation "power4-store-update-indexed" 12 (and (eq_attr "type" "store_ux") (eq_attr "cpu" "power4")) "du1_power4+du2_power4+du3_power4+du4_power4,\ iu1_power4,lsu2_power4+iu2_power4,iu2_power4") -(define_insn_reservation "power4-fpstore" 1 +(define_insn_reservation "power4-fpstore" 12 (and (eq_attr "type" "fpstore") (eq_attr "cpu" "power4")) "(du1_power4,lsu1_power4,fpu1_power4)\ @@ -160,7 +160,7 @@ |(du3_power4,lsu2_power4,nothing,fpu2_power4)\ |(du4_power4,lsu1_power4,nothing,fpu1_power4)") -(define_insn_reservation "power4-fpstore-update" 1 +(define_insn_reservation "power4-fpstore-update" 12 (and (eq_attr "type" "fpstore_u,fpstore_ux") (eq_attr "cpu" "power4")) "(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\ @@ -168,7 +168,7 @@ |(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)") ; |(du3_power4+du4_power4,nothing,lsu2_power4+iu1_power4,fpu2_power4)") -(define_insn_reservation "power4-vecstore" 1 +(define_insn_reservation "power4-vecstore" 12 (and (eq_attr "type" "vecstore") (eq_attr "cpu" "power4")) "(du1_power4,lsu1_power4,vec_power4)\ diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md index 59baa79..932c4bf 100644 --- a/gcc/config/rs6000/power5.md +++ b/gcc/config/rs6000/power5.md @@ -103,7 +103,7 @@ (eq_attr "cpu" "power5")) "du1_power5+du2_power5,lsu1_power5+iu2_power5") -(define_insn_reservation "power5-store" 1 +(define_insn_reservation "power5-store" 12 (and (eq_attr "type" "store") (eq_attr "cpu" "power5")) "(du1_power5,lsu1_power5,iu1_power5)\ @@ -111,18 +111,18 @@ |(du3_power5,lsu2_power5,nothing,iu2_power5)\ |(du4_power5,lsu1_power5,nothing,iu1_power5)") -(define_insn_reservation "power5-store-update" 1 +(define_insn_reservation "power5-store-update" 12 (and (eq_attr "type" "store_u") (eq_attr "cpu" "power5")) "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5") -(define_insn_reservation "power5-store-update-indexed" 1 +(define_insn_reservation "power5-store-update-indexed" 12 (and (eq_attr "type" "store_ux") (eq_attr "cpu" "power5")) "du1_power5+du2_power5+du3_power5+du4_power5,\ iu1_power5,lsu2_power5+iu2_power5,iu2_power5") -(define_insn_reservation "power5-fpstore" 1 +(define_insn_reservation "power5-fpstore" 12 (and (eq_attr "type" "fpstore") (eq_attr "cpu" "power5")) "(du1_power5,lsu1_power5,fpu1_power5)\ @@ -130,7 +130,7 @@ |(du3_power5,lsu2_power5,nothing,fpu2_power5)\ |(du4_power5,lsu1_power5,nothing,fpu1_power5)") -(define_insn_reservation "power5-fpstore-update" 1 +(define_insn_reservation "power5-fpstore-update" 12 (and (eq_attr "type" "fpstore_u,fpstore_ux") (eq_attr "cpu" "power5")) "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5") -- 2.7.4