From 59479e7208c4be3ea9317763dad05b208f0ea135 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 22 Apr 2016 03:22:38 +0000 Subject: [PATCH] [AVX512] Teach lowering to use vplzcntd/q to implement 128/256-bit CTTZ_ZERO_UNDEF even without VLX support. We can just extend to 512-bits and extract like we do for CTLZ. llvm-svn: 267100 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 15 ++- llvm/test/CodeGen/X86/vector-tzcnt-128.ll | 145 ++++++++++++++++++++++++- llvm/test/CodeGen/X86/vector-tzcnt-256.ll | 173 +++++++++++++++++++++++++++++- llvm/test/CodeGen/X86/vector-tzcnt-512.ll | 1 + 4 files changed, 323 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index c551cef..e2cb59a 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1341,17 +1341,17 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::CTLZ, MVT::v8i32, Legal); setOperationAction(ISD::CTLZ, MVT::v2i64, Legal); setOperationAction(ISD::CTLZ, MVT::v4i32, Legal); - - setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom); - setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom); - setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom); - setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom); } else { setOperationAction(ISD::CTLZ, MVT::v4i64, Custom); setOperationAction(ISD::CTLZ, MVT::v8i32, Custom); setOperationAction(ISD::CTLZ, MVT::v2i64, Custom); setOperationAction(ISD::CTLZ, MVT::v4i32, Custom); } + + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom); } // Subtarget.hasCDI() if (Subtarget.hasDQI()) { @@ -18783,8 +18783,6 @@ static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) { SDLoc dl(Op); if (VT.isVector()) { - const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - SDValue N0 = Op.getOperand(0); SDValue Zero = DAG.getConstant(0, dl, VT); @@ -18793,8 +18791,7 @@ static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) { DAG.getNode(ISD::SUB, dl, VT, Zero, N0)); // cttz_undef(x) = (width - 1) - ctlz(lsb) - if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF && - TLI.isOperationLegal(ISD::CTLZ, VT)) { + if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF) { SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT); return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne, DAG.getNode(ISD::CTLZ, dl, VT, LSB)); diff --git a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll index 0c8f37b..ab75d00 100644 --- a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll +++ b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; NOTE: Assertions have been autogenerated by update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3 @@ -6,6 +6,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512CDVL +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,-avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512CD ; ; Just one 32-bit run to make sure we do reasonable things for i64 tzcnt. ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=X32-SSE --check-prefix=X32-SSE41 @@ -199,6 +200,16 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind { ; AVX512CDVL-NEXT: vpsubq %xmm0, %xmm1, %xmm0 ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: testv2i64u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512CD-NEXT: vpsubq %xmm0, %xmm1, %xmm1 +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vplzcntq %zmm0, %zmm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm1 = [63,63] +; AVX512CD-NEXT: vpsubq %xmm0, %xmm1, %xmm0 +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: testv2i64u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pextrd $2, %xmm0, %eax @@ -396,6 +407,28 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind { ; AVX512CDVL-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: testv4i32: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512CD-NEXT: vpsubd %xmm0, %xmm1, %xmm2 +; AVX512CD-NEXT: vpand %xmm2, %xmm0, %xmm0 +; AVX512CD-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2 +; AVX512CD-NEXT: vpsubd %xmm2, %xmm0, %xmm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %xmm2, %xmm0, %xmm3 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %xmm3, %xmm4, %xmm3 +; AVX512CD-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX512CD-NEXT: vpand %xmm2, %xmm0, %xmm0 +; AVX512CD-NEXT: vpshufb %xmm0, %xmm4, %xmm0 +; AVX512CD-NEXT: vpaddb %xmm3, %xmm0, %xmm0 +; AVX512CD-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] +; AVX512CD-NEXT: vpsadbw %xmm1, %xmm2, %xmm2 +; AVX512CD-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; AVX512CD-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: testv4i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -586,6 +619,16 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind { ; AVX512CDVL-NEXT: vpsubd %xmm0, %xmm1, %xmm0 ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: testv4i32u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512CD-NEXT: vpsubd %xmm0, %xmm1, %xmm1 +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vplzcntd %zmm0, %zmm0 +; AVX512CD-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1 +; AVX512CD-NEXT: vpsubd %xmm0, %xmm1, %xmm0 +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: testv4i32u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -768,6 +811,25 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind { ; AVX512CDVL-NEXT: vpsrlw $8, %xmm0, %xmm0 ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: testv8i16: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512CD-NEXT: vpsubw %xmm0, %xmm1, %xmm1 +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX512CD-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX512CD-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX512CD-NEXT: vpsllw $8, %xmm0, %xmm1 +; AVX512CD-NEXT: vpaddb %xmm0, %xmm1, %xmm0 +; AVX512CD-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: testv8i16: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -947,6 +1009,25 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind { ; AVX512CDVL-NEXT: vpsrlw $8, %xmm0, %xmm0 ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: testv8i16u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512CD-NEXT: vpsubw %xmm0, %xmm1, %xmm1 +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX512CD-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX512CD-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX512CD-NEXT: vpsllw $8, %xmm0, %xmm1 +; AVX512CD-NEXT: vpaddb %xmm0, %xmm1, %xmm0 +; AVX512CD-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: testv8i16u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -1101,6 +1182,22 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind { ; AVX512CDVL-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: testv16i8: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512CD-NEXT: vpsubb %xmm0, %xmm1, %xmm1 +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vpsubb {{.*}}(%rip), %xmm0, %xmm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX512CD-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX512CD-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: testv16i8: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -1251,6 +1348,22 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind { ; AVX512CDVL-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: testv16i8u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512CD-NEXT: vpsubb %xmm0, %xmm1, %xmm1 +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vpsubb {{.*}}(%rip), %xmm0, %xmm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX512CD-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX512CD-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX512CD-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512CD-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX512CD-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: testv16i8u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -1337,6 +1450,11 @@ define <4 x i32> @foldv4i32() nounwind { ; AVX512CDVL-NEXT: vmovdqa32 {{.*#+}} xmm0 = [8,0,32,0] ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: foldv4i32: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0] +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: foldv4i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,32,0] @@ -1366,6 +1484,11 @@ define <4 x i32> @foldv4i32u() nounwind { ; AVX512CDVL-NEXT: vmovdqa32 {{.*#+}} xmm0 = [8,0,32,0] ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: foldv4i32u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0] +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: foldv4i32u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,32,0] @@ -1395,6 +1518,11 @@ define <8 x i16> @foldv8i16() nounwind { ; AVX512CDVL-NEXT: vmovdqa64 {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: foldv8i16: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: foldv8i16: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] @@ -1424,6 +1552,11 @@ define <8 x i16> @foldv8i16u() nounwind { ; AVX512CDVL-NEXT: vmovdqa64 {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: foldv8i16u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: foldv8i16u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] @@ -1453,6 +1586,11 @@ define <16 x i8> @foldv16i8() nounwind { ; AVX512CDVL-NEXT: vmovdqa64 {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: foldv16i8: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: foldv16i8: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] @@ -1482,6 +1620,11 @@ define <16 x i8> @foldv16i8u() nounwind { ; AVX512CDVL-NEXT: vmovdqa64 {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] ; AVX512CDVL-NEXT: retq ; +; AVX512CD-LABEL: foldv16i8u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] +; AVX512CD-NEXT: retq +; ; X32-SSE-LABEL: foldv16i8u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] diff --git a/llvm/test/CodeGen/X86/vector-tzcnt-256.ll b/llvm/test/CodeGen/X86/vector-tzcnt-256.ll index 5c8eff0..b7d9644 100644 --- a/llvm/test/CodeGen/X86/vector-tzcnt-256.ll +++ b/llvm/test/CodeGen/X86/vector-tzcnt-256.ll @@ -1,7 +1,8 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; NOTE: Assertions have been autogenerated by update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512CDVL +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,-avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512CD define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX1-LABEL: testv4i64: @@ -69,6 +70,24 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX512CDVL-NEXT: vpaddb %ymm3, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: testv4i64: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512CD-NEXT: vpsubq %ymm0, %ymm1, %ymm2 +; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: vpbroadcastq {{.*}}(%rip), %ymm2 +; AVX512CD-NEXT: vpsubq %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm3 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %ymm3, %ymm4, %ymm3 +; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: vpshufb %ymm0, %ymm4, %ymm0 +; AVX512CD-NEXT: vpaddb %ymm3, %ymm0, %ymm0 +; AVX512CD-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: retq %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %in, i1 0) ret <4 x i64> %out } @@ -132,6 +151,16 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind { ; AVX512CDVL-NEXT: vpbroadcastq {{.*}}(%rip), %ymm1 ; AVX512CDVL-NEXT: vpsubq %ymm0, %ymm1, %ymm0 ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: testv4i64u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512CD-NEXT: vpsubq %ymm0, %ymm1, %ymm1 +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vplzcntq %zmm0, %zmm0 +; AVX512CD-NEXT: vpbroadcastq {{.*}}(%rip), %ymm1 +; AVX512CD-NEXT: vpsubq %ymm0, %ymm1, %ymm0 +; AVX512CD-NEXT: retq %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %in, i1 -1) ret <4 x i64> %out } @@ -218,6 +247,28 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { ; AVX512CDVL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: testv8i32: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512CD-NEXT: vpsubd %ymm0, %ymm1, %ymm2 +; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: vpbroadcastd {{.*}}(%rip), %ymm2 +; AVX512CD-NEXT: vpsubd %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm3 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %ymm3, %ymm4, %ymm3 +; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: vpshufb %ymm0, %ymm4, %ymm0 +; AVX512CD-NEXT: vpaddb %ymm3, %ymm0, %ymm0 +; AVX512CD-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] +; AVX512CD-NEXT: vpsadbw %ymm1, %ymm2, %ymm2 +; AVX512CD-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] +; AVX512CD-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: retq %out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %in, i1 0) ret <8 x i32> %out } @@ -293,6 +344,16 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind { ; AVX512CDVL-NEXT: vpbroadcastd {{.*}}(%rip), %ymm1 ; AVX512CDVL-NEXT: vpsubd %ymm0, %ymm1, %ymm0 ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: testv8i32u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512CD-NEXT: vpsubd %ymm0, %ymm1, %ymm1 +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vplzcntd %zmm0, %zmm0 +; AVX512CD-NEXT: vpbroadcastd {{.*}}(%rip), %ymm1 +; AVX512CD-NEXT: vpsubd %ymm0, %ymm1, %ymm0 +; AVX512CD-NEXT: retq %out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %in, i1 -1) ret <8 x i32> %out } @@ -370,6 +431,25 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind { ; AVX512CDVL-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX512CDVL-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: testv16i16: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512CD-NEXT: vpsubw %ymm0, %ymm1, %ymm1 +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: vpsllw $8, %ymm0, %ymm1 +; AVX512CD-NEXT: vpaddb %ymm0, %ymm1, %ymm0 +; AVX512CD-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX512CD-NEXT: retq %out = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %in, i1 0) ret <16 x i16> %out } @@ -447,6 +527,25 @@ define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind { ; AVX512CDVL-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX512CDVL-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: testv16i16u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512CD-NEXT: vpsubw %ymm0, %ymm1, %ymm1 +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: vpsllw $8, %ymm0, %ymm1 +; AVX512CD-NEXT: vpaddb %ymm0, %ymm1, %ymm0 +; AVX512CD-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX512CD-NEXT: retq %out = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %in, i1 -1) ret <16 x i16> %out } @@ -512,6 +611,22 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; AVX512CDVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX512CDVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: testv32i8: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512CD-NEXT: vpsubb %ymm0, %ymm1, %ymm1 +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vpsubb {{.*}}(%rip), %ymm0, %ymm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: retq %out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %in, i1 0) ret <32 x i8> %out } @@ -577,6 +692,22 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind { ; AVX512CDVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX512CDVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: testv32i8u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512CD-NEXT: vpsubb %ymm0, %ymm1, %ymm1 +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vpsubb {{.*}}(%rip), %ymm0, %ymm0 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2 +; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX512CD-NEXT: retq %out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %in, i1 -1) ret <32 x i8> %out } @@ -596,6 +727,11 @@ define <4 x i64> @foldv4i64() nounwind { ; AVX512CDVL: # BB#0: ; AVX512CDVL-NEXT: vmovdqa64 {{.*#+}} ymm0 = [8,0,64,0] ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: foldv4i64: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0] +; AVX512CD-NEXT: retq %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> , i1 0) ret <4 x i64> %out } @@ -615,6 +751,11 @@ define <4 x i64> @foldv4i64u() nounwind { ; AVX512CDVL: # BB#0: ; AVX512CDVL-NEXT: vmovdqa64 {{.*#+}} ymm0 = [8,0,64,0] ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: foldv4i64u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0] +; AVX512CD-NEXT: retq %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> , i1 -1) ret <4 x i64> %out } @@ -634,6 +775,11 @@ define <8 x i32> @foldv8i32() nounwind { ; AVX512CDVL: # BB#0: ; AVX512CDVL-NEXT: vmovdqa32 {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3] ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: foldv8i32: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3] +; AVX512CD-NEXT: retq %out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> , i1 0) ret <8 x i32> %out } @@ -653,6 +799,11 @@ define <8 x i32> @foldv8i32u() nounwind { ; AVX512CDVL: # BB#0: ; AVX512CDVL-NEXT: vmovdqa32 {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3] ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: foldv8i32u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3] +; AVX512CD-NEXT: retq %out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> , i1 -1) ret <8 x i32> %out } @@ -672,6 +823,11 @@ define <16 x i16> @foldv16i16() nounwind { ; AVX512CDVL: # BB#0: ; AVX512CDVL-NEXT: vmovdqa64 {{.*#+}} ymm0 = [8,0,16,0,16,0,3,3,1,1,0,1,2,3,4,5] ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: foldv16i16: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,16,0,16,0,3,3,1,1,0,1,2,3,4,5] +; AVX512CD-NEXT: retq %out = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> , i1 0) ret <16 x i16> %out } @@ -691,6 +847,11 @@ define <16 x i16> @foldv16i16u() nounwind { ; AVX512CDVL: # BB#0: ; AVX512CDVL-NEXT: vmovdqa64 {{.*#+}} ymm0 = [8,0,16,0,16,0,3,3,1,1,0,1,2,3,4,5] ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: foldv16i16u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,16,0,16,0,3,3,1,1,0,1,2,3,4,5] +; AVX512CD-NEXT: retq %out = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> , i1 -1) ret <16 x i16> %out } @@ -710,6 +871,11 @@ define <32 x i8> @foldv32i8() nounwind { ; AVX512CDVL: # BB#0: ; AVX512CDVL-NEXT: vmovdqa64 {{.*#+}} ymm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5,6,7,8,8,7,6,5,4,3,2,1,0,0,0,0,0] ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: foldv32i8: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5,6,7,8,8,7,6,5,4,3,2,1,0,0,0,0,0] +; AVX512CD-NEXT: retq %out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> , i1 0) ret <32 x i8> %out } @@ -729,6 +895,11 @@ define <32 x i8> @foldv32i8u() nounwind { ; AVX512CDVL: # BB#0: ; AVX512CDVL-NEXT: vmovdqa64 {{.*#+}} ymm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5,6,7,8,8,7,6,5,4,3,2,1,0,0,0,0,0] ; AVX512CDVL-NEXT: retq +; +; AVX512CD-LABEL: foldv32i8u: +; AVX512CD: # BB#0: +; AVX512CD-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5,6,7,8,8,7,6,5,4,3,2,1,0,0,0,0,0] +; AVX512CD-NEXT: retq %out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> , i1 -1) ret <32 x i8> %out } diff --git a/llvm/test/CodeGen/X86/vector-tzcnt-512.ll b/llvm/test/CodeGen/X86/vector-tzcnt-512.ll index 2d17159..81bfd81 100644 --- a/llvm/test/CodeGen/X86/vector-tzcnt-512.ll +++ b/llvm/test/CodeGen/X86/vector-tzcnt-512.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd,-avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512CD ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd,+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512CDBW -- 2.7.4