From 593a00aecc53acae08fefa4da910f0908c46c357 Mon Sep 17 00:00:00 2001 From: Kaifu Hu Date: Wed, 30 Aug 2017 17:19:54 +0800 Subject: [PATCH] hdmitx: fix 4k smpte no signal PD#149239: hdmitx: fix 4k smpte no signal when 4k smpte 444,10bit, div40 and scramble need be setted Change-Id: Iadfc337519e1444c244b36086c3929d231bd80c4 Signed-off-by: Kaifu Hu --- .../media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c | 37 +++++++++++++--------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index a557df0..0813e75 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -522,10 +522,10 @@ static void hdmi_hwp_init(struct hdmitx_dev *hdev) } } return; - } else { - hdev->para->cd = COLORDEPTH_RESERVED; - hdev->para->cs = COLORSPACE_RESERVED; } + + hdev->para->cd = COLORDEPTH_RESERVED; + hdev->para->cs = COLORSPACE_RESERVED; /* reset HDMITX APB & TX & PHY */ hd_set_reg_bits(P_RESET0_REGISTER, 1, 19, 1); hd_set_reg_bits(P_RESET2_REGISTER, 1, 15, 1); @@ -1866,25 +1866,17 @@ static void set_tmds_clk_div40(unsigned int div40) hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); } -static int hdmitx_set_dispmode(struct hdmitx_dev *hdev) +static void hdmitx_set_scdc(struct hdmitx_dev *hdev) { unsigned char rx_ver = 0; - struct hdmi_format_para *para = NULL; - - if (hdev->cur_video_param == NULL) /* disable HDMI */ - return 0; - else - if (!hdmitx_edid_VIC_support(hdev->cur_video_param->VIC)) - return -1; - hdev->cur_VIC = hdev->cur_video_param->VIC; scdc_rd_sink(SINK_VER, &rx_ver); if (rx_ver != 1) scdc_rd_sink(SINK_VER, &rx_ver); /* Recheck */ - pr_info("hdmirx version is %s\n", + hdmi_print(IMP, SYS "hdmirx version is %s\n", (rx_ver == 1) ? "2.0" : "1.4 or below"); - switch (hdev->cur_VIC) { + switch (hdev->cur_video_param->VIC) { case HDMI_3840x2160p50_16x9: case HDMI_3840x2160p60_16x9: case HDMI_4096x2160p50_256x135: @@ -1908,10 +1900,13 @@ static int hdmitx_set_dispmode(struct hdmitx_dev *hdev) break; case HDMI_3840x2160p24_16x9: case HDMI_3840x2160p24_64x27: + case HDMI_4096x2160p24_256x135: case HDMI_3840x2160p25_16x9: case HDMI_3840x2160p25_64x27: + case HDMI_4096x2160p25_256x135: case HDMI_3840x2160p30_16x9: case HDMI_3840x2160p30_64x27: + case HDMI_4096x2160p30_256x135: if ((hdev->para->cs == COLORSPACE_YUV422) || (hdev->para->cd == COLORDEPTH_24B)) hdev->para->tmds_clk_div40 = 0; @@ -1924,6 +1919,19 @@ static int hdmitx_set_dispmode(struct hdmitx_dev *hdev) } set_tmds_clk_div40(hdev->para->tmds_clk_div40); scdc_config(hdev); +} + +static int hdmitx_set_dispmode(struct hdmitx_dev *hdev) +{ + struct hdmi_format_para *para = NULL; + + if (hdev->cur_video_param == NULL) /* disable HDMI */ + return 0; + if (!hdmitx_edid_VIC_support(hdev->cur_video_param->VIC)) + return -1; + hdev->cur_VIC = hdev->cur_video_param->VIC; + + hdmitx_set_scdc(hdev); if (color_depth_f == 24) hdev->cur_video_param->color_depth = COLORDEPTH_24B; @@ -3564,7 +3572,6 @@ static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd, return hdmitx_hdcp_opr(0xa); case DDC_HDCP_22_LSTORE: return hdmitx_hdcp_opr(0xb); - break; case DDC_SCDC_DIV40_SCRAMB: if (argv == 1) { scdc_wr_sink(TMDS_CFG, 0x3); /* TMDS 1/40 & Scramble */ -- 2.7.4