From 58f505ba24761c22314a85874580679c209388b5 Mon Sep 17 00:00:00 2001
From: Chad Rosier <mcrosier@codeaurora.org>
Date: Fri, 26 Aug 2016 18:05:50 +0000
Subject: [PATCH] [AArch64] Avoid materializing constant values when generating
 csel instructions.

Differential Revision: https://reviews.llvm.org/D23677

llvm-svn: 279849
---
 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp  | 16 ++++
 llvm/test/CodeGen/AArch64/cond-sel-value-prop.ll | 99 ++++++++++++++++++++++++
 2 files changed, 115 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/cond-sel-value-prop.ll

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 2236071..fcbc1a7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4036,6 +4036,22 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
       }
     }
 
+    // Avoid materializing a constant when possible by reusing a known value in
+    // a register.  However, don't perform this optimization if the known value
+    // is one, zero or negative one.  We can always materialize these values
+    // using CSINC, CSEL and CSINV with wzr/xzr as the FVal, respectively.
+    ConstantSDNode *RHSVal = dyn_cast<ConstantSDNode>(RHS);
+    if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&
+        !RHSVal->isNullValue() && !RHSVal->isAllOnesValue()) {
+      AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
+      // Transform "a == C ? C : x" to "a == C ? a : x" and "a != C ? x : C" to
+      // "a != C ? x : a" to avoid materializing C.
+      if (CTVal && CTVal == RHSVal && AArch64CC == AArch64CC::EQ)
+        TVal = LHS;
+      else if (CFVal && CFVal == RHSVal && AArch64CC == AArch64CC::NE)
+        FVal = LHS;
+    }
+
     SDValue CCVal;
     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
 
diff --git a/llvm/test/CodeGen/AArch64/cond-sel-value-prop.ll b/llvm/test/CodeGen/AArch64/cond-sel-value-prop.ll
new file mode 100644
index 0000000..cc0aad1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cond-sel-value-prop.ll
@@ -0,0 +1,99 @@
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+
+; Transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C.
+; CHECK-LABEL: test1:
+; CHECK: cmp w[[REG1:[0-9]+]], #2
+; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x7
+; CHECK: csel w0, w[[REG1]], w[[REG2]], eq
+define i32 @test1(i32 %x) {
+  %cmp = icmp eq i32 %x, 2
+  %res = select i1 %cmp, i32 2, i32 7
+  ret i32 %res
+}
+
+; Transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C.
+; CHECK-LABEL: test2:
+; CHECK: cmp x[[REG1:[0-9]+]], #2
+; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x7
+; CHECK: csel x0, x[[REG1]], x[[REG2]], eq
+define i64 @test2(i64 %x) {
+  %cmp = icmp eq i64 %x, 2
+  %res = select i1 %cmp, i64 2, i64 7
+  ret i64 %res
+}
+
+; Transform "a != C ? x : C" to "a != C ? x : a" to avoid materializing C.
+; CHECK-LABEL: test3:
+; CHECK: cmp x[[REG1:[0-9]+]], #7
+; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x2
+; CHECK: csel x0, x[[REG2]], x[[REG1]], ne
+define i64 @test3(i64 %x) {
+  %cmp = icmp ne i64 %x, 7
+  %res = select i1 %cmp, i64 2, i64 7
+  ret i64 %res
+}
+
+; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == 0.  If we did we
+; would needlessly extend the live range of x0 when we can just use xzr.
+; CHECK-LABEL: test4:
+; CHECK: cmp x0, #0
+; CHECK: orr w8, wzr, #0x7
+; CHECK: csel x0, xzr, x8, eq
+define i64 @test4(i64 %x) {
+  %cmp = icmp eq i64 %x, 0
+  %res = select i1 %cmp, i64 0, i64 7
+  ret i64 %res
+}
+
+; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == 1.  If we did we
+; would needlessly extend the live range of x0 when we can just use xzr with
+; CSINC to materialize the 1.
+; CHECK-LABEL: test5:
+; CHECK: cmp x0, #1
+; CHECK: orr w[[REG:[0-9]+]], wzr, #0x7
+; CHECK: csinc x0, x[[REG]], xzr, ne
+define i64 @test5(i64 %x) {
+  %cmp = icmp eq i64 %x, 1
+  %res = select i1 %cmp, i64 1, i64 7
+  ret i64 %res
+}
+
+; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == -1.  If we did we
+; would needlessly extend the live range of x0 when we can just use xzr with
+; CSINV to materialize the -1.
+; CHECK-LABEL: test6:
+; CHECK: cmn x0, #1
+; CHECK: orr w[[REG:[0-9]+]], wzr, #0x7
+; CHECK: csinv x0, x[[REG]], xzr, ne
+define i64 @test6(i64 %x) {
+  %cmp = icmp eq i64 %x, -1
+  %res = select i1 %cmp, i64 -1, i64 7
+  ret i64 %res
+}
+
+; CHECK-LABEL: test7:
+; CHECK: cmp x[[REG:[0-9]]], #7
+; CHECK: csinc x0, x[[REG]], xzr, eq
+define i64 @test7(i64 %x) {
+  %cmp = icmp eq i64 %x, 7
+  %res = select i1 %cmp, i64 7, i64 1
+  ret i64 %res
+}
+
+; CHECK-LABEL: test8:
+; CHECK: cmp x[[REG:[0-9]]], #7
+; CHECK: csinc x0, x[[REG]], xzr, eq
+define i64 @test8(i64 %x) {
+  %cmp = icmp ne i64 %x, 7
+  %res = select i1 %cmp, i64 1, i64 7
+  ret i64 %res
+}
+
+; CHECK-LABEL: test9:
+; CHECK: cmp x[[REG:[0-9]]], #7
+; CHECK: csinv x0, x[[REG]], xzr, eq
+define i64 @test9(i64 %x) {
+  %cmp = icmp eq i64 %x, 7
+  %res = select i1 %cmp, i64 7, i64 -1
+  ret i64 %res
+}
-- 
2.7.4