From 58e933e3f012d47d88ca35cd8688d4a31a0def4d Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 8 Jun 2021 13:27:46 -0400 Subject: [PATCH] drm/msm/a6xx: add GMU_CX_GMU_CX_FALNEXT_INTF write for a650 downstream msm-5.14 kernel added a write to this register, so match that. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20210608172808.11803-4-jonathan@marek.ca Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index e58e455..b64e623 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -751,8 +751,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) int ret; u32 chipid; - if (adreno_is_a650(adreno_gpu)) + if (adreno_is_a650(adreno_gpu)) { + gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); + } if (state == GMU_WARM_BOOT) { ret = a6xx_rpmh_start(gmu); -- 2.7.4