From 5893cfb26a15e20e0049aeb07440547a4055029b Mon Sep 17 00:00:00 2001 From: Ju-Zhe Zhong Date: Mon, 13 Feb 2023 16:03:03 +0800 Subject: [PATCH] RISC-V: Add vmsge vx C api tests gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmsge_vx_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-3.c: New test. --- .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-1.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-2.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-3.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-3.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-1.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-2.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-3.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-3.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.c | 160 +++++++++++++++++++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-1.c | 157 ++++++++++++++++++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-2.c | 157 ++++++++++++++++++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-3.c | 157 ++++++++++++++++++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-1.c | 160 +++++++++++++++++++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-2.c | 160 +++++++++++++++++++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-3.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-1.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-2.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-3.c | 157 ++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-3.c | 160 +++++++++++++++++++++ 36 files changed, 5706 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-1.c new file mode 100644 index 0000000..f453f6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_m(mask,op1,op2,vl); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-2.c new file mode 100644 index 0000000..c80153b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_m(mask,op1,op2,31); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-3.c new file mode 100644 index 0000000..cfe7c27 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_m(mask,op1,op2,32); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-1.c new file mode 100644 index 0000000..a27ef98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_m(mask,op1,op2,vl); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-2.c new file mode 100644 index 0000000..c0c5bf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_m(mask,op1,op2,31); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-3.c new file mode 100644 index 0000000..9fcfd9e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_m(mask,op1,op2,32); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.c new file mode 100644 index 0000000..77ac74e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.c new file mode 100644 index 0000000..32e65cd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_mu(mask,merge,op1,op2,31); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.c new file mode 100644 index 0000000..522e14d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_mu(mask,merge,op1,op2,32); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.c new file mode 100644 index 0000000..1629f45 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.c new file mode 100644 index 0000000..293a7d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_mu(mask,merge,op1,op2,31); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.c new file mode 100644 index 0000000..3522184 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2_mu(mask,merge,op1,op2,32); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-1.c new file mode 100644 index 0000000..d8a356f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2(op1,op2,vl); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1(op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2(op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4(op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-2.c new file mode 100644 index 0000000..473ea26 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2(op1,op2,31); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1(op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2(op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4(op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-3.c new file mode 100644 index 0000000..9971160 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2(op1,op2,32); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1(op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2(op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4(op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-1.c new file mode 100644 index 0000000..40ce0f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2(op1,op2,vl); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1(op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2(op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4(op1,op2,vl); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-2.c new file mode 100644 index 0000000..1dd8d58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2(op1,op2,31); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1(op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2(op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4(op1,op2,31); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-3.c new file mode 100644 index 0000000..039dda9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmslt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf8_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf4_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8mf2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m1_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m2_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m4_b2(op1,op2,32); +} + + +vbool1_t test___riscv_vmslt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i8m8_b1(op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf4_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16mf2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m1_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m2_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m4_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmslt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i16m8_b2(op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32mf2_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m1_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m4_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmslt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i32m8_b4(op1,op2,32); +} + + +vbool64_t test___riscv_vmslt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m1_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmslt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmslt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m4_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmslt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmslt_vx_i64m8_b8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.c new file mode 100644 index 0000000..431aec3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_m(mask,op1,op2,vl); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmsltu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.c new file mode 100644 index 0000000..2701f0c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_m(mask,op1,op2,31); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmsltu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.c new file mode 100644 index 0000000..405f292 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_m(mask,op1,op2,32); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmsltu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.c new file mode 100644 index 0000000..0fbc0bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_m(mask,op1,op2,vl); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.c new file mode 100644 index 0000000..3dc5ae8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_m(mask,op1,op2,31); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.c new file mode 100644 index 0000000..2a67239 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_m(mask,op1,op2,32); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-1.c new file mode 100644 index 0000000..e8264e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmsltu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-2.c new file mode 100644 index 0000000..6142941 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_mu(mask,merge,op1,op2,31); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmsltu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-3.c new file mode 100644 index 0000000..e90ee46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_mu(mask,merge,op1,op2,32); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmsltu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-1.c new file mode 100644 index 0000000..9df3cda --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-2.c new file mode 100644 index 0000000..c2f48ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_mu(mask,merge,op1,op2,31); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-3.c new file mode 100644 index 0000000..5d3ed53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2_mu(mask,merge,op1,op2,32); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-1.c new file mode 100644 index 0000000..67dd60b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2(op1,op2,vl); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmsltu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-2.c new file mode 100644 index 0000000..a23c3c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2(op1,op2,31); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1(op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2(op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4(op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmsltu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-3.c new file mode 100644 index 0000000..a004b04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2(op1,op2,32); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1(op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2(op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4(op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmsltu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-1.c new file mode 100644 index 0000000..1afba99 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2(op1,op2,vl); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-2.c new file mode 100644 index 0000000..9d12bee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2(op1,op2,31); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1(op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2(op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4(op1,op2,31); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-3.c new file mode 100644 index 0000000..dcf461d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsltu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf8_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf4_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8mf2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m1_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m2_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m4_b2(op1,op2,32); +} + + +vbool1_t test___riscv_vmsltu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u8m8_b1(op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf4_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16mf2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m1_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m2_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m4_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmsltu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u16m8_b2(op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32mf2_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m1_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m4_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsltu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u32m8_b4(op1,op2,32); +} + + +vbool64_t test___riscv_vmsltu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m1_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsltu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsltu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m4_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsltu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmsltu_vx_u64m8_b8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsltu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ -- 2.7.4