From 57dba04afbb7e06d3c1399bc38a2831c158ea478 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Fri, 23 Apr 2021 11:27:33 -0500 Subject: [PATCH] arm: mach-k3: am642: Add support for boot device detection AM642 allows for booting from primary or backup boot media. Both media can be chosen individually based on switch settings. ROM looks for a valid image in primary boot media, if not found then looks in backup boot media. In order to pass this boot media information to boot loader, ROM stores a value at a particular address. Add support for reading this information and determining the boot media correctly. Signed-off-by: Keerthy Signed-off-by: Dave Gerlach --- arch/arm/mach-k3/am642_init.c | 98 +++++++++++++++++++++++++++ arch/arm/mach-k3/include/mach/am64_hardware.h | 48 +++++++++++++ arch/arm/mach-k3/include/mach/am64_spl.h | 44 ++++++++++++ arch/arm/mach-k3/include/mach/hardware.h | 4 ++ arch/arm/mach-k3/include/mach/spl.h | 4 ++ 5 files changed, 198 insertions(+) create mode 100644 arch/arm/mach-k3/include/mach/am64_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/am64_spl.h diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 79de049..54944af 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "common.h" #if defined(CONFIG_SPL_BUILD) @@ -25,4 +26,101 @@ void board_init_f(ulong dummy) preloader_console_init(); } + +u32 spl_boot_mode(const u32 boot_device) +{ + switch (boot_device) { + case BOOT_DEVICE_MMC1: + return MMCSD_MODE_EMMCBOOT; + + case BOOT_DEVICE_MMC2: + return MMCSD_MODE_FS; + + default: + return MMCSD_MODE_RAW; + } +} + +static u32 __get_backup_bootmedia(u32 main_devstat) +{ + u32 bkup_bootmode = + (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 main_devstat) +{ + u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = + (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 spl_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + + if (bootindex == K3_PRIMARY_BOOTMODE) + return __get_primary_bootmedia(devstat); + else + return __get_backup_bootmedia(devstat); +} #endif diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h new file mode 100644 index 0000000..a447f2e --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: AM64 SoC definitions, structures etc. + * + * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ +#ifndef __ASM_ARCH_AM64_HARDWARE_H +#define __ASM_ARCH_AM64_HARDWARE_H + +#include + +#define CTRL_MMR0_BASE 0x43000000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) + +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078 +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 + +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380 +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 + +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 + +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 + +/* After the cfg mask and shifts have been applied */ +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04 + +/* + * The CTRL_MMR memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR lock/kick-mechanism shared register definitions. + */ +#define CTRLMMR_LOCK_KICK0 0x01008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) +#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 +#define CTRLMMR_LOCK_KICK1 0x0100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +#endif /* __ASM_ARCH_DRA8_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h new file mode 100644 index 0000000..36826cf --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am64_spl.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Keerthy + */ +#ifndef _ASM_ARCH_AM64_SPL_H_ +#define _ASM_ARCH_AM64_SPL_H_ + +/* Primary BootMode devices */ +#define BOOT_DEVICE_RAM 0x00 +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_ETHERNET_RGMII 0x04 +#define BOOT_DEVICE_ETHERNET_RMII 0x05 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_MMC 0x08 +#define BOOT_DEVICE_EMMC 0x09 + +#define BOOT_DEVICE_USB 0x0A +#define BOOT_DEVICE_GPMC_NOR 0x0C +#define BOOT_DEVICE_PCIE 0x0D +#define BOOT_DEVICE_XSPI 0x0E + +#define BOOT_DEVICE_NOBOOT 0x0F + +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_MMC1 0x09 +/* INVALID */ +#define BOOT_DEVICE_MMC2_2 0x1F + +/* Backup BootMode devices */ +#define BACKUP_BOOT_DEVICE_USB 0x01 +#define BACKUP_BOOT_DEVICE_UART 0x03 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x04 +#define BACKUP_BOOT_DEVICE_MMC 0x05 +#define BACKUP_BOOT_DEVICE_SPI 0x06 +#define BACKUP_BOOT_DEVICE_I2C 0x07 + +#define K3_PRIMARY_BOOTMODE 0x0 + +#endif diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 02b3df0..8725e7d 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -14,6 +14,10 @@ #include "j721e_hardware.h" #endif +#ifdef CONFIG_SOC_K3_AM642 +#include "am64_hardware.h" +#endif + /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_ID 0x43000014 #define JTAG_ID_VARIANT_SHIFT 28 diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index a26c8ec..ef1c3fb 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -13,4 +13,8 @@ #ifdef CONFIG_SOC_K3_J721E #include "j721e_spl.h" #endif + +#ifdef CONFIG_SOC_K3_AM642 +#include "am64_spl.h" +#endif #endif /* _ASM_ARCH_SPL_H_ */ -- 2.7.4