From 57aeef5c13538b78ad4fa88cfdc812442b64fb77 Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Fri, 18 Jun 2021 16:30:08 +0200 Subject: [PATCH] ir3/frontend: Switch to srcs/dsts arrays Part-of: --- src/freedreno/ir3/ir3_a4xx.c | 2 +- src/freedreno/ir3/ir3_a6xx.c | 14 ++--- src/freedreno/ir3/ir3_compiler_nir.c | 106 +++++++++++++++++------------------ src/freedreno/ir3/ir3_context.c | 36 ++++++------ src/freedreno/ir3/ir3_shader.c | 2 +- 5 files changed, 80 insertions(+), 80 deletions(-) diff --git a/src/freedreno/ir3/ir3_a4xx.c b/src/freedreno/ir3/ir3_a4xx.c index 968b1d7..486dd1f 100644 --- a/src/freedreno/ir3/ir3_a4xx.c +++ b/src/freedreno/ir3/ir3_a4xx.c @@ -56,7 +56,7 @@ emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr, ldgb = ir3_LDGB(b, ssbo, 0, src0, 0, src1, 0); - ldgb->regs[0]->wrmask = MASK(intr->num_components); + ldgb->dsts[0]->wrmask = MASK(intr->num_components); ldgb->cat6.iim_val = intr->num_components; ldgb->cat6.d = 4; ldgb->cat6.type = TYPE_U32; diff --git a/src/freedreno/ir3/ir3_a6xx.c b/src/freedreno/ir3/ir3_a6xx.c index 9f3efa3..1fbc8f1 100644 --- a/src/freedreno/ir3/ir3_a6xx.c +++ b/src/freedreno/ir3/ir3_a6xx.c @@ -49,7 +49,7 @@ emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr, offset = ir3_get_src(ctx, &intr->src[2])[0]; ldib = ir3_LDIB(b, ir3_ssbo_to_ibo(ctx, intr->src[0]), 0, offset, 0); - ldib->regs[0]->wrmask = MASK(intr->num_components); + ldib->dsts[0]->wrmask = MASK(intr->num_components); ldib->cat6.iim_val = intr->num_components; ldib->cat6.d = 1; ldib->cat6.type = intr->dest.ssa.bit_size == 16 ? TYPE_U16 : TYPE_U32; @@ -193,8 +193,8 @@ emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr) /* even if nothing consume the result, we can't DCE the instruction: */ array_insert(b, b->keeps, atomic); - atomic->regs[0]->wrmask = src1->regs[0]->wrmask; - ir3_reg_tie(atomic->regs[0], atomic->regs[3]); + atomic->dsts[0]->wrmask = src1->dsts[0]->wrmask; + ir3_reg_tie(atomic->dsts[0], atomic->srcs[2]); struct ir3_instruction *split; ir3_split_dest(b, &split, atomic, 0, 1); return split; @@ -212,7 +212,7 @@ emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr, ldib = ir3_LDIB(b, ir3_image_to_ibo(ctx, intr->src[0]), 0, ir3_create_collect(ctx, coords, ncoords), 0); - ldib->regs[0]->wrmask = MASK(intr->num_components); + ldib->dsts[0]->wrmask = MASK(intr->num_components); ldib->cat6.iim_val = intr->num_components; ldib->cat6.d = ncoords; ldib->cat6.type = ir3_get_type_for_image_intrinsic(intr); @@ -345,8 +345,8 @@ emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr) /* even if nothing consume the result, we can't DCE the instruction: */ array_insert(b, b->keeps, atomic); - atomic->regs[0]->wrmask = src1->regs[0]->wrmask; - ir3_reg_tie(atomic->regs[0], atomic->regs[3]); + atomic->dsts[0]->wrmask = src1->dsts[0]->wrmask; + ir3_reg_tie(atomic->dsts[0], atomic->srcs[2]); struct ir3_instruction *split; ir3_split_dest(b, &split, atomic, 0, 1); return split; @@ -365,7 +365,7 @@ emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, resinfo->cat6.typed = false; /* resinfo has no writemask and always writes out 3 components: */ compile_assert(ctx, intr->num_components <= 3); - resinfo->regs[0]->wrmask = MASK(3); + resinfo->dsts[0]->wrmask = MASK(3); ir3_handle_bindless_cat6(resinfo, intr->src[0]); ir3_split_dest(b, dst, resinfo, 0, intr->num_components); diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 4078f89..49484b1 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -89,7 +89,7 @@ create_frag_input(struct ir3_context *ctx, struct ir3_instruction *coord, unsign instr->cat6.iim_val = 1; } else { instr = ir3_BARY_F(block, inloc, 0, ctx->ij[IJ_PERSP_PIXEL], 0); - instr->regs[2]->wrmask = 0x3; + instr->srcs[1]->wrmask = 0x3; } return instr; @@ -647,8 +647,8 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) */ if (cond->opc == OPC_ABSNEG_S && cond->flags == 0 && - (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) { - cond = cond->regs[1]->def->instr; + (cond->srcs[0]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) { + cond = cond->srcs[0]->def->instr; } compile_assert(ctx, bs[1] == bs[2]); @@ -688,11 +688,11 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) // TODO maybe the builders should default to making dst half-precision // if the src's were half precision, to make this less awkward.. otoh // we should probably just do this lowering in NIR. - hi->regs[0]->flags |= IR3_REG_HALF; - lo->regs[0]->flags |= IR3_REG_HALF; + hi->dsts[0]->flags |= IR3_REG_HALF; + lo->dsts[0]->flags |= IR3_REG_HALF; dst[0] = ir3_ADD_S(b, hi, 0, lo, 0); - dst[0]->regs[0]->flags |= IR3_REG_HALF; + dst[0]->dsts[0]->flags |= IR3_REG_HALF; dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32); break; } @@ -759,7 +759,7 @@ emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr, struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0]; struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0]; struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0); - ldc->regs[0]->wrmask = MASK(ncomp); + ldc->dsts[0]->wrmask = MASK(ncomp); ldc->cat6.iim_val = ncomp; ldc->cat6.d = nir_intrinsic_component(intr); ldc->cat6.type = TYPE_U32; @@ -789,9 +789,9 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr, /* First src is ubo index, which could either be an immed or not: */ src0 = ir3_get_src(ctx, &intr->src[0])[0]; if (is_same_type_mov(src0) && - (src0->regs[1]->flags & IR3_REG_IMMED)) { - base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz)); - base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1); + (src0->srcs[0]->flags & IR3_REG_IMMED)) { + base_lo = create_uniform(b, ubo + (src0->srcs[0]->iim_val * ptrsz)); + base_hi = create_uniform(b, ubo + (src0->srcs[0]->iim_val * ptrsz) + 1); } else { base_lo = create_uniform_indirect(b, ubo, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz)); base_hi = create_uniform_indirect(b, ubo + 1, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz)); @@ -865,7 +865,7 @@ emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, resinfo->cat6.type = TYPE_U32; resinfo->cat6.typed = false; /* resinfo has no writemask and always writes out 3 components */ - resinfo->regs[0]->wrmask = MASK(3); + resinfo->dsts[0]->wrmask = MASK(3); ir3_handle_bindless_cat6(resinfo, intr->src[0]); struct ir3_instruction *resinfo_dst; ir3_split_dest(b, &resinfo_dst, resinfo, 0, 1); @@ -906,7 +906,7 @@ emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr, create_immed(b, intr->num_components), 0); ldl->cat6.type = utype_dst(intr->dest); - ldl->regs[0]->wrmask = MASK(intr->num_components); + ldl->dsts[0]->wrmask = MASK(intr->num_components); ldl->barrier_class = IR3_BARRIER_SHARED_R; ldl->barrier_conflict = IR3_BARRIER_SHARED_W; @@ -964,7 +964,7 @@ emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *int load->opc = OPC_LDL; load->cat6.type = utype_dst(intr->dest); - load->regs[0]->wrmask = MASK(intr->num_components); + load->dsts[0]->wrmask = MASK(intr->num_components); load->barrier_class = IR3_BARRIER_SHARED_R; load->barrier_conflict = IR3_BARRIER_SHARED_W; @@ -1095,7 +1095,7 @@ emit_intrinsic_load_scratch(struct ir3_context *ctx, nir_intrinsic_instr *intr, create_immed(b, intr->num_components), 0); ldp->cat6.type = utype_dst(intr->dest); - ldp->regs[0]->wrmask = MASK(intr->num_components); + ldp->dsts[0]->wrmask = MASK(intr->num_components); ldp->barrier_class = IR3_BARRIER_PRIVATE_R; ldp->barrier_conflict = IR3_BARRIER_PRIVATE_W; @@ -1775,7 +1775,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) ir3_LDG(b, addr, 0, offset, 0, create_immed(ctx->block, dest_components), 0); load->cat6.type = TYPE_U32; - load->regs[0]->wrmask = MASK(dest_components); + load->dsts[0]->wrmask = MASK(dest_components); load->barrier_class = IR3_BARRIER_BUFFER_R; load->barrier_conflict = IR3_BARRIER_BUFFER_W; @@ -1799,7 +1799,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) */ struct ir3_instruction *offset = ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0); - offset->regs[0]->wrmask = 0x3; + offset->dsts[0]->wrmask = 0x3; offset->cat5.type = TYPE_F32; ir3_split_dest(b, dst, offset, 0, 2); @@ -1985,7 +1985,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) case nir_intrinsic_load_sample_id_no_per_sample: if (!ctx->samp_id) { ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1); - ctx->samp_id->regs[0]->flags |= IR3_REG_HALF; + ctx->samp_id->dsts[0]->flags |= IR3_REG_HALF; } dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32); break; @@ -2006,7 +2006,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) if (!ctx->frag_face) { ctx->so->frag_face = true; ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1); - ctx->frag_face->regs[0]->flags |= IR3_REG_HALF; + ctx->frag_face->dsts[0]->flags |= IR3_REG_HALF; } /* for fragface, we get -1 for back and 0 for front. However this is * the inverse of what nir expects (where ~0 is true). @@ -2028,7 +2028,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) if (!ctx->work_group_id) { ctx->work_group_id = create_sysval_input(ctx, SYSTEM_VALUE_WORKGROUP_ID, 0x7); - ctx->work_group_id->regs[0]->flags |= IR3_REG_SHARED; + ctx->work_group_id->dsts[0]->flags |= IR3_REG_SHARED; } ir3_split_dest(b, dst, ctx->work_group_id, 0, 3); break; @@ -2072,8 +2072,8 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) cond->cat2.condition = IR3_COND_NE; /* condition always goes in predicate register: */ - cond->regs[0]->num = regid(REG_P0, 0); - cond->regs[0]->flags &= ~IR3_REG_SSA; + cond->dsts[0]->num = regid(REG_P0, 0); + cond->dsts[0]->flags &= ~IR3_REG_SSA; if (intr->intrinsic == nir_intrinsic_demote || intr->intrinsic == nir_intrinsic_demote_if) { @@ -2085,7 +2085,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) /* Side-effects should not be moved on a different side of the kill */ kill->barrier_class = IR3_BARRIER_IMAGE_W | IR3_BARRIER_BUFFER_W; kill->barrier_conflict = IR3_BARRIER_IMAGE_W | IR3_BARRIER_BUFFER_W; - kill->regs[1]->num = regid(REG_P0, 0); + kill->srcs[0]->num = regid(REG_P0, 0); array_insert(ctx->ir, ctx->ir->predicates, kill); array_insert(b, b->keeps, kill); @@ -2105,7 +2105,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) cond->cat2.condition = IR3_COND_NE; /* condition always goes in predicate register: */ - cond->regs[0]->num = regid(REG_P0, 0); + cond->dsts[0]->num = regid(REG_P0, 0); kill = ir3_PREDT(b, cond, 0); @@ -2636,7 +2636,7 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex) assert(opc != OPC_META_TEX_PREFETCH); /* only need first 3 components: */ - sam->regs[0]->wrmask = 0x7; + sam->dsts[0]->wrmask = 0x7; ir3_split_dest(b, dst, sam, 0, 3); /* we need to sample the alpha separately with a non-ASTC @@ -2791,7 +2791,7 @@ resolve_phis(struct ir3_context *ctx, struct ir3_block *block) if (get_block(ctx, nsrc->pred) == pred) { if (nsrc->src.ssa->parent_instr->type == nir_instr_type_ssa_undef) { /* Create an ir3 undef */ - ir3_src_create(phi, INVALID_REG, phi->regs[0]->flags & ~IR3_REG_DEST); + ir3_src_create(phi, INVALID_REG, phi->dsts[0]->flags & ~IR3_REG_DEST); } else { struct ir3_instruction *src = ir3_get_src(ctx, &nsrc->src)[0]; __ssa_src(phi, src, 0); @@ -3042,8 +3042,8 @@ emit_stream_out(struct ir3_context *ctx) /* setup 'if (vtxcnt < maxvtxcnt)' condition: */ cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0); - cond->regs[0]->num = regid(REG_P0, 0); - cond->regs[0]->flags &= ~IR3_REG_SSA; + cond->dsts[0]->num = regid(REG_P0, 0); + cond->dsts[0]->flags &= ~IR3_REG_SSA; cond->cat2.condition = IR3_COND_LT; /* condition goes on previous block to the conditional, @@ -3216,7 +3216,7 @@ setup_input(struct ir3_context *ctx, nir_intrinsic_instr *intr) * first see a vec2 index at slot N, and then later a vec4, * the wrmask of the resulting overlapped vec2 and vec4 is 0xf */ - input->regs[0]->wrmask |= compmask; + input->dsts[0]->wrmask |= compmask; } for (int i = 0; i < ncomp + frac; i++) { @@ -3225,7 +3225,7 @@ setup_input(struct ir3_context *ctx, nir_intrinsic_instr *intr) /* fixup the src wrmask to avoid validation fail */ if (ctx->inputs[idx] && (ctx->inputs[idx] != input)) { - ctx->inputs[idx]->regs[1]->wrmask = input->regs[0]->wrmask; + ctx->inputs[idx]->srcs[0]->wrmask = input->dsts[0]->wrmask; continue; } @@ -3259,11 +3259,11 @@ pack_inlocs(struct ir3_context *ctx) foreach_block (block, &ctx->ir->block_list) { foreach_instr (instr, &block->instr_list) { if (is_input(instr)) { - unsigned inloc = instr->regs[1]->iim_val; + unsigned inloc = instr->srcs[0]->iim_val; unsigned i = inloc / 4; unsigned j = inloc % 4; - compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED); + compile_assert(ctx, instr->srcs[0]->flags & IR3_REG_IMMED); compile_assert(ctx, i < so->inputs_count); used_components[i] |= 1 << j; @@ -3343,11 +3343,11 @@ pack_inlocs(struct ir3_context *ctx) foreach_block (block, &ctx->ir->block_list) { foreach_instr (instr, &block->instr_list) { if (is_input(instr)) { - unsigned inloc = instr->regs[1]->iim_val; + unsigned inloc = instr->srcs[0]->iim_val; unsigned i = inloc / 4; unsigned j = inloc % 4; - instr->regs[1]->iim_val = so->inputs[i].inloc + j; + instr->srcs[0]->iim_val = so->inputs[i].inloc + j; } else if (instr->opc == OPC_META_TEX_PREFETCH) { unsigned i = instr->prefetch.input_offset / 4; unsigned j = instr->prefetch.input_offset % 4; @@ -3696,17 +3696,17 @@ fixup_binning_pass(struct ir3_context *ctx, struct ir3_instruction *end) unsigned i, j; /* first pass, remove unused outputs from the IR level outputs: */ - for (i = 0, j = 0; i < end->regs_count - 1; i++) { + for (i = 0, j = 0; i < end->srcs_count; i++) { unsigned outidx = end->end.outidxs[i]; unsigned slot = so->outputs[outidx].slot; if (output_slot_used_for_binning(slot)) { - end->regs[j + 1] = end->regs[i + 1]; + end->srcs[j] = end->srcs[i]; end->end.outidxs[j] = end->end.outidxs[i]; j++; } } - end->regs_count = j + 1; + end->srcs_count = j; /* second pass, cleanup the unused slots in ir3_shader_variant::outputs * table: @@ -3718,7 +3718,7 @@ fixup_binning_pass(struct ir3_context *ctx, struct ir3_instruction *end) so->outputs[j] = so->outputs[i]; /* fixup outidx to point to new output table entry: */ - for (unsigned k = 0; k < end->regs_count - 1; k++) { + for (unsigned k = 0; k < end->srcs_count; k++) { if (end->end.outidxs[k] == i) { end->end.outidxs[k] = j; break; @@ -3757,8 +3757,8 @@ collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir) fetch->tex_id = instr->prefetch.tex; fetch->samp_id = instr->prefetch.samp; } - fetch->wrmask = instr->regs[0]->wrmask; - fetch->dst = instr->regs[0]->num; + fetch->wrmask = instr->dsts[0]->wrmask; + fetch->dst = instr->dsts[0]->num; fetch->src = instr->prefetch.input_offset; /* These are the limits on a5xx/a6xx, we might need to @@ -3771,7 +3771,7 @@ collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir) ctx->so->total_in = MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2); - fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF); + fetch->half_precision = !!(instr->dsts[0]->flags & IR3_REG_HALF); /* Remove the prefetch placeholder instruction: */ list_delinit(&instr->node); @@ -4032,23 +4032,23 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, assert(in->opc == OPC_META_INPUT); unsigned inidx = in->input.inidx; - in->regs[0]->num = so->nonbinning->inputs[inidx].regid; + in->dsts[0]->num = so->nonbinning->inputs[inidx].regid; } } else if (ctx->tcs_header) { /* We need to have these values in the same registers between VS and TCS * since the VS chains to TCS and doesn't get the sysvals redelivered. */ - ctx->tcs_header->regs[0]->num = regid(0, 0); - ctx->primitive_id->regs[0]->num = regid(0, 1); + ctx->tcs_header->dsts[0]->num = regid(0, 0); + ctx->primitive_id->dsts[0]->num = regid(0, 1); } else if (ctx->gs_header) { /* We need to have these values in the same registers between producer * (VS or DS) and GS since the producer chains to GS and doesn't get * the sysvals redelivered. */ - ctx->gs_header->regs[0]->num = regid(0, 0); - ctx->primitive_id->regs[0]->num = regid(0, 1); + ctx->gs_header->dsts[0]->num = regid(0, 0); + ctx->primitive_id->dsts[0]->num = regid(0, 1); } else if (so->num_sampler_prefetch) { assert(so->type == MESA_SHADER_FRAGMENT); int idx = 0; @@ -4058,7 +4058,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, continue; assert(idx < 2); - instr->regs[0]->num = idx; + instr->dsts[0]->num = idx; idx++; } } @@ -4091,9 +4091,9 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, struct ir3_instruction *end = find_end(so->ir); - for (unsigned i = 1; i < end->regs_count; i++) { - unsigned outidx = end->end.outidxs[i - 1]; - struct ir3_register *reg = end->regs[i]; + for (unsigned i = 0; i < end->srcs_count; i++) { + unsigned outidx = end->end.outidxs[i]; + struct ir3_register *reg = end->srcs[i]; so->outputs[outidx].regid = reg->num; so->outputs[outidx].half = !!(reg->flags & IR3_REG_HALF); @@ -4105,16 +4105,16 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, if (pre_assign_inputs && !so->inputs[inidx].sysval) { if (VALIDREG(so->nonbinning->inputs[inidx].regid)) { - compile_assert(ctx, in->regs[0]->num == + compile_assert(ctx, in->dsts[0]->num == so->nonbinning->inputs[inidx].regid); - compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) == + compile_assert(ctx, !!(in->dsts[0]->flags & IR3_REG_HALF) == so->nonbinning->inputs[inidx].half); } so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid; so->inputs[inidx].half = so->nonbinning->inputs[inidx].half; } else { - so->inputs[inidx].regid = in->regs[0]->num; - so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF); + so->inputs[inidx].regid = in->dsts[0]->num; + so->inputs[inidx].half = !!(in->dsts[0]->flags & IR3_REG_HALF); } } diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c index 00ad005..c0f2fb1 100644 --- a/src/freedreno/ir3/ir3_context.c +++ b/src/freedreno/ir3/ir3_context.c @@ -246,7 +246,7 @@ ir3_put_dst(struct ir3_context *ctx, nir_dest *dst) for (unsigned i = 0; i < ctx->last_dst_n; i++) { if (!ctx->last_dst[i]) continue; - if (ctx->last_dst[i]->regs[0]->flags & IR3_REG_SHARED) { + if (ctx->last_dst[i]->dsts[0]->flags & IR3_REG_SHARED) { ctx->last_dst[i] = ir3_MOV(ctx->block, ctx->last_dst[i], TYPE_U32); } } @@ -258,9 +258,9 @@ ir3_put_dst(struct ir3_context *ctx, nir_dest *dst) ir3_set_dst_type(dst, true); ir3_fixup_src_type(dst); if (dst->opc == OPC_META_SPLIT) { - ir3_set_dst_type(ssa(dst->regs[1]), true); - ir3_fixup_src_type(ssa(dst->regs[1])); - dst->regs[1]->flags |= IR3_REG_HALF; + ir3_set_dst_type(ssa(dst->srcs[0]), true); + ir3_fixup_src_type(ssa(dst->srcs[0])); + dst->srcs[0]->flags |= IR3_REG_HALF; } } } @@ -293,7 +293,7 @@ ir3_put_dst(struct ir3_context *ctx, nir_dest *dst) static unsigned dest_flags(struct ir3_instruction *instr) { - return instr->regs[0]->flags & (IR3_REG_HALF | IR3_REG_SHARED); + return instr->dsts[0]->flags & (IR3_REG_HALF | IR3_REG_SHARED); } struct ir3_instruction * @@ -337,7 +337,7 @@ ir3_create_collect(struct ir3_context *ctx, struct ir3_instruction *const *arr, * scalar registers. * */ - if (elem->regs[0]->flags & IR3_REG_ARRAY) { + if (elem->dsts[0]->flags & IR3_REG_ARRAY) { type_t type = (flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32; elem = ir3_MOV(block, elem, type); } @@ -346,7 +346,7 @@ ir3_create_collect(struct ir3_context *ctx, struct ir3_instruction *const *arr, __ssa_src(collect, elem, flags); } - collect->regs[0]->wrmask = MASK(arrsz); + collect->dsts[0]->wrmask = MASK(arrsz); return collect; } @@ -358,7 +358,7 @@ void ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst, struct ir3_instruction *src, unsigned base, unsigned n) { - if ((n == 1) && (src->regs[0]->wrmask == 0x1) && + if ((n == 1) && (src->dsts[0]->wrmask == 0x1) && /* setup_input needs ir3_split_dest to generate a SPLIT instruction */ src->opc != OPC_META_INPUT) { dst[0] = src; @@ -367,10 +367,10 @@ ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst, } if (src->opc == OPC_META_COLLECT) { - debug_assert((base + n) < src->regs_count); + debug_assert((base + n) <= src->srcs_count); for (int i = 0; i < n; i++) { - dst[i] = ssa(src->regs[i + base + 1]); + dst[i] = ssa(src->srcs[i + base]); } return; @@ -385,7 +385,7 @@ ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst, __ssa_src(split, src, flags); split->split.off = i + base; - if (src->regs[0]->wrmask & (1 << (i + base))) + if (src->dsts[0]->wrmask & (1 << (i + base))) dst[j++] = split; } } @@ -443,10 +443,10 @@ create_addr0(struct ir3_block *block, struct ir3_instruction *src, int align) return NULL; } - instr->regs[0]->flags |= IR3_REG_HALF; + instr->dsts[0]->flags |= IR3_REG_HALF; instr = ir3_MOV(block, instr, TYPE_S16); - instr->regs[0]->num = regid(REG_A0, 0); + instr->dsts[0]->num = regid(REG_A0, 0); return instr; } @@ -456,7 +456,7 @@ create_addr1(struct ir3_block *block, unsigned const_val) { struct ir3_instruction *immed = create_immed_typed(block, const_val, TYPE_U16); struct ir3_instruction *instr = ir3_MOV(block, immed, TYPE_U16); - instr->regs[0]->num = regid(REG_A0, 1); + instr->dsts[0]->num = regid(REG_A0, 1); return instr; } @@ -518,8 +518,8 @@ ir3_get_predicate(struct ir3_context *ctx, struct ir3_instruction *src) cond->cat2.condition = IR3_COND_NE; /* condition always goes in predicate register: */ - cond->regs[0]->num = regid(REG_P0, 0); - cond->regs[0]->flags &= ~IR3_REG_SSA; + cond->dsts[0]->num = regid(REG_P0, 0); + cond->dsts[0]->flags &= ~IR3_REG_SSA; return cond; } @@ -616,7 +616,7 @@ ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n, * since that creates a situation that RA can't really handle properly. */ if (!address && !is_meta(src)) { - dst = src->regs[0]; + dst = src->dsts[0]; src->barrier_class |= IR3_BARRIER_ARRAY_W; src->barrier_conflict |= IR3_BARRIER_ARRAY_R | IR3_BARRIER_ARRAY_W; @@ -656,7 +656,7 @@ ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n, dst->array.id = arr->id; dst->array.offset = n; dst->array.base = INVALID_REG; - ir3_src_create(mov, 0, IR3_REG_SSA | flags)->def = src->regs[0]; + ir3_src_create(mov, 0, IR3_REG_SSA | flags)->def = src->dsts[0]; if (arr->last_write && arr->last_write->instr->block == block) ir3_reg_set_last_array(mov, dst, arr->last_write); diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c index aaa8ac4..70a67eb 100644 --- a/src/freedreno/ir3/ir3_shader.c +++ b/src/freedreno/ir3/ir3_shader.c @@ -651,7 +651,7 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out) unsigned i; foreach_input_n (instr, i, ir) { - reg = instr->regs[0]; + reg = instr->dsts[0]; regid = reg->num; fprintf(out, "@in(%sr%d.%c)\tin%d", (reg->flags & IR3_REG_HALF) ? "h" : "", -- 2.7.4