From 579f3f0606c351e9a939e1265d61cb9ace2adac8 Mon Sep 17 00:00:00 2001 From: gonglingqin Date: Thu, 8 Dec 2022 15:39:21 +0800 Subject: [PATCH] [LoongArch] Rename the test file and separate the tests on LA32 and LA64. NFC. Use intrinsic-la32*.c to test the intrinsics of loongarch32. Use intrinsic-la64*.c to test the intrinsics of loongarch64. --- .../{intrinsic-error.c => intrinsic-la32-error.c} | 0 .../LoongArch/{intrinsic.c => intrinsic-la32.c} | 64 ------------------- ...trinsic-error-la64.c => intrinsic-la64-error.c} | 0 clang/test/CodeGen/LoongArch/intrinsic-la64.c | 72 ++++++++++++++++++++++ 4 files changed, 72 insertions(+), 64 deletions(-) rename clang/test/CodeGen/LoongArch/{intrinsic-error.c => intrinsic-la32-error.c} (100%) rename clang/test/CodeGen/LoongArch/{intrinsic.c => intrinsic-la32.c} (56%) rename clang/test/CodeGen/LoongArch/{intrinsic-error-la64.c => intrinsic-la64-error.c} (100%) diff --git a/clang/test/CodeGen/LoongArch/intrinsic-error.c b/clang/test/CodeGen/LoongArch/intrinsic-la32-error.c similarity index 100% rename from clang/test/CodeGen/LoongArch/intrinsic-error.c rename to clang/test/CodeGen/LoongArch/intrinsic-la32-error.c diff --git a/clang/test/CodeGen/LoongArch/intrinsic.c b/clang/test/CodeGen/LoongArch/intrinsic-la32.c similarity index 56% rename from clang/test/CodeGen/LoongArch/intrinsic.c rename to clang/test/CodeGen/LoongArch/intrinsic-la32.c index 5dc788a..ec74a3d 100644 --- a/clang/test/CodeGen/LoongArch/intrinsic.c +++ b/clang/test/CodeGen/LoongArch/intrinsic-la32.c @@ -1,8 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple loongarch32 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=LA32 -// RUN: %clang_cc1 -triple loongarch64 -emit-llvm %s -o - \ -// RUN: | FileCheck %s -check-prefix=LA64 #include @@ -11,11 +9,6 @@ // LA32-NEXT: call void @llvm.loongarch.dbar(i32 0) // LA32-NEXT: ret void // -// LA64-LABEL: @dbar( -// LA64-NEXT: entry: -// LA64-NEXT: call void @llvm.loongarch.dbar(i32 0) -// LA64-NEXT: ret void -// void dbar() { return __builtin_loongarch_dbar(0); } @@ -25,11 +18,6 @@ void dbar() { // LA32-NEXT: call void @llvm.loongarch.ibar(i32 0) // LA32-NEXT: ret void // -// LA64-LABEL: @ibar( -// LA64-NEXT: entry: -// LA64-NEXT: call void @llvm.loongarch.ibar(i32 0) -// LA64-NEXT: ret void -// void ibar() { return __builtin_loongarch_ibar(0); } @@ -39,11 +27,6 @@ void ibar() { // LA32-NEXT: call void @llvm.loongarch.break(i32 1) // LA32-NEXT: ret void // -// LA64-LABEL: @loongarch_break( -// LA64-NEXT: entry: -// LA64-NEXT: call void @llvm.loongarch.break(i32 1) -// LA64-NEXT: ret void -// void loongarch_break() { __builtin_loongarch_break(1); } @@ -53,11 +36,6 @@ void loongarch_break() { // LA32-NEXT: call void @llvm.loongarch.syscall(i32 1) // LA32-NEXT: ret void // -// LA64-LABEL: @syscall( -// LA64-NEXT: entry: -// LA64-NEXT: call void @llvm.loongarch.syscall(i32 1) -// LA64-NEXT: ret void -// void syscall() { __builtin_loongarch_syscall(1); } @@ -72,16 +50,6 @@ void syscall() { // LA32-NEXT: store i32 [[TMP1]], ptr [[B]], align 4 // LA32-NEXT: ret i32 0 // -// LA64-LABEL: @csrrd_w( -// LA64-NEXT: entry: -// LA64-NEXT: [[A:%.*]] = alloca i32, align 4 -// LA64-NEXT: [[B:%.*]] = alloca i32, align 4 -// LA64-NEXT: [[TMP0:%.*]] = call i32 @llvm.loongarch.csrrd.w(i32 1) -// LA64-NEXT: store i32 [[TMP0]], ptr [[A]], align 4 -// LA64-NEXT: [[TMP1:%.*]] = call i32 @llvm.loongarch.csrrd.w(i32 1) -// LA64-NEXT: store i32 [[TMP1]], ptr [[B]], align 4 -// LA64-NEXT: ret i32 0 -// unsigned int csrrd_w() { unsigned int a = __csrrd_w(1); unsigned int b = __builtin_loongarch_csrrd_w(1); @@ -102,20 +70,6 @@ unsigned int csrrd_w() { // LA32-NEXT: store i32 [[TMP3]], ptr [[C]], align 4 // LA32-NEXT: ret i32 0 // -// LA64-LABEL: @csrwr_w( -// LA64-NEXT: entry: -// LA64-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// LA64-NEXT: [[B:%.*]] = alloca i32, align 4 -// LA64-NEXT: [[C:%.*]] = alloca i32, align 4 -// LA64-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// LA64-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// LA64-NEXT: [[TMP1:%.*]] = call i32 @llvm.loongarch.csrwr.w(i32 [[TMP0]], i32 1) -// LA64-NEXT: store i32 [[TMP1]], ptr [[B]], align 4 -// LA64-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// LA64-NEXT: [[TMP3:%.*]] = call i32 @llvm.loongarch.csrwr.w(i32 [[TMP2]], i32 1) -// LA64-NEXT: store i32 [[TMP3]], ptr [[C]], align 4 -// LA64-NEXT: ret i32 0 -// unsigned int csrwr_w(unsigned int a) { unsigned int b = __csrwr_w(a, 1); unsigned int c = __builtin_loongarch_csrwr_w(a, 1); @@ -140,24 +94,6 @@ unsigned int csrwr_w(unsigned int a) { // LA32-NEXT: store i32 [[TMP5]], ptr [[D]], align 4 // LA32-NEXT: ret i32 0 // -// LA64-LABEL: @csrxchg_w( -// LA64-NEXT: entry: -// LA64-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// LA64-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// LA64-NEXT: [[C:%.*]] = alloca i32, align 4 -// LA64-NEXT: [[D:%.*]] = alloca i32, align 4 -// LA64-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// LA64-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// LA64-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// LA64-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// LA64-NEXT: [[TMP2:%.*]] = call i32 @llvm.loongarch.csrxchg.w(i32 [[TMP0]], i32 [[TMP1]], i32 1) -// LA64-NEXT: store i32 [[TMP2]], ptr [[C]], align 4 -// LA64-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// LA64-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// LA64-NEXT: [[TMP5:%.*]] = call i32 @llvm.loongarch.csrxchg.w(i32 [[TMP3]], i32 [[TMP4]], i32 1) -// LA64-NEXT: store i32 [[TMP5]], ptr [[D]], align 4 -// LA64-NEXT: ret i32 0 -// unsigned int csrxchg_w(unsigned int a, unsigned int b) { unsigned int c = __csrxchg_w(a, b, 1); unsigned int d = __builtin_loongarch_csrxchg_w(a, b, 1); diff --git a/clang/test/CodeGen/LoongArch/intrinsic-error-la64.c b/clang/test/CodeGen/LoongArch/intrinsic-la64-error.c similarity index 100% rename from clang/test/CodeGen/LoongArch/intrinsic-error-la64.c rename to clang/test/CodeGen/LoongArch/intrinsic-la64-error.c diff --git a/clang/test/CodeGen/LoongArch/intrinsic-la64.c b/clang/test/CodeGen/LoongArch/intrinsic-la64.c index e5ac673..d2bad0e 100644 --- a/clang/test/CodeGen/LoongArch/intrinsic-la64.c +++ b/clang/test/CodeGen/LoongArch/intrinsic-la64.c @@ -3,6 +3,78 @@ #include +// CHECK-LABEL: @dbar( +// CHECK-NEXT: entry: +// CHECK-NEXT: tail call void @llvm.loongarch.dbar(i32 0) +// CHECK-NEXT: ret void +// +void dbar() { + return __builtin_loongarch_dbar(0); +} + +// CHECK-LABEL: @ibar( +// CHECK-NEXT: entry: +// CHECK-NEXT: tail call void @llvm.loongarch.ibar(i32 0) +// CHECK-NEXT: ret void +// +void ibar() { + return __builtin_loongarch_ibar(0); +} + +// CHECK-LABEL: @loongarch_break( +// CHECK-NEXT: entry: +// CHECK-NEXT: tail call void @llvm.loongarch.break(i32 1) +// CHECK-NEXT: ret void +// +void loongarch_break() { + __builtin_loongarch_break(1); +} + +// CHECK-LABEL: @syscall( +// CHECK-NEXT: entry: +// CHECK-NEXT: tail call void @llvm.loongarch.syscall(i32 1) +// CHECK-NEXT: ret void +// +void syscall() { + __builtin_loongarch_syscall(1); +} + +// CHECK-LABEL: @csrrd_w( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.loongarch.csrrd.w(i32 1) +// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.loongarch.csrrd.w(i32 1) +// CHECK-NEXT: ret i32 0 +// +unsigned int csrrd_w() { + unsigned int a = __csrrd_w(1); + unsigned int b = __builtin_loongarch_csrrd_w(1); + return 0; +} + +// CHECK-LABEL: @csrwr_w( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.loongarch.csrwr.w(i32 [[A:%.*]], i32 1) +// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.loongarch.csrwr.w(i32 [[A]], i32 1) +// CHECK-NEXT: ret i32 0 +// +unsigned int csrwr_w(unsigned int a) { + unsigned int b = __csrwr_w(a, 1); + unsigned int c = __builtin_loongarch_csrwr_w(a, 1); + return 0; +} + +// CHECK-LABEL: @csrxchg_w( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.loongarch.csrxchg.w(i32 [[A:%.*]], i32 [[B:%.*]], i32 1) +// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.loongarch.csrxchg.w(i32 [[A]], i32 [[B]], i32 1) +// CHECK-NEXT: ret i32 0 +// +unsigned int csrxchg_w(unsigned int a, unsigned int b) { + unsigned int c = __csrxchg_w(a, b, 1); + unsigned int d = __builtin_loongarch_csrxchg_w(a, b, 1); + return 0; +} + // CHECK-LABEL: @crc_w_b_w( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.b.w(i32 [[A:%.*]], i32 [[B:%.*]]) -- 2.7.4