From 570d47a0107f7dea936e0ab9a0b0352b4acbf87e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 11 Aug 2018 05:33:00 +0000 Subject: [PATCH] [X86] Change the MOV32ri64 pseudo instruction to def a GR64 directly instead of wrapping it in a SUBREG_TO_REG. Now we switch to the subregister in expandPostRAPseudos where we already switched the opcode. This simplifies a few isel patterns that used the pseudo directly. And magically seems to have improved our ability to CSE it in the undef-label.ll test. llvm-svn: 339496 --- llvm/lib/Target/X86/X86InstrCompiler.td | 16 ++++------------ llvm/lib/Target/X86/X86InstrInfo.cpp | 7 ++++++- llvm/test/CodeGen/X86/abi-isel.ll | 10 +++++----- llvm/test/CodeGen/X86/atomic_mi.ll | 4 ++-- .../CodeGen/X86/conditional-tailcall-samedest.mir | 2 +- llvm/test/CodeGen/X86/flags-copy-lowering.mir | 16 ++++++++-------- llvm/test/CodeGen/X86/licm-nested.ll | 2 +- llvm/test/CodeGen/X86/select-mmx.ll | 4 ++-- llvm/test/CodeGen/X86/select_const.ll | 6 +++--- llvm/test/CodeGen/X86/tail-call-conditional.mir | 2 +- llvm/test/CodeGen/X86/undef-label.ll | 19 ++++++++----------- llvm/test/DebugInfo/MIR/X86/live-debug-values.mir | 2 +- 12 files changed, 42 insertions(+), 48 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index 7f6ef70..bc258f6 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -319,16 +319,14 @@ def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", // that would make it more difficult to rematerialize. let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in -def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>; +def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "", []>; // This 64-bit pseudo-move can be used for both a 64-bit constant that is // actually the zero-extension of a 32-bit constant and for labels in the // x86-64 small code model. def mov64imm32 : ComplexPattern; -let AddedComplexity = 1 in -def : Pat<(i64 mov64imm32:$src), - (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>; +def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>; // Use sbb to materialize carry bit. let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in { @@ -2060,13 +2058,7 @@ let Predicates = [HasBMI, NoTBM] in { def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)), (BEXTR32rm addr:$src1, (MOV32ri imm:$src2))>; def : Pat<(X86bextr GR64:$src1, mov64imm32:$src2), - (BEXTR64rr GR64:$src1, - (SUBREG_TO_REG (i64 0), - (MOV32ri64 mov64imm32:$src2), - sub_32bit))>; + (BEXTR64rr GR64:$src1, (MOV32ri64 mov64imm32:$src2))>; def : Pat<(X86bextr (loadi64 addr:$src1), mov64imm32:$src2), - (BEXTR64rm addr:$src1, - (SUBREG_TO_REG (i64 0), - (MOV32ri64 mov64imm32:$src2), - sub_32bit))>; + (BEXTR64rm addr:$src1, (MOV32ri64 mov64imm32:$src2))>; } // HasBMI, NoTBM diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 961c187..289faee 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -4267,9 +4267,14 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { case X86::VMOVUPSZ256mr_NOVLX: return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr), get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm); - case X86::MOV32ri64: + case X86::MOV32ri64: { + unsigned Reg = MIB->getOperand(0).getReg(); + unsigned Reg32 = RI.getSubReg(Reg, X86::sub_32bit); MI.setDesc(get(X86::MOV32ri)); + MIB->getOperand(0).setReg(Reg32); + MIB.addReg(Reg, RegState::ImplicitDefine); return true; + } // KNL does not recognize dependency-breaking idioms for mask registers, // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1. diff --git a/llvm/test/CodeGen/X86/abi-isel.ll b/llvm/test/CodeGen/X86/abi-isel.ll index 0c98201..62b8a8c 100644 --- a/llvm/test/CodeGen/X86/abi-isel.ll +++ b/llvm/test/CodeGen/X86/abi-isel.ll @@ -7751,8 +7751,8 @@ define i8* @bam02() nounwind { ; ; LINUX-64-PIC-LABEL: bam02: ; LINUX-64-PIC: # %bb.0: # %entry +; LINUX-64-PIC-NEXT: movq ptr@{{.*}}(%rip), %rcx ; LINUX-64-PIC-NEXT: movl $262144, %eax # imm = 0x40000 -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx ; LINUX-64-PIC-NEXT: addq (%rcx), %rax ; LINUX-64-PIC-NEXT: retq ; @@ -7781,22 +7781,22 @@ define i8* @bam02() nounwind { ; ; DARWIN-64-STATIC-LABEL: bam02: ; DARWIN-64-STATIC: ## %bb.0: ## %entry +; DARWIN-64-STATIC-NEXT: movq _ptr@{{.*}}(%rip), %rcx ; DARWIN-64-STATIC-NEXT: movl $262144, %eax ## imm = 0x40000 -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx ; DARWIN-64-STATIC-NEXT: addq (%rcx), %rax ; DARWIN-64-STATIC-NEXT: retq ; ; DARWIN-64-DYNAMIC-LABEL: bam02: ; DARWIN-64-DYNAMIC: ## %bb.0: ## %entry +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@{{.*}}(%rip), %rcx ; DARWIN-64-DYNAMIC-NEXT: movl $262144, %eax ## imm = 0x40000 -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx ; DARWIN-64-DYNAMIC-NEXT: addq (%rcx), %rax ; DARWIN-64-DYNAMIC-NEXT: retq ; ; DARWIN-64-PIC-LABEL: bam02: ; DARWIN-64-PIC: ## %bb.0: ## %entry +; DARWIN-64-PIC-NEXT: movq _ptr@{{.*}}(%rip), %rcx ; DARWIN-64-PIC-NEXT: movl $262144, %eax ## imm = 0x40000 -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx ; DARWIN-64-PIC-NEXT: addq (%rcx), %rax ; DARWIN-64-PIC-NEXT: retq @@ -7946,8 +7946,8 @@ define i8* @bam05() nounwind { ; ; LINUX-64-PIC-LABEL: bam05: ; LINUX-64-PIC: # %bb.0: # %entry +; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx ; LINUX-64-PIC-NEXT: movl $262144, %eax # imm = 0x40000 -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx ; LINUX-64-PIC-NEXT: addq (%rcx), %rax ; LINUX-64-PIC-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/atomic_mi.ll b/llvm/test/CodeGen/X86/atomic_mi.ll index 1852680..308e138 100644 --- a/llvm/test/CodeGen/X86/atomic_mi.ll +++ b/llvm/test/CodeGen/X86/atomic_mi.ll @@ -2050,8 +2050,8 @@ define void @fadd_64g() { define void @fadd_32imm() { ; X64-LABEL: fadd_32imm: ; X64: # %bb.0: -; X64-NEXT: movl $3735928559, %eax # imm = 0xDEADBEEF ; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X64-NEXT: movl $3735928559, %eax # imm = 0xDEADBEEF ; X64-NEXT: addss (%rax), %xmm0 ; X64-NEXT: movss %xmm0, (%rax) ; X64-NEXT: retq @@ -2082,8 +2082,8 @@ define void @fadd_32imm() { define void @fadd_64imm() { ; X64-LABEL: fadd_64imm: ; X64: # %bb.0: -; X64-NEXT: movl $3735928559, %eax # imm = 0xDEADBEEF ; X64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; X64-NEXT: movl $3735928559, %eax # imm = 0xDEADBEEF ; X64-NEXT: addsd (%rax), %xmm0 ; X64-NEXT: movsd %xmm0, (%rax) ; X64-NEXT: retq diff --git a/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir b/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir index fc91221..ab75e3f 100644 --- a/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir +++ b/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir @@ -124,7 +124,7 @@ body: | JMP_1 %bb.3 bb.3.init.check.i: - dead $edi = MOV32ri64 @static_local_guard, implicit-def $rdi + dead $edi = MOV32ri @static_local_guard, implicit-def $rdi TCRETURNdi64 @initialize_static_local, 0, csr_64, implicit $rsp, implicit $rdi bb.4.sw.bb2: diff --git a/llvm/test/CodeGen/X86/flags-copy-lowering.mir b/llvm/test/CodeGen/X86/flags-copy-lowering.mir index d599175..1e9cee4 100644 --- a/llvm/test/CodeGen/X86/flags-copy-lowering.mir +++ b/llvm/test/CodeGen/X86/flags-copy-lowering.mir @@ -144,12 +144,12 @@ body: | ; CHECK-NEXT: JMP_1 %bb.3 bb.1: - %3:gr32 = MOV32ri64 42 + %3:gr32 = MOV32ri 42 $eax = COPY %3 RET 0, $eax bb.2: - %4:gr32 = MOV32ri64 43 + %4:gr32 = MOV32ri 43 $eax = COPY %4 RET 0, $eax @@ -205,12 +205,12 @@ body: | RET 0, $eax bb.2: - %3:gr32 = MOV32ri64 42 + %3:gr32 = MOV32ri 42 $eax = COPY %3 RET 0, $eax bb.3: - %4:gr32 = MOV32ri64 43 + %4:gr32 = MOV32ri 43 $eax = COPY %4 RET 0, $eax @@ -991,12 +991,12 @@ body: | ; CHECK-NEXT: JMP_1 %bb.3 bb.1: - %5:gr32 = MOV32ri64 42 + %5:gr32 = MOV32ri 42 $eax = COPY %5 RET 0, $eax bb.2: - %6:gr32 = MOV32ri64 43 + %6:gr32 = MOV32ri 43 $eax = COPY %6 RET 0, $eax @@ -1045,12 +1045,12 @@ body: | ; CHECK-NEXT: JMP_1 %bb.2 bb.1: - %3:gr32 = MOV32ri64 42 + %3:gr32 = MOV32ri 42 $eax = COPY %3 RET 0, $eax bb.2: - %4:gr32 = MOV32ri64 43 + %4:gr32 = MOV32ri 43 $eax = COPY %4 RET 0, $eax diff --git a/llvm/test/CodeGen/X86/licm-nested.ll b/llvm/test/CodeGen/X86/licm-nested.ll index c029508..1f85f72 100644 --- a/llvm/test/CodeGen/X86/licm-nested.ll +++ b/llvm/test/CodeGen/X86/licm-nested.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -mtriple=x86_64-apple-darwin < %s -o /dev/null -stats -info-output-file - | grep "hoisted out of loops" | grep 5 +; RUN: llc -mtriple=x86_64-apple-darwin < %s -o /dev/null -stats -info-output-file - | grep "hoisted out of loops" | grep 3 ; MachineLICM should be able to hoist the symbolic addresses out of ; the inner loops. diff --git a/llvm/test/CodeGen/X86/select-mmx.ll b/llvm/test/CodeGen/X86/select-mmx.ll index f24111f..da00f0f 100644 --- a/llvm/test/CodeGen/X86/select-mmx.ll +++ b/llvm/test/CodeGen/X86/select-mmx.ll @@ -17,8 +17,8 @@ define i64 @test47(i64 %arg) { ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: testq %rdi, %rdi ; X64-NEXT: movl $7, %ecx -; X64-NEXT: cmoveq %rcx, %rax -; X64-NEXT: movq %rax, %mm0 +; X64-NEXT: cmovneq %rax, %rcx +; X64-NEXT: movq %rcx, %mm0 ; X64-NEXT: psllw %mm0, %mm0 ; X64-NEXT: movq %mm0, %rax ; X64-NEXT: retq diff --git a/llvm/test/CodeGen/X86/select_const.ll b/llvm/test/CodeGen/X86/select_const.ll index 6f79e8c..aad18fe 100644 --- a/llvm/test/CodeGen/X86/select_const.ll +++ b/llvm/test/CodeGen/X86/select_const.ll @@ -484,9 +484,9 @@ define i64 @opaque_constant(i1 %cond, i64 %x) { ; CHECK-LABEL: opaque_constant: ; CHECK: # %bb.0: ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: movl $23, %ecx -; CHECK-NEXT: movq $-4, %rax -; CHECK-NEXT: cmoveq %rcx, %rax +; CHECK-NEXT: movq $-4, %rcx +; CHECK-NEXT: movl $23, %eax +; CHECK-NEXT: cmovneq %rcx, %rax ; CHECK-NEXT: movabsq $4294967297, %rcx # imm = 0x100000001 ; CHECK-NEXT: andq %rcx, %rax ; CHECK-NEXT: xorl %edx, %edx diff --git a/llvm/test/CodeGen/X86/tail-call-conditional.mir b/llvm/test/CodeGen/X86/tail-call-conditional.mir index 22d315e..77d1e46 100644 --- a/llvm/test/CodeGen/X86/tail-call-conditional.mir +++ b/llvm/test/CodeGen/X86/tail-call-conditional.mir @@ -79,7 +79,7 @@ body: | TCRETURNdi64 @f2, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi bb.4: - dead $eax = MOV32ri64 123, implicit-def $rax + dead $eax = MOV32ri 123, implicit-def $rax RET 0, $rax ... diff --git a/llvm/test/CodeGen/X86/undef-label.ll b/llvm/test/CodeGen/X86/undef-label.ll index 04aaf9c..b4be383 100644 --- a/llvm/test/CodeGen/X86/undef-label.ll +++ b/llvm/test/CodeGen/X86/undef-label.ll @@ -10,20 +10,17 @@ define void @xyz() { ; CHECK-LABEL: xyz: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl $g, %eax -; CHECK-NEXT: movq %rax, %xmm1 -; CHECK-NEXT: xorps %xmm0, %xmm0 -; CHECK-NEXT: ucomisd %xmm0, %xmm1 +; CHECK-NEXT: movq %rax, %xmm0 +; CHECK-NEXT: xorps %xmm1, %xmm1 +; CHECK-NEXT: ucomisd %xmm1, %xmm0 ; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: jnp .LBB0_3 -; CHECK-NEXT: .LBB0_1: # %foo.preheader -; CHECK-NEXT: movl $g, %eax -; CHECK-NEXT: movq %rax, %xmm1 +; CHECK-NEXT: jnp .LBB0_2 ; CHECK-NEXT: .p2align 4, 0x90 -; CHECK-NEXT: .LBB0_2: # %foo +; CHECK-NEXT: .LBB0_1: # %foo ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: ucomisd %xmm0, %xmm1 -; CHECK-NEXT: ja .LBB0_2 -; CHECK-NEXT: .LBB0_3: # %bar +; CHECK-NEXT: ucomisd %xmm1, %xmm0 +; CHECK-NEXT: ja .LBB0_1 +; CHECK-NEXT: .LBB0_2: # %bar ; CHECK-NEXT: retq entry: br i1 fcmp oeq (double bitcast (i64 ptrtoint (i32* @g to i64) to double), double 0.000000e+00), label %bar, label %foo diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir index 0f022bc..c3558aa 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir @@ -246,7 +246,7 @@ body: | liveins: $ecx MOV32mr $rip, 1, _, @m, _, $ecx, debug-location !43 :: (store 4 into @m, !tbaa !44) - dead undef $edi = MOV32ri64 @.str, implicit-def $rdi, debug-location !46 + dead undef $edi = MOV32ri @.str, implicit-def $rdi, debug-location !46 dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !47 $esi = MOV32rr killed $ecx, debug-location !46 CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $esi, implicit $al, implicit-def $rsp, implicit-def dead $eax, debug-location !46 -- 2.7.4