From 570228780990568f27288961f8ffe17de8f31e3d Mon Sep 17 00:00:00 2001 From: "Duncan P. N. Exon Smith" Date: Sat, 27 Feb 2016 19:09:00 +0000 Subject: [PATCH] CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC In all but one case, change the DFAPacketizer API to take MachineInstr& instead of MachineInstr*. In DFAPacketizer::endPacket(), take MachineBasicBlock::iterator. Besides cleaning up the API, this is in search of PR26753. llvm-svn: 262142 --- llvm/include/llvm/CodeGen/DFAPacketizer.h | 24 +++---- llvm/lib/CodeGen/DFAPacketizer.cpp | 19 +++--- llvm/lib/Target/AMDGPU/R600Packetizer.cpp | 73 +++++++++++----------- .../lib/Target/Hexagon/HexagonMachineScheduler.cpp | 4 +- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 65 ++++++++++--------- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h | 11 ++-- 6 files changed, 98 insertions(+), 98 deletions(-) diff --git a/llvm/include/llvm/CodeGen/DFAPacketizer.h b/llvm/include/llvm/CodeGen/DFAPacketizer.h index 2a0ff23..2145884 100644 --- a/llvm/include/llvm/CodeGen/DFAPacketizer.h +++ b/llvm/include/llvm/CodeGen/DFAPacketizer.h @@ -108,11 +108,11 @@ public: // Check if the resources occupied by a machine instruction are available // in the current state. - bool canReserveResources(llvm::MachineInstr *MI); + bool canReserveResources(llvm::MachineInstr &MI); // Reserve the resources occupied by a machine instruction and change the // current state to reflect that change. - void reserveResources(llvm::MachineInstr *MI); + void reserveResources(llvm::MachineInstr &MI); const InstrItineraryData *getInstrItins() const { return InstrItins; } }; @@ -156,33 +156,31 @@ public: DFAPacketizer *getResourceTracker() {return ResourceTracker;} // addToPacket - Add MI to the current packet. - virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) { - MachineBasicBlock::iterator MII = MI; - CurrentPacketMIs.push_back(MI); + virtual MachineBasicBlock::iterator addToPacket(MachineInstr &MI) { + CurrentPacketMIs.push_back(&MI); ResourceTracker->reserveResources(MI); - return MII; + return MI; } // End the current packet and reset the state of the packetizer. // Overriding this function allows the target-specific packetizer // to perform custom finalization. - virtual void endPacket(MachineBasicBlock *MBB, MachineInstr *MI); + virtual void endPacket(MachineBasicBlock *MBB, + MachineBasicBlock::iterator MI); // Perform initialization before packetizing an instruction. This // function is supposed to be overrided by the target dependent packetizer. virtual void initPacketizerState() {} // Check if the given instruction I should be ignored by the packetizer. - virtual bool ignorePseudoInstruction(const MachineInstr *I, + virtual bool ignorePseudoInstruction(const MachineInstr &I, const MachineBasicBlock *MBB) { return false; } // Return true if instruction MI can not be packetized with any other // instruction, which means that MI itself is a packet. - virtual bool isSoloInstruction(const MachineInstr *MI) { - return true; - } + virtual bool isSoloInstruction(const MachineInstr &MI) { return true; } // Check if the packetizer should try to add the given instruction to // the current packet. One reasons for which it may not be desirable @@ -190,9 +188,7 @@ public: // would cause a stall. // If this function returns "false", the current packet will be ended, // and the instruction will be added to the next packet. - virtual bool shouldAddToPacket(const MachineInstr *MI) { - return true; - } + virtual bool shouldAddToPacket(const MachineInstr &MI) { return true; } // Check if it is legal to packetize SUI and SUJ together. virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { diff --git a/llvm/lib/CodeGen/DFAPacketizer.cpp b/llvm/lib/CodeGen/DFAPacketizer.cpp index c8a3d38..a4ed61b 100644 --- a/llvm/lib/CodeGen/DFAPacketizer.cpp +++ b/llvm/lib/CodeGen/DFAPacketizer.cpp @@ -135,16 +135,16 @@ void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { // Check if the resources occupied by a machine instruction are available // in the current state. -bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) { - const llvm::MCInstrDesc &MID = MI->getDesc(); +bool DFAPacketizer::canReserveResources(llvm::MachineInstr &MI) { + const llvm::MCInstrDesc &MID = MI.getDesc(); return canReserveResources(&MID); } // Reserve the resources occupied by a machine instruction and change the // current state to reflect that change. -void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) { - const llvm::MCInstrDesc &MID = MI->getDesc(); +void DFAPacketizer::reserveResources(llvm::MachineInstr &MI) { + const llvm::MCInstrDesc &MID = MI.getDesc(); reserveResources(&MID); } @@ -195,10 +195,11 @@ VLIWPacketizerList::~VLIWPacketizerList() { // End the current packet, bundle packet instructions and reset DFA state. -void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, MachineInstr *MI) { +void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, + MachineBasicBlock::iterator MI) { if (CurrentPacketMIs.size() > 1) { - MachineInstr *MIFirst = CurrentPacketMIs.front(); - finalizeBundle(*MBB, MIFirst->getIterator(), MI->getIterator()); + MachineInstr &MIFirst = *CurrentPacketMIs.front(); + finalizeBundle(*MBB, MIFirst.getIterator(), MI.getInstrIterator()); } CurrentPacketMIs.clear(); ResourceTracker->clearResources(); @@ -222,7 +223,7 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, // The main packetizer loop. for (; BeginItr != EndItr; ++BeginItr) { - MachineInstr *MI = BeginItr; + MachineInstr &MI = *BeginItr; initPacketizerState(); // End the current packet if needed. @@ -235,7 +236,7 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, if (ignorePseudoInstruction(MI, MBB)) continue; - SUnit *SUI = MIToSUnit[MI]; + SUnit *SUI = MIToSUnit[&MI]; assert(SUI && "Missing SUnit Info!"); // Ask DFA if machine resource is available for MI. diff --git a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp index 3fdd7d1..5d8ce41 100644 --- a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp +++ b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp @@ -63,8 +63,8 @@ private: bool VLIW5; bool ConsideredInstUsesAlreadyWrittenVectorElement; - unsigned getSlot(const MachineInstr *MI) const { - return TRI.getHWRegChan(MI->getOperand(0).getReg()); + unsigned getSlot(const MachineInstr &MI) const { + return TRI.getHWRegChan(MI.getOperand(0).getReg()); } /// \returns register to PV chan mapping for bundle/single instructions that @@ -81,7 +81,7 @@ private: int LastDstChan = -1; do { bool isTrans = false; - int BISlot = getSlot(&*BI); + int BISlot = getSlot(*BI); if (LastDstChan >= BISlot) isTrans = true; LastDstChan = BISlot; @@ -129,7 +129,7 @@ private: return Result; } - void substitutePV(MachineInstr *MI, const DenseMap &PVs) + void substitutePV(MachineInstr &MI, const DenseMap &PVs) const { unsigned Ops[] = { AMDGPU::OpName::src0, @@ -137,13 +137,13 @@ private: AMDGPU::OpName::src2 }; for (unsigned i = 0; i < 3; i++) { - int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); + int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]); if (OperandIdx < 0) continue; - unsigned Src = MI->getOperand(OperandIdx).getReg(); + unsigned Src = MI.getOperand(OperandIdx).getReg(); const DenseMap::const_iterator It = PVs.find(Src); if (It != PVs.end()) - MI->getOperand(OperandIdx).setReg(It->second); + MI.getOperand(OperandIdx).setReg(It->second); } } public: @@ -162,23 +162,23 @@ public: } // ignorePseudoInstruction - Ignore bundling of pseudo instructions. - bool ignorePseudoInstruction(const MachineInstr *MI, + bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override { return false; } // isSoloInstruction - return true if instruction MI can not be packetized // with any other instruction, which means that MI itself is a packet. - bool isSoloInstruction(const MachineInstr *MI) override { - if (TII->isVector(*MI)) + bool isSoloInstruction(const MachineInstr &MI) override { + if (TII->isVector(MI)) return true; - if (!TII->isALUInstr(MI->getOpcode())) + if (!TII->isALUInstr(MI.getOpcode())) return true; - if (MI->getOpcode() == AMDGPU::GROUP_BARRIER) + if (MI.getOpcode() == AMDGPU::GROUP_BARRIER) return true; // XXX: This can be removed once the packetizer properly handles all the // LDS instruction group restrictions. - if (TII->isLDSInstr(MI->getOpcode())) + if (TII->isLDSInstr(MI.getOpcode())) return true; return false; } @@ -187,7 +187,7 @@ public: // together. bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override { MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr(); - if (getSlot(MII) == getSlot(MIJ)) + if (getSlot(*MII) == getSlot(*MIJ)) ConsideredInstUsesAlreadyWrittenVectorElement = true; // Does MII and MIJ share the same pred_sel ? int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel), @@ -231,20 +231,23 @@ public: MI->getOperand(LastOp).setImm(Bit); } - bool isBundlableWithCurrentPMI(MachineInstr *MI, + bool isBundlableWithCurrentPMI(MachineInstr &MI, const DenseMap &PV, std::vector &BS, bool &isTransSlot) { - isTransSlot = TII->isTransOnly(MI); + isTransSlot = TII->isTransOnly(&MI); assert (!isTransSlot || VLIW5); // Is the dst reg sequence legal ? if (!isTransSlot && !CurrentPacketMIs.empty()) { - if (getSlot(MI) <= getSlot(CurrentPacketMIs.back())) { - if (ConsideredInstUsesAlreadyWrittenVectorElement && - !TII->isVectorOnly(MI) && VLIW5) { + if (getSlot(MI) <= getSlot(*CurrentPacketMIs.back())) { + if (ConsideredInstUsesAlreadyWrittenVectorElement && + !TII->isVectorOnly(&MI) && VLIW5) { isTransSlot = true; - DEBUG(dbgs() << "Considering as Trans Inst :"; MI->dump();); + DEBUG({ + dbgs() << "Considering as Trans Inst :"; + MI.dump(); + }); } else return false; @@ -252,18 +255,18 @@ public: } // Are the Constants limitations met ? - CurrentPacketMIs.push_back(MI); + CurrentPacketMIs.push_back(&MI); if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) { - DEBUG( + DEBUG({ dbgs() << "Couldn't pack :\n"; - MI->dump(); + MI.dump(); dbgs() << "with the following packets :\n"; for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) { CurrentPacketMIs[i]->dump(); dbgs() << "\n"; } dbgs() << "because of Consts read limitations\n"; - ); + }); CurrentPacketMIs.pop_back(); return false; } @@ -271,31 +274,31 @@ public: // Is there a BankSwizzle set that meet Read Port limitations ? if (!TII->fitsReadPortLimitations(CurrentPacketMIs, PV, BS, isTransSlot)) { - DEBUG( + DEBUG({ dbgs() << "Couldn't pack :\n"; - MI->dump(); + MI.dump(); dbgs() << "with the following packets :\n"; for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) { CurrentPacketMIs[i]->dump(); dbgs() << "\n"; } dbgs() << "because of Read port limitations\n"; - ); + }); CurrentPacketMIs.pop_back(); return false; } // We cannot read LDS source registrs from the Trans slot. - if (isTransSlot && TII->readsLDSSrcReg(MI)) + if (isTransSlot && TII->readsLDSSrcReg(&MI)) return false; CurrentPacketMIs.pop_back(); return true; } - MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override { + MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override { MachineBasicBlock::iterator FirstInBundle = - CurrentPacketMIs.empty() ? MI : CurrentPacketMIs.front(); + CurrentPacketMIs.empty() ? &MI : CurrentPacketMIs.front(); const DenseMap &PV = getPreviousVector(FirstInBundle); std::vector BS; @@ -308,9 +311,9 @@ public: AMDGPU::OpName::bank_swizzle); MI->getOperand(Op).setImm(BS[i]); } - unsigned Op = TII->getOperandIdx(MI->getOpcode(), - AMDGPU::OpName::bank_swizzle); - MI->getOperand(Op).setImm(BS.back()); + unsigned Op = + TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::bank_swizzle); + MI.getOperand(Op).setImm(BS.back()); if (!CurrentPacketMIs.empty()) setIsLastBit(CurrentPacketMIs.back(), 0); substitutePV(MI, PV); @@ -320,8 +323,8 @@ public: } return It; } - endPacket(MI->getParent(), MI); - if (TII->isTransOnly(MI)) + endPacket(MI.getParent(), MI); + if (TII->isTransOnly(&MI)) return MI; return VLIWPacketizerList::addToPacket(MI); } diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 7a52d68..035cea3 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -48,7 +48,7 @@ bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { // in the current cycle. switch (SU->getInstr()->getOpcode()) { default: - if (!ResourcesModel->canReserveResources(SU->getInstr())) + if (!ResourcesModel->canReserveResources(*SU->getInstr())) return false; case TargetOpcode::EXTRACT_SUBREG: case TargetOpcode::INSERT_SUBREG: @@ -100,7 +100,7 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) { switch (SU->getInstr()->getOpcode()) { default: - ResourcesModel->reserveResources(SU->getInstr()); + ResourcesModel->reserveResources(*SU->getInstr()); break; case TargetOpcode::EXTRACT_SUBREG: case TargetOpcode::INSERT_SUBREG: diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 657713f..9f55489 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -254,9 +254,9 @@ bool HexagonPacketizerList::canReserveResourcesForConstExt() { // return true, otherwise, return false. bool HexagonPacketizerList::tryAllocateResourcesForConstExt(bool Reserve) { auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc()); - bool Avail = ResourceTracker->canReserveResources(ExtMI); + bool Avail = ResourceTracker->canReserveResources(*ExtMI); if (Reserve && Avail) - ResourceTracker->reserveResources(ExtMI); + ResourceTracker->reserveResources(*ExtMI); MF.DeleteMachineInstr(ExtMI); return Avail; } @@ -762,7 +762,7 @@ bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr *MI, int NewOpcode = HII->getDotNewOp(MI); const MCInstrDesc &D = HII->get(NewOpcode); MachineInstr *NewMI = MF.CreateMachineInstr(D, DebugLoc()); - bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI); + bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI); MF.DeleteMachineInstr(NewMI); if (!ResourcesAvailable) return false; @@ -911,31 +911,31 @@ void HexagonPacketizerList::initPacketizerState() { } // Ignore bundling of pseudo instructions. -bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr *MI, - const MachineBasicBlock*) { - if (MI->isDebugValue()) +bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI, + const MachineBasicBlock *) { + if (MI.isDebugValue()) return true; - if (MI->isCFIInstruction()) + if (MI.isCFIInstruction()) return false; // We must print out inline assembly. - if (MI->isInlineAsm()) + if (MI.isInlineAsm()) return false; - if (MI->isImplicitDef()) + if (MI.isImplicitDef()) return false; // We check if MI has any functional units mapped to it. If it doesn't, // we ignore the instruction. - const MCInstrDesc& TID = MI->getDesc(); + const MCInstrDesc& TID = MI.getDesc(); auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass()); unsigned FuncUnits = IS->getUnits(); return !FuncUnits; } -bool HexagonPacketizerList::isSoloInstruction(const MachineInstr *MI) { - if (MI->isEHLabel() || MI->isCFIInstruction()) +bool HexagonPacketizerList::isSoloInstruction(const MachineInstr &MI) { + if (MI.isEHLabel() || MI.isCFIInstruction()) return true; // Consider inline asm to not be a solo instruction by default. @@ -943,19 +943,19 @@ bool HexagonPacketizerList::isSoloInstruction(const MachineInstr *MI) { // removed, and placed outside of the packet (before or after, depending // on dependencies). This is to reduce the impact of inline asm as a // "packet splitting" instruction. - if (MI->isInlineAsm() && !ScheduleInlineAsm) + if (MI.isInlineAsm() && !ScheduleInlineAsm) return true; // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints: // trap, pause, barrier, icinva, isync, and syncht are solo instructions. // They must not be grouped with other instructions in a packet. - if (isSchedBarrier(MI)) + if (isSchedBarrier(&MI)) return true; - if (HII->isSolo(MI)) + if (HII->isSolo(&MI)) return true; - if (MI->getOpcode() == Hexagon::A2_nop) + if (MI.getOpcode() == Hexagon::A2_nop) return true; return false; @@ -1139,7 +1139,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { const unsigned FrameSize = MF.getFrameInfo()->getStackSize(); // Solo instructions cannot go in the packet. - assert(!isSoloInstruction(I) && "Unexpected solo instr!"); + assert(!isSoloInstruction(*I) && "Unexpected solo instr!"); if (cannotCoexist(I, J)) return false; @@ -1444,26 +1444,25 @@ bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) { return false; } - MachineBasicBlock::iterator -HexagonPacketizerList::addToPacket(MachineInstr *MI) { +HexagonPacketizerList::addToPacket(MachineInstr &MI) { MachineBasicBlock::iterator MII = MI; - MachineBasicBlock *MBB = MI->getParent(); - if (MI->isImplicitDef()) { - unsigned R = MI->getOperand(0).getReg(); + MachineBasicBlock *MBB = MI.getParent(); + if (MI.isImplicitDef()) { + unsigned R = MI.getOperand(0).getReg(); if (Hexagon::IntRegsRegClass.contains(R)) { MCSuperRegIterator S(R, HRI, false); - MI->addOperand(MachineOperand::CreateReg(*S, true, true)); + MI.addOperand(MachineOperand::CreateReg(*S, true, true)); } return MII; } assert(ResourceTracker->canReserveResources(MI)); - bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI); + bool ExtMI = HII->isExtended(&MI) || HII->isConstExtended(&MI); bool Good = true; if (GlueToNewValueJump) { - MachineInstr *NvjMI = ++MII; + MachineInstr &NvjMI = *++MII; // We need to put both instructions in the same packet: MI and NvjMI. // Either of them can require a constant extender. Try to add both to // the current packet, and if that fails, end the packet and start a @@ -1472,7 +1471,7 @@ HexagonPacketizerList::addToPacket(MachineInstr *MI) { if (ExtMI) Good = tryAllocateResourcesForConstExt(true); - bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI); + bool ExtNvjMI = HII->isExtended(&NvjMI) || HII->isConstExtended(&NvjMI); if (Good) { if (ResourceTracker->canReserveResources(NvjMI)) ResourceTracker->reserveResources(NvjMI); @@ -1497,8 +1496,8 @@ HexagonPacketizerList::addToPacket(MachineInstr *MI) { reserveResourcesForConstExt(); } } - CurrentPacketMIs.push_back(MI); - CurrentPacketMIs.push_back(NvjMI); + CurrentPacketMIs.push_back(&MI); + CurrentPacketMIs.push_back(&NvjMI); return MII; } @@ -1506,23 +1505,23 @@ HexagonPacketizerList::addToPacket(MachineInstr *MI) { if (ExtMI && !tryAllocateResourcesForConstExt(true)) { endPacket(MBB, MI); if (PromotedToDotNew) - demoteToDotOld(MI); + demoteToDotOld(&MI); ResourceTracker->reserveResources(MI); reserveResourcesForConstExt(); } - CurrentPacketMIs.push_back(MI); + CurrentPacketMIs.push_back(&MI); return MII; } void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB, - MachineInstr *MI) { + MachineBasicBlock::iterator MI) { OldPacketMIs = CurrentPacketMIs; VLIWPacketizerList::endPacket(MBB, MI); } -bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr *MI) { - return !producesStall(MI); +bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) { + return !producesStall(&MI); } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h index aff8917..3f8ed5a 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h @@ -50,12 +50,12 @@ public: void initPacketizerState() override; // ignorePseudoInstruction - Ignore bundling of pseudo instructions. - bool ignorePseudoInstruction(const MachineInstr *MI, + bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override; // isSoloInstruction - return true if instruction MI can not be packetized // with any other instruction, which means that MI itself is a packet. - bool isSoloInstruction(const MachineInstr *MI) override; + bool isSoloInstruction(const MachineInstr &MI) override; // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ // together. @@ -65,9 +65,10 @@ public: // and SUJ. bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override; - MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override; - void endPacket(MachineBasicBlock *MBB, MachineInstr *MI) override; - bool shouldAddToPacket(const MachineInstr *MI) override; + MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override; + void endPacket(MachineBasicBlock *MBB, + MachineBasicBlock::iterator MI) override; + bool shouldAddToPacket(const MachineInstr &MI) override; void unpacketizeSoloInstrs(MachineFunction &MF); -- 2.7.4