From 56c25575ce7434e63b5b52351e5072566250018b Mon Sep 17 00:00:00 2001 From: eopXD Date: Thu, 18 May 2023 05:27:40 -0700 Subject: [PATCH] [1/3][RISCV] Define machine instruction to write an immediate into vxrm This patch-set wants to model rounding mode for the fixed-point intrinsics of the RVV C intrinsics. The specification PR: [riscv-non-isa/rvv-intrinsic-doc#222](https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222) The 3 patches is a proof-of-concept with a bottom-up approach Going from machine instruction to LLVM intrinsics, then to the C intrinsics. The 3 patches applies the rounding mode control on the `vaadd` instruction. Proceeding patches will extend the change to all other fixed-point computations. --- This is the 1st commit of the patch-set. This patch gives a name to the machine instruction that writes an immediate into the CSR `vxrm`. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D151395 --- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 ++ llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 +- llvm/test/CodeGen/RISCV/rvv/vxrm.mir | 31 ++++++++++++++++++++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/RISCV/rvv/vxrm.mir diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 313ea4c..6fb4e6b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1743,6 +1743,8 @@ def WriteFRM : WriteSysReg; def WriteFRMImm : WriteSysRegImm; def SwapFRMImm : SwapSysRegImm; +def WriteVXRMImm : WriteSysRegImm; + let hasSideEffects = true in { def ReadFFLAGS : ReadSysReg; def WriteFFLAGS : WriteSysReg; diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 6c9bb3b..43475e82 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -331,7 +331,7 @@ def : SysReg<"dscratch1", 0x7B3>; //===----------------------------------------------------------------------===// def : SysReg<"vstart", 0x008>; def : SysReg<"vxsat", 0x009>; -def : SysReg<"vxrm", 0x00A>; +def SysRegVXRM : SysReg<"vxrm", 0x00A>; def : SysReg<"vcsr", 0x00F>; def SysRegVL : SysReg<"vl", 0xC20>; def : SysReg<"vtype", 0xC21>; diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm.mir b/llvm/test/CodeGen/RISCV/rvv/vxrm.mir new file mode 100644 index 0000000..2fb3f4d4 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/vxrm.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -stop-after prologepilog -o - %s | FileCheck %s --check-prefix=MIR +# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=ASM + +--- +name: verify_vxrm +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9, $x10 + + ; MIR-LABEL: name: verify_vxrm + ; MIR: liveins: $v8, $v9, $x10 + ; MIR-NEXT: {{ $}} + ; MIR-NEXT: dead $x0 = PseudoVSETVLI renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; MIR-NEXT: WriteVXRMImm 0, implicit-def $vxrm + ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 renamable $v8, renamable $v9, $noreg, 3 /* e8 */, implicit $vxrm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + ; MIR-NEXT: PseudoRET implicit $v8 + ; ASM-LABEL: verify_vxrm: + ; ASM: # %bb.0: + ; ASM-NEXT: vsetvli zero, a0, e8, mf8, ta, ma + ; ASM-NEXT: csrwi vxrm, 0 + ; ASM-NEXT: vaadd.vv v8, v8, v9 + ; ASM-NEXT: ret + %0:vr = COPY $v8 + %1:vr = COPY $v9 + dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype + WriteVXRMImm 0, implicit-def $vxrm + renamable $v8 = PseudoVAADD_VV_MF8 killed renamable $v8, killed renamable $v9, $noreg, 3 /* e8 */, implicit $vxrm, implicit $vl, implicit $vtype + PseudoRET implicit $v8 +... -- 2.7.4