From 5654a3dd0add58984e2c3247c70946d2ae0175f6 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 25 Nov 2020 10:42:08 -0800 Subject: [PATCH] [RISCV] Add test cases showing that we don't recognize the select form of NABS in SelectionDAGBuilder so we end up with branches. NFC There's a FIXME that it should produce (sub 0, (abs)). --- llvm/test/CodeGen/RISCV/neg-abs.ll | 49 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/neg-abs.ll b/llvm/test/CodeGen/RISCV/neg-abs.ll index 2171a1d..10290a0 100644 --- a/llvm/test/CodeGen/RISCV/neg-abs.ll +++ b/llvm/test/CodeGen/RISCV/neg-abs.ll @@ -24,6 +24,29 @@ define i32 @neg_abs32(i32 %x) { ret i32 %neg } +define i32 @select_neg_abs32(i32 %x) { +; RV32-LABEL: select_neg_abs32: +; RV32: # %bb.0: +; RV32-NEXT: bltz a0, .LBB1_2 +; RV32-NEXT: # %bb.1: +; RV32-NEXT: neg a0, a0 +; RV32-NEXT: .LBB1_2: +; RV32-NEXT: ret +; +; RV64-LABEL: select_neg_abs32: +; RV64: # %bb.0: +; RV64-NEXT: sext.w a1, a0 +; RV64-NEXT: bltz a1, .LBB1_2 +; RV64-NEXT: # %bb.1: +; RV64-NEXT: negw a0, a0 +; RV64-NEXT: .LBB1_2: +; RV64-NEXT: ret + %1 = icmp slt i32 %x, 0 + %2 = sub nsw i32 0, %x + %3 = select i1 %1, i32 %x, i32 %2 + ret i32 %3 +} + define i64 @neg_abs64(i64 %x) { ; RV32-LABEL: neg_abs64: ; RV32: # %bb.0: @@ -46,3 +69,29 @@ define i64 @neg_abs64(i64 %x) { %neg = sub nsw i64 0, %abs ret i64 %neg } + +define i64 @select_neg_abs64(i64 %x) { +; RV32-LABEL: select_neg_abs64: +; RV32: # %bb.0: +; RV32-NEXT: bltz a1, .LBB3_2 +; RV32-NEXT: # %bb.1: +; RV32-NEXT: snez a2, a0 +; RV32-NEXT: add a1, a1, a2 +; RV32-NEXT: neg a1, a1 +; RV32-NEXT: neg a0, a0 +; RV32-NEXT: .LBB3_2: +; RV32-NEXT: ret +; +; RV64-LABEL: select_neg_abs64: +; RV64: # %bb.0: +; RV64-NEXT: bltz a0, .LBB3_2 +; RV64-NEXT: # %bb.1: +; RV64-NEXT: neg a0, a0 +; RV64-NEXT: .LBB3_2: +; RV64-NEXT: ret + %1 = icmp slt i64 %x, 0 + %2 = sub nsw i64 0, %x + %3 = select i1 %1, i64 %x, i64 %2 + ret i64 %3 +} + -- 2.7.4