From 5603ed60ad6cd6370010e0746faef9f823c1fa72 Mon Sep 17 00:00:00 2001 From: luxufan <932494295@qq.com> Date: Mon, 12 Apr 2021 13:28:00 +0800 Subject: [PATCH] [RISCV] Fix StackOffset calculation when using sp to access the fixed stack object in the case of rvv vector objects existed When rvv vector objects existed, using sp to access the fixed stack object will pass the rvv vector objects field. So the StackOffset needs add a scalable offset of the size of rvv vector objects field Differential Revision: https://reviews.llvm.org/D100286 --- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 9 ++++++--- llvm/test/CodeGen/RISCV/rvv/localvar.ll | 5 ++++- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 8ad11ae..f1fd921 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -749,9 +749,12 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, // RVV->getRVVPadding() and it can be zero. It allows us to align the RVV // objects to 8 bytes. if (MFI.getStackID(FI) == TargetStackID::Default) { - Offset += StackOffset::getFixed(MFI.getStackSize()); - if (FI < 0) - Offset += StackOffset::getFixed(RVFI->getLibCallStackSize()); + if (MFI.isFixedObjectIndex(FI)) { + Offset += StackOffset::get(MFI.getStackSize() + RVFI->getRVVPadding() + + RVFI->getLibCallStackSize(), RVFI->getRVVStackSize()); + } else { + Offset += StackOffset::getFixed(MFI.getStackSize()); + } } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) { Offset += StackOffset::get( alignTo(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(), 8), diff --git a/llvm/test/CodeGen/RISCV/rvv/localvar.ll b/llvm/test/CodeGen/RISCV/rvv/localvar.ll index 6b95249..4368eec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/localvar.ll +++ b/llvm/test/CodeGen/RISCV/rvv/localvar.ll @@ -294,7 +294,10 @@ define i64 @fixed_object(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: slli a0, a0, 3 ; RV64IV-NEXT: sub sp, sp, a0 -; RV64IV-NEXT: ld a0, 32(sp) +; RV64IV-NEXT: csrr a0, vlenb +; RV64IV-NEXT: slli a0, a0, 3 +; RV64IV-NEXT: add a0, sp, a0 +; RV64IV-NEXT: ld a0, 32(a0) ; RV64IV-NEXT: csrr a1, vlenb ; RV64IV-NEXT: slli a1, a1, 3 ; RV64IV-NEXT: add sp, sp, a1 -- 2.7.4