From 55244beeee8ad0fd21c0f6a98996ff11301e397c Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Mon, 9 Sep 2019 11:21:14 +0000 Subject: [PATCH] [AArch64][SVE] Implement abs and neg intrinsics Summary: This patch implements two arithmetic intrinsics: * int_aarch64_sve_abs * int_aarch64_sve_neg testing the support for scalable vector types in intrinsics added in D65930. Reviewed By: greened Differential Revision: https://reviews.llvm.org/D65931 llvm-svn: 371388 --- llvm/include/llvm/IR/IntrinsicsAArch64.td | 23 ++++- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 4 +- llvm/lib/Target/AArch64/SVEInstrFormats.td | 16 +++- .../CodeGen/AArch64/sve-intrinsics-int-arith.ll | 99 ++++++++++++++++++++++ 4 files changed, 136 insertions(+), 6 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index dc2ead3..a81127e 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -749,9 +749,6 @@ def int_aarch64_ttest : GCCBuiltin<"__builtin_arm_ttest">, [IntrNoMem, IntrHasSideEffects]>; } -//===----------------------------------------------------------------------===// -// SVE - def llvm_nxv2i1_ty : LLVMType; def llvm_nxv4i1_ty : LLVMType; def llvm_nxv8i1_ty : LLVMType; @@ -764,6 +761,13 @@ def llvm_nxv4f32_ty : LLVMType; def llvm_nxv2f64_ty : LLVMType; let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". + class AdvSIMD_Merged1VectorArg_Intrinsic + : Intrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, + LLVMMatchType<0>], + [IntrNoMem]>; + // This class of intrinsics are not intended to be useful within LLVM IR but // are instead here to support some of the more regid parts of the ACLE. class Builtin_SVCVT @@ -771,8 +775,21 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". Intrinsic<[OUT], [OUT, llvm_nxv16i1_ty, IN], [IntrNoMem]>; } +//===----------------------------------------------------------------------===// +// SVE + +let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". + +// +// Integer arithmetic +// + +def int_aarch64_sve_abs : AdvSIMD_Merged1VectorArg_Intrinsic; +def int_aarch64_sve_neg : AdvSIMD_Merged1VectorArg_Intrinsic; + // // Floating-point comparisons // def int_aarch64_sve_fcvtzs_i32f16 : Builtin_SVCVT<"svcvt_s32_f16_m", llvm_nxv4i32_ty, llvm_nxv8f16_ty>; +} diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 7359ea3..0813c41 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -94,8 +94,8 @@ let Predicates = [HasSVE] in { defm UXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b011, "uxth">; defm SXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b100, "sxtw">; defm UXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b101, "uxtw">; - defm ABS_ZPmZ : sve_int_un_pred_arit_0< 0b110, "abs">; - defm NEG_ZPmZ : sve_int_un_pred_arit_0< 0b111, "neg">; + defm ABS_ZPmZ : sve_int_un_pred_arit_0< 0b110, "abs", int_aarch64_sve_abs>; + defm NEG_ZPmZ : sve_int_un_pred_arit_0< 0b111, "neg", int_aarch64_sve_neg>; defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls">; defm CLZ_ZPmZ : sve_int_un_pred_arit_1< 0b001, "clz">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index dfd6c57..8c8713b 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -279,6 +279,14 @@ let Predicates = [HasSVE] in { defm PTRUES : sve_int_ptrue<0b001, "ptrues">; } +//===----------------------------------------------------------------------===// +// SVE pattern match helpers. +//===----------------------------------------------------------------------===// + +class SVE_3_Op_Pat +: Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)), + (inst $Op1, $Op2, $Op3)>; //===----------------------------------------------------------------------===// // SVE Predicate Misc Group @@ -2835,11 +2843,17 @@ class sve_int_un_pred_arit sz8_64, bits<4> opc, let ElementSize = zprty.ElementSize; } -multiclass sve_int_un_pred_arit_0 opc, string asm> { +multiclass sve_int_un_pred_arit_0 opc, string asm, + SDPatternOperator op> { def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>; def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>; def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; + + def : SVE_3_Op_Pat(NAME # _B)>; + def : SVE_3_Op_Pat(NAME # _H)>; + def : SVE_3_Op_Pat(NAME # _S)>; + def : SVE_3_Op_Pat(NAME # _D)>; } multiclass sve_int_un_pred_arit_0_h opc, string asm> { diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll new file mode 100644 index 0000000..08e475b --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll @@ -0,0 +1,99 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s + +; +; ABS +; + +define @abs_i8( %a, %pg, %b) { +; CHECK-LABEL: abs_i8: +; CHECK: abs z0.b, p0/m, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.abs.nxv16i8( %a, + %pg, + %b) + ret %out +} + +define @abs_i16( %a, %pg, %b) { +; CHECK-LABEL: abs_i16: +; CHECK: abs z0.h, p0/m, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.abs.nxv8i16( %a, + %pg, + %b) + ret %out +} + +define @abs_i32( %a, %pg, %b) { +; CHECK-LABEL: abs_i32: +; CHECK: abs z0.s, p0/m, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.abs.nxv4i32( %a, + %pg, + %b) + ret %out +} + +define @abs_i64( %a, %pg, %b) { +; CHECK-LABEL: abs_i64: +; CHECK: abs z0.d, p0/m, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.abs.nxv2i64( %a, + %pg, + %b) + ret %out +} + +; +; NEG +; + +define @neg_i8( %a, %pg, %b) { +; CHECK-LABEL: neg_i8: +; CHECK: neg z0.b, p0/m, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.neg.nxv16i8( %a, + %pg, + %b) + ret %out +} + +define @neg_i16( %a, %pg, %b) { +; CHECK-LABEL: neg_i16: +; CHECK: neg z0.h, p0/m, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.neg.nxv8i16( %a, + %pg, + %b) + ret %out +} + +define @neg_i32( %a, %pg, %b) { +; CHECK-LABEL: neg_i32: +; CHECK: neg z0.s, p0/m, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.neg.nxv4i32( %a, + %pg, + %b) + ret %out +} + +define @neg_i64( %a, %pg, %b) { +; CHECK-LABEL: neg_i64: +; CHECK: neg z0.d, p0/m, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.neg.nxv2i64( %a, + %pg, + %b) + ret %out +} + +declare @llvm.aarch64.sve.abs.nxv16i8(, , ) +declare @llvm.aarch64.sve.abs.nxv8i16(, , ) +declare @llvm.aarch64.sve.abs.nxv4i32(, , ) +declare @llvm.aarch64.sve.abs.nxv2i64(, , ) + +declare @llvm.aarch64.sve.neg.nxv16i8(, , ) +declare @llvm.aarch64.sve.neg.nxv8i16(, , ) +declare @llvm.aarch64.sve.neg.nxv4i32(, , ) +declare @llvm.aarch64.sve.neg.nxv2i64(, , ) -- 2.7.4