From 5504f0cdbca4be1aba6365a27175cac5574edd28 Mon Sep 17 00:00:00 2001 From: nobody <> Date: Wed, 9 Mar 2005 09:39:32 +0000 Subject: [PATCH] This commit was manufactured by cvs2svn to create branch 'binutils- 2_16-branch'. Cherrypick from master 2005-03-09 09:39:31 UTC Richard Sandiford ' * config/tc-mips.c (MAX_VR4130_NOPS, MAX_DELAY_NOPS): New macros.': gas/testsuite/gas/mips/branch-misc-3.d gas/testsuite/gas/mips/branch-misc-3.s gas/testsuite/gas/mips/vr4130.d gas/testsuite/gas/mips/vr4130.s --- gas/testsuite/gas/mips/branch-misc-3.d | 59 +++ gas/testsuite/gas/mips/branch-misc-3.s | 44 ++ gas/testsuite/gas/mips/vr4130.d | 705 +++++++++++++++++++++++++++++++++ gas/testsuite/gas/mips/vr4130.s | 305 ++++++++++++++ 4 files changed, 1113 insertions(+) create mode 100644 gas/testsuite/gas/mips/branch-misc-3.d create mode 100644 gas/testsuite/gas/mips/branch-misc-3.s create mode 100644 gas/testsuite/gas/mips/vr4130.d create mode 100644 gas/testsuite/gas/mips/vr4130.s diff --git a/gas/testsuite/gas/mips/branch-misc-3.d b/gas/testsuite/gas/mips/branch-misc-3.d new file mode 100644 index 0000000..754ed20 --- /dev/null +++ b/gas/testsuite/gas/mips/branch-misc-3.d @@ -0,0 +1,59 @@ +#as: -march=mips1 -32 +#objdump: -dz +#name: MIPS coprocessor branches + +.*file format .* + +Disassembly .*: + +0+00 <.*>: +.* ctc1 a0,\$31 +.* b .* +.* nop +# +.* ctc1 a0,\$31 +.* nop +.* nop +.* bc1t .* +.* nop +# +.* c\.eq\.s \$f0,\$f2 +.* b .* +.* nop +# +.* c\.eq\.s \$f0,\$f2 +.* nop +.* bc1t .* +.* nop +# +.* ctc1 a0,\$31 +.* addiu a1,a1,1 +.* nop +.* bc1t .* +.* nop +# +.* ctc1 a0,\$31 +.* addiu a1,a1,1 +.* addiu a2,a2,1 +.* bc1t .* +.* nop +# +.* c\.eq\.s \$f0,\$f2 +.* addiu a1,a1,1 +.* bc1t .* +.* nop +# +.* ctc1 a0,\$31 +.* addiu a1,a1,1 +.* addiu a2,a2,1 +.* bc1t .* +.* addiu a3,a3,1 +# +.* c\.eq\.s \$f0,\$f2 +.* addiu a1,a1,1 +.* bc1t .* +.* addiu a2,a2,1 +# +.* bc1t .* +.* addiu a3,a3,1 +#pass diff --git a/gas/testsuite/gas/mips/branch-misc-3.s b/gas/testsuite/gas/mips/branch-misc-3.s new file mode 100644 index 0000000..7a025a7 --- /dev/null +++ b/gas/testsuite/gas/mips/branch-misc-3.s @@ -0,0 +1,44 @@ + # ctc1s and compares shouldn't appear in a branch delay slot. + ctc1 $4,$31 + b 1f +1: + ctc1 $4,$31 + bc1t 1f +1: + c.eq.s $f0,$f2 + b 1f +1: + c.eq.s $f0,$f2 + bc1t 1f +1: + + # The next three branches should have nop-filled slots. + ctc1 $4,$31 + addiu $5,$5,1 + bc1t 1f +1: + ctc1 $4,$31 + addiu $5,$5,1 + addiu $6,$6,1 + bc1t 1f +1: + c.eq.s $f0,$f2 + addiu $5,$5,1 + bc1t 1f +1: + + # ...but a swap is possible in these three. + ctc1 $4,$31 + addiu $5,$5,1 + addiu $6,$6,1 + addiu $7,$7,1 + bc1t 1f +1: + c.eq.s $f0,$f2 + addiu $5,$5,1 + addiu $6,$6,1 + bc1t 1f +1: + addiu $7,$7,1 + bc1t 1f +1: diff --git a/gas/testsuite/gas/mips/vr4130.d b/gas/testsuite/gas/mips/vr4130.d new file mode 100644 index 0000000..4933d4d --- /dev/null +++ b/gas/testsuite/gas/mips/vr4130.d @@ -0,0 +1,705 @@ +#as: -mfix-vr4130 -march=vr4130 -mabi=o64 +#objdump: -dz +#name: MIPS VR4130 workarounds + +.*file format.* + +Disassembly.* + +.* : +# +# PART A +# +.* mfhi .* +.* mult .* +# +.* mflo .* +.* mult .* +# +# PART B +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* nop +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +# PART C +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +# PART D +# +.* mfhi .* +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* nop +.* mult .* +# +# PART E +# +.* mfhi .* +.* nop +.* nop +.* bnez .* +.* nop +# +.* mfhi .* +.* addiu .* +.* nop +.* bnez .* +.* nop +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* bnez .* +.* nop +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* bnez .* +.* nop +# +# PART F +# +.* mfhi .* +.* addiu .* +.* nop +.* bnez .* +.* nop +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* bnez .* +.* nop +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* bnez .* +.* addiu .* +# +# PART G +# +.* mfhi .* +.* addiu .* +.* nop +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +# PART H +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* addiu .* +.* mult .* +# +.* mfhi .* +.* addiu .* +.* nop +.* nop +.* addiu .* +.* mult .* +# +.* mfhi .* +.* nop +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +# PART I +# +.* mflo .* +.* nop +.* nop +.* nop +.* nop +.* mult .* +# +.* mflo .* +.* nop +.* nop +.* nop +.* nop +.* multu .* +# +.* mflo .* +.* nop +.* nop +.* nop +.* nop +.* dmult .* +# +.* mflo .* +.* nop +.* nop +.* nop +.* nop +.* dmultu .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* div .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* divu .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* ddiv .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* ddivu .* +# +# PART J +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* macc .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* macchi .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* macchis .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* macchiu .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* macchius .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* maccs .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* maccu .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* maccus .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* dmacc .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* dmacchi .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* dmacchis .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* dmacchiu .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* dmacchius .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* dmaccs .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* dmaccu .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* dmaccus .* +# +# PART K +# +.* mflo .* +.* nop +.* nop +.* mtlo .* +# +.* mflo .* +.* mthi .* +# +.* mfhi .* +.* mtlo .* +# +.* mfhi .* +.* nop +.* nop +.* mthi .* + +.* : +# +# PART A +# +.* mfhi .* +.* mult .* +# +.* mflo .* +.* mult .* +# +# PART B +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* nop +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +# PART C +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +# PART D +# +.* mfhi .* +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* nop +.* mult .* +# +# PART E +# +.* mfhi .* +.* nop +.* nop +.* nop +.* bnez .* +# +.* mfhi .* +.* addiu .* +.* nop +.* nop +.* bnez .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* nop +.* bnez .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* bnez .* +# +# PART F +# +.* mfhi .* +.* addiu .* +.* nop +.* nop +.* bnez .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* nop +.* bnez .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* bnez .* +# +# PART G +# +.* mfhi .* +.* addiu .* +.* nop +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* nop +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +# PART H +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* mult .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* addiu .* +.* mult .* +# +.* mfhi .* +.* addiu .* +.* nop +.* nop +.* addiu .* +.* mult .* +# +.* mfhi .* +.* nop +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +.* mfhi .* +.* addiu .* +.* addiu .* +.* addiu .* +.* addiu .* +.* mult .* +# +# PART I +# +.* mflo .* +.* nop +.* nop +.* nop +.* nop +.* mult .* +# +.* mflo .* +.* nop +.* nop +.* nop +.* nop +.* multu .* +# +.* mflo .* +.* nop +.* nop +.* nop +.* nop +.* dmult .* +# +.* mflo .* +.* nop +.* nop +.* nop +.* nop +.* dmultu .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* div .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* divu .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* ddiv .* +# +.* mfhi .* +.* nop +.* nop +.* nop +.* nop +.* ddivu .* +#pass diff --git a/gas/testsuite/gas/mips/vr4130.s b/gas/testsuite/gas/mips/vr4130.s new file mode 100644 index 0000000..1f1dfcf --- /dev/null +++ b/gas/testsuite/gas/mips/vr4130.s @@ -0,0 +1,305 @@ + .macro check2 insn + mflo $2 + \insn $3,$3 + .endm + + .macro check3 insn + mfhi $2 + \insn $0,$3,$3 + .endm + + .macro main func + + .ent \func + .type \func,@function +\func: + + # PART A + # + # Check that mfhis and mflos in .set noreorder blocks are not + # considered. + + .set noreorder + mfhi $2 + .set reorder + mult $3,$3 + + .set noreorder + mflo $2 + .set reorder + mult $3,$3 + + # PART B + # + # Check for simple instances. + + mfhi $2 + mult $3,$3 # 4 nops + + mfhi $2 + addiu $3,1 + mult $4,$4 # 3 nops + + mfhi $2 + addiu $3,1 + addiu $4,1 + mult $5,$5 # 2 nops + + mfhi $2 + addiu $3,1 + addiu $4,1 + addiu $5,1 + mult $6,$6 # 1 nop + + mfhi $2 + addiu $3,1 + addiu $4,1 + addiu $5,1 + addiu $6,1 + mult $7,$7 # 0 nops + + # PART C + # + # Check that no nops are inserted after the result has been read. + + mfhi $2 + addiu $2,1 + addiu $3,1 + addiu $4,1 + mult $5,$5 + + mfhi $2 + addiu $3,1 + addiu $2,1 + addiu $4,1 + mult $5,$5 + + mfhi $2 + addiu $3,1 + addiu $4,1 + addiu $2,1 + mult $5,$5 + + mfhi $2 + addiu $3,1 + addiu $4,1 + addiu $5,1 + mult $2,$2 + + # PART D + # + # Check that we still insert the usual interlocking nops in cases + # where the VR4130 errata doesn't apply. + + mfhi $2 + mult $2,$2 # 2 nops + + mfhi $2 + addiu $2,1 + mult $3,$3 # 1 nop + + mfhi $2 + addiu $3,1 + mult $2,$2 # 1 nop + + # PART E + # + # Check for branches whose targets might be affected. + + mfhi $2 + bnez $3,1f # 2 nops for normal mode, 3 for mips16 + + mfhi $2 + addiu $3,1 + bnez $3,1f # 1 nop for normal mode, 2 for mips16 + + mfhi $2 + addiu $3,1 + addiu $3,1 + bnez $3,1f # 0 nops for normal mode, 1 for mips16 + + mfhi $2 + addiu $3,1 + addiu $3,1 + addiu $3,1 + bnez $3,1f # 0 nops + + # PART F + # + # As above, but with no dependencies between the branch and + # the previous instruction. The final branch can use the + # preceding addiu as its delay slot. + + mfhi $2 + addiu $3,1 + bnez $4,1f # 1 nop for normal mode, 2 for mips16 + + mfhi $2 + addiu $3,1 + addiu $4,1 + bnez $5,1f # 0 nops for normal mode, 1 for mips16 + + mfhi $2 + addiu $3,1 + addiu $4,1 + addiu $5,1 + bnez $6,1f # 0 nops, fill delay slot in normal mode +1: + + # PART G + # + # Like part B, but check that intervening .set noreorders don't + # affect the number of nops. + + mfhi $2 + .set noreorder + addiu $3,1 + .set reorder + mult $4,$4 # 3 nops + + mfhi $2 + .set noreorder + addiu $3,1 + .set reorder + addiu $4,1 + mult $5,$5 # 2 nops + + mfhi $2 + addiu $3,1 + .set noreorder + addiu $4,1 + .set reorder + mult $5,$5 # 2 nops + + mfhi $2 + .set noreorder + addiu $3,1 + addiu $4,1 + .set reorder + mult $5,$5 # 2 nops + + mfhi $2 + addiu $3,1 + .set noreorder + addiu $4,1 + .set reorder + addiu $5,1 + mult $6,$6 # 1 nop + + mfhi $2 + .set noreorder + addiu $3,1 + addiu $4,1 + addiu $5,1 + .set reorder + mult $6,$6 # 1 nop + + mfhi $2 + .set noreorder + addiu $3,1 + addiu $4,1 + addiu $5,1 + addiu $6,1 + .set reorder + mult $7,$7 # 0 nops + + # PART H + # + # Like part B, but the mult occurs in a .set noreorder block. + + mfhi $2 + .set noreorder + mult $3,$3 # 4 nops + .set reorder + + mfhi $2 + .set noreorder + addiu $3,1 + mult $4,$4 # 3 nops + .set reorder + + mfhi $2 + addiu $3,1 + .set noreorder + addiu $4,1 + mult $5,$5 # 2 nops + .set reorder + + mfhi $2 + .set noreorder + addiu $3,1 + addiu $4,1 + addiu $5,1 + mult $6,$6 # 1 nop + .set reorder + + mfhi $2 + .set noreorder + addiu $3,1 + addiu $4,1 + addiu $5,1 + addiu $6,1 + mult $7,$7 # 0 nops + .set reorder + + # PART I + # + # Check every affected multiplication and division instruction. + + check2 mult + check2 multu + check2 dmult + check2 dmultu + + check3 div + check3 divu + check3 ddiv + check3 ddivu + + .end \func + .endm + + .set nomips16 + main foo + + # PART J + # + # Check every affected multiply-accumulate instruction. + + check3 macc + check3 macchi + check3 macchis + check3 macchiu + check3 macchius + check3 maccs + check3 maccu + check3 maccus + + check3 dmacc + check3 dmacchi + check3 dmacchis + check3 dmacchiu + check3 dmacchius + check3 dmaccs + check3 dmaccu + check3 dmaccus + + # PART K + # + # Check that mtlo and mthi are exempt from the VR4130 errata, + # although the usual interlocking delay applies. + + mflo $2 + mtlo $3 + + mflo $2 + mthi $3 + + mfhi $2 + mtlo $3 + + mfhi $2 + mthi $3 + + .set mips16 + main bar -- 2.7.4