From 5500c0ff898bd5ca2ddfe0d78dc965f4a8366487 Mon Sep 17 00:00:00 2001 From: Mihai Popa Date: Thu, 22 Aug 2013 13:16:07 +0000 Subject: [PATCH] Fix ARM vcvt encoding when the number of fractional bits is zero. The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009 --- llvm/lib/Target/ARM/ARMInstrNEON.td | 19 +++++++++++++++++++ llvm/test/MC/ARM/neon-convert-encoding.s | 16 ++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index af4f4d1..59dea48 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -5461,6 +5461,25 @@ def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32", v4f32, v4i32, int_arm_neon_vcvtfxu2fp>; } +def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0", + (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>; +def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0", + (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>; +def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0", + (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>; +def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0", + (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>; + +def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0", + (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>; +def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0", + (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>; +def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0", + (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>; +def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0", + (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>; + + // VCVT : Vector Convert Between Half-Precision and Single-Precision. def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0, IIC_VUNAQ, "vcvt", "f16.f32", diff --git a/llvm/test/MC/ARM/neon-convert-encoding.s b/llvm/test/MC/ARM/neon-convert-encoding.s index 1733c52..20c7895 100644 --- a/llvm/test/MC/ARM/neon-convert-encoding.s +++ b/llvm/test/MC/ARM/neon-convert-encoding.s @@ -18,20 +18,36 @@ vcvt.f32.u32 q8, q8 @ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2] vcvt.s32.f32 d16, d16, #1 +@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3] + vcvt.s32.f32 d16, d16, #0 @ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3] vcvt.u32.f32 d16, d16, #1 +@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3] + vcvt.u32.f32 d16, d16, #0 @ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2] vcvt.f32.s32 d16, d16, #1 +@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3] + vcvt.f32.s32 d16, d16, #0 @ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3] vcvt.f32.u32 d16, d16, #1 +@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3] + vcvt.f32.u32 d16, d16, #0 @ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2] vcvt.s32.f32 q8, q8, #1 +@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3] + vcvt.s32.f32 q8, q8, #0 @ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3] vcvt.u32.f32 q8, q8, #1 +@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3] + vcvt.u32.f32 q8, q8, #0 @ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf2] vcvt.f32.s32 q8, q8, #1 +@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3] + vcvt.f32.s32 q8, q8, #0 @ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3] vcvt.f32.u32 q8, q8, #1 +@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3] + vcvt.f32.u32 q8, q8, #0 @ CHECK: vcvt.f32.f16 q8, d16 @ encoding: [0x20,0x07,0xf6,0xf3] vcvt.f32.f16 q8, d16 @ CHECK: vcvt.f16.f32 d16, q8 @ encoding: [0x20,0x06,0xf6,0xf3] -- 2.7.4