From 54829ec5d037e59f07962884bcc6c21441e60f01 Mon Sep 17 00:00:00 2001
From: Diana Picus <diana.picus@linaro.org>
Date: Fri, 1 Mar 2019 10:12:28 +0000
Subject: [PATCH] [ARM GlobalISel] Support G_CTLZ for Thumb2

Same as ARM mode but with different opcode.

llvm-svn: 355191
---
 llvm/lib/Target/ARM/ARMLegalizerInfo.cpp           |  7 -----
 .../ARM/GlobalISel/arm-legalize-bitcounts.mir      |  1 +
 llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir    | 33 ++++++++++++++++++++++
 3 files changed, 34 insertions(+), 7 deletions(-)
 create mode 100644 llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir

diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index 26c7a98..82817d3 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -206,13 +206,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
 
   getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
 
-  if (ST.isThumb()) {
-    // FIXME: merge with the code for non-Thumb.
-    computeTables();
-    verify(*ST.getInstrInfo());
-    return;
-  }
-
   if (ST.hasV5TOps()) {
     getActionDefinitionsBuilder(G_CTLZ)
         .legalFor({s32, s32})
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
index 962dd84..8e83bc4 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
@@ -1,4 +1,5 @@
 # RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=+v5t -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,CLZ
+# RUN: llc -O0 -mtriple thumb-linux-gnueabi -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,CLZ
 # RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=-v5t -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,LIBCALLS
 --- |
   define void @test_ctlz_s32() { ret void }
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir
new file mode 100644
index 0000000..d3cf3b3
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir
@@ -0,0 +1,33 @@
+# RUN: llc -O0 -mtriple arm-- -mattr=+v6 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,ARM
+# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,THUMB
+--- |
+  define void @test_clz() { ret void }
+...
+---
+name:            test_clz
+# CHECK-LABEL: name: test_clz
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %0(s32) = COPY $r0
+    ; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0
+    ; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
+
+    %1(s32) = G_CTLZ %0(s32)
+    ; ARM: [[VREGR:%[0-9]+]]:gpr = CLZ [[VREGX]], 14, $noreg
+    ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2CLZ [[VREGX]], 14, $noreg
+
+    $r0 = COPY %1(s32)
+    ; CHECK: $r0 = COPY [[VREGR]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
-- 
2.7.4