From 53cf1897ccea18a5919e109cde61b29d16dd8fb9 Mon Sep 17 00:00:00 2001 From: Artyom Skrobov Date: Sun, 23 Apr 2017 06:58:08 +0000 Subject: [PATCH] [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs Summary: D30400 has enabled tADC and tSBC instructions to be unglued, thereby allowing CPSR to remain live between Thumb1 scheduling units. Most Thumb1 instructions have an OptionalDef for CPSR; but the scheduler ignored the OptionalDefs, and could unwittingly insert a flag-setting instruction in between an ADDS and the corresponding ADC. Reviewers: javed.absar, atrick, MatzeB, t.p.northover, jmolloy, rengolin Reviewed By: javed.absar Subscribers: rogfer01, efriedma, aemerson, rengolin, llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D31081 llvm-svn: 301106 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 12 ++++++++++++ llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll | 18 ++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index e923e30..69b76fb 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1320,6 +1320,18 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl &LRegs) { RegAdded, LRegs); const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); + if (MCID.hasOptionalDef()) { + // Most ARM instructions have an OptionalDef for CPSR, to model the S-bit. + // This operand can be either a def of CPSR, if the S bit is set; or a use + // of %noreg. When the OptionalDef is set to a valid register, we need to + // handle it in the same way as an ImplicitDef. + for (unsigned i = 0; i < MCID.getNumDefs(); ++i) + if (MCID.OpInfo[i].isOptionalDef()) { + const SDValue &OptionalDef = Node->getOperand(i - Node->getNumValues()); + unsigned Reg = cast(OptionalDef)->getReg(); + CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI); + } + } if (!MCID.ImplicitDefs) continue; for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) diff --git a/llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll b/llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll new file mode 100644 index 0000000..bd091cf --- /dev/null +++ b/llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | FileCheck %s +; RUN: llc -mtriple=thumbv6-eabi %s -verify-machineinstrs -o - | FileCheck %s + +define i1 @test(i64 %arg) { +entry: + %ispos = icmp sgt i64 %arg, -1 + %neg = sub i64 0, %arg + %sel = select i1 %ispos, i64 %arg, i64 %neg + %cmp2 = icmp eq i64 %sel, %arg + ret i1 %cmp2 +} + +; The scheduler used to ignore OptionalDefs, and could unwittingly insert +; a flag-setting instruction in between an ADDS and the corresponding ADC. + +; CHECK: adds +; CHECK-NOT: eors +; CHECK: adcs -- 2.7.4