From 538b85810ce51671da8dce120d528069e6fc8049 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Thu, 15 Jan 2015 19:28:32 +0000 Subject: [PATCH] [Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions. llvm-svn: 226194 --- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 6 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 82 ++++++++++++------------ llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 4 +- llvm/test/MC/Disassembler/Hexagon/xtype_perm.txt | 4 ++ 4 files changed, 49 insertions(+), 47 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index a46a335..e77c9f2 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -355,11 +355,11 @@ static unsigned doesIntrinsicContainPredicate(unsigned ID) case Intrinsic::hexagon_C2_muxii: return Hexagon::C2_muxii; case Intrinsic::hexagon_C2_vmux: - return Hexagon::VMUX_prr64; + return Hexagon::C2_vmux; case Intrinsic::hexagon_S2_valignrb: - return Hexagon::VALIGN_rrp; + return Hexagon::S2_valignrb; case Intrinsic::hexagon_S2_vsplicerb: - return Hexagon::VSPLICE_rrp; + return Hexagon::S2_vsplicerb; } } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index a4cffa1..a41380e 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -30,6 +30,20 @@ def F64 : PatLeaf<(f64 DoubleRegs:$R)>; def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>; +// SDNode for converting immediate C to C-1. +def DEC_CONST_SIGNED : SDNodeXFormgetSExtValue(); + return XformSToSM1Imm(imm); +}]>; + +// SDNode for converting immediate C to C-1. +def DEC_CONST_UNSIGNED : SDNodeXFormgetZExtValue(); + return XformUToUM1Imm(imm); +}]>; + //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// @@ -799,14 +813,6 @@ def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>; def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>; def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>; -// Mux. -def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, - DoubleRegs:$src2, - DoubleRegs:$src3), - "$dst = vmux($src1, $src2, $src3)", - []>; - - //===----------------------------------------------------------------------===// // ALU32/PERM - //===----------------------------------------------------------------------===// @@ -816,28 +822,6 @@ def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, // ALU32/PRED + //===----------------------------------------------------------------------===// -// SDNode for converting immediate C to C-1. -def DEC_CONST_SIGNED : SDNodeXFormgetSExtValue(); - return XformSToSM1Imm(imm); -}]>; - -// SDNode for converting immediate C to C-1. -def DEC_CONST_UNSIGNED : SDNodeXFormgetZExtValue(); - return XformUToUM1Imm(imm); -}]>; - -def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1), - "$dst = cl0($src1)", - [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>; - -def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1), - "$dst = ct0($src1)", - [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>; - //===----------------------------------------------------------------------===// // ALU32/PRED - //===----------------------------------------------------------------------===// @@ -1253,18 +1237,6 @@ def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt), let Inst{4-0} = Rd; } -def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, - DoubleRegs:$src2, - PredRegs:$src3), - "$dst = valignb($src1, $src2, $src3)", - []>; - -def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, - DoubleRegs:$src2, - PredRegs:$src3), - "$dst = vspliceb($src1, $src2, $src3)", - []>; - // User control register transfer. //===----------------------------------------------------------------------===// // CR - @@ -4941,6 +4913,32 @@ class T_S3op_64 MajOp, bits<3> MinOp, bit SwapOps, let isCodeGenOnly = 0 in def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>; +let hasSideEffects = 0 in +class T_S3op_2 MajOp, bit SwapOps> + : SInst < (outs DoubleRegs:$Rdd), + (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu), + "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)", + [], "", S_3op_tc_1_SLOT23 > { + bits<5> Rdd; + bits<5> Rss; + bits<5> Rtt; + bits<2> Pu; + + let IClass = 0b1100; + + let Inst{27-24} = 0b0010; + let Inst{23-21} = MajOp; + let Inst{20-16} = !if (SwapOps, Rtt, Rss); + let Inst{12-8} = !if (SwapOps, Rss, Rtt); + let Inst{6-5} = Pu; + let Inst{4-0} = Rdd; + } + +let isCodeGenOnly = 0 in { +def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>; +def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>; +} + //===----------------------------------------------------------------------===// // Template class used by vector shift, vector rotate, vector neg, // 32-bit shift, 64-bit shifts, etc. diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index 9efecd2..ad2393c 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -3725,11 +3725,11 @@ def STriw_offset_ext_V4 : STInst<(outs), Requires<[HasV4T]>; def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))), - (i64 (A4_combineir (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>, + (i64 (A4_combineir (i32 0), (i32 (S2_cl0p DoubleRegs:$src1))))>, Requires<[HasV4T]>; def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))), - (i64 (A4_combineir (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>, + (i64 (A4_combineir (i32 0), (i32 (S2_ct0p DoubleRegs:$src1))))>, Requires<[HasV4T]>; diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_perm.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_perm.txt index 1de3d11..7267e71 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_perm.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_perm.txt @@ -12,3 +12,7 @@ # CHECK: r17 = satb(r21) 0xf1 0xc0 0x95 0x8c # CHECK: r17 = swiz(r21) +0x70 0xd4 0x1e 0xc2 +# CHECK: r17:16 = valignb(r21:20, r31:30, p3) +0x70 0xde 0x94 0xc2 +# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3) -- 2.7.4