From 536f34d9ab88e153aa11329e789afe6975fbe9a9 Mon Sep 17 00:00:00 2001 From: Adeel Mujahid <3840695+am11@users.noreply.github.com> Date: Fri, 26 Aug 2022 17:07:03 +0300 Subject: [PATCH] Simplify platform macro definitions in PAL (#73530) * Simplify platform macro definitions in PAL * Address CR feedback * Rename unwinder.cpp to baseunwinder.cpp * Sync arm64 DAC_CS_NATIVE_DATA_SIZE --- src/coreclr/debug/daccess/riscv64/primitives.cpp | 8 +++ src/coreclr/debug/ee/CMakeLists.txt | 18 ++----- .../debug/ee/amd64/{amd64walker.cpp => walker.cpp} | 4 +- .../debug/ee/arm/{armwalker.cpp => walker.cpp} | 4 +- .../debug/ee/arm64/{arm64walker.cpp => walker.cpp} | 4 +- .../debug/ee/i386/{x86walker.cpp => walker.cpp} | 4 +- .../{loongarch64walker.cpp => walker.cpp} | 3 -- .../ee/ppc64le/walker.cpp} | 7 --- src/coreclr/debug/ee/riscv64/dbghelpers.S | 7 +++ src/coreclr/debug/ee/riscv64/primitives.cpp | 10 ++++ src/coreclr/debug/ee/riscv64/walker.cpp | 19 +++++++ src/coreclr/debug/ee/s390x/walker.cpp | 4 ++ src/coreclr/debug/shared/riscv64/primitives.cpp | 15 ++++++ src/coreclr/gc/env/gcenv.interlocked.h | 2 +- src/coreclr/gc/env/gcenv.interlocked.inl | 37 ++++++------- src/coreclr/inc/crosscomp.h | 2 +- src/coreclr/jit/hashbv.h | 2 +- src/coreclr/nativeaot/Runtime/arm64/AsmMacros.h | 2 +- src/coreclr/nativeaot/Runtime/arm64/Interlocked.S | 4 +- .../nativeaot/Runtime/arm64/Interlocked.asm | 4 +- .../nativeaot/Runtime/arm64/WriteBarriers.S | 4 +- .../nativeaot/Runtime/arm64/WriteBarriers.asm | 4 +- .../nativeaot/Runtime/unix/unixasmmacrosarm64.inc | 2 +- src/coreclr/pal/inc/pal.h | 62 ++++------------------ src/coreclr/pal/src/safecrt/cruntime.h | 14 ++--- src/coreclr/unwinder/CMakeLists.txt | 4 +- .../amd64/{unwinder_amd64.cpp => unwinder.cpp} | 2 +- .../amd64/{unwinder_amd64.h => unwinder.h} | 2 +- .../arm/{unwinder_arm.cpp => unwinder.cpp} | 2 +- .../unwinder/arm/{unwinder_arm.h => unwinder.h} | 2 +- .../arm64/{unwinder_arm64.cpp => unwinder.cpp} | 2 +- .../arm64/{unwinder_arm64.h => unwinder.h} | 2 +- .../unwinder/{unwinder.cpp => baseunwinder.cpp} | 2 +- .../unwinder/{unwinder.h => baseunwinder.h} | 0 .../i386/{unwinder_i386.cpp => unwinder.cpp} | 2 +- .../unwinder/i386/{unwinder_i386.h => unwinder.h} | 2 +- .../{unwinder_loongarch64.cpp => unwinder.cpp} | 2 +- .../{unwinder_loongarch64.h => unwinder.h} | 2 +- src/coreclr/unwinder/ppc64le/unwinder.cpp | 4 ++ .../unwinder_ppc64le.cpp => riscv64/unwinder.cpp} | 3 +- src/coreclr/unwinder/riscv64/unwinder.h | 13 +++++ src/coreclr/unwinder/s390x/unwinder.cpp | 4 ++ src/coreclr/vm/CMakeLists.txt | 4 +- .../{armsinglestepper.cpp => singlestepper.cpp} | 0 .../{arm64singlestepper.cpp => singlestepper.cpp} | 0 src/coreclr/vm/riscv64/asmconstants.h | 4 ++ src/coreclr/vm/riscv64/asmhelpers.S | 7 +++ .../vm/riscv64/calldescrworkerloongarch64.S | 7 +++ src/coreclr/vm/riscv64/cgencpu.h | 4 ++ src/coreclr/vm/riscv64/crthelpers.S | 6 +++ src/coreclr/vm/riscv64/excepcpu.h | 7 +++ src/coreclr/vm/riscv64/gmscpu.h | 4 ++ src/coreclr/vm/riscv64/pinvokestubs.S | 7 +++ src/coreclr/vm/riscv64/profiler.cpp | 6 +++ src/coreclr/vm/riscv64/stubs.cpp | 4 ++ src/coreclr/vm/riscv64/thunktemplates.S | 7 +++ src/coreclr/vm/riscv64/unixstubs.cpp | 12 +++++ src/coreclr/vm/riscv64/virtualcallstubcpu.hpp | 4 ++ 58 files changed, 234 insertions(+), 145 deletions(-) create mode 100644 src/coreclr/debug/daccess/riscv64/primitives.cpp rename src/coreclr/debug/ee/amd64/{amd64walker.cpp => walker.cpp} (99%) rename src/coreclr/debug/ee/arm/{armwalker.cpp => walker.cpp} (99%) rename src/coreclr/debug/ee/arm64/{arm64walker.cpp => walker.cpp} (99%) rename src/coreclr/debug/ee/i386/{x86walker.cpp => walker.cpp} (99%) rename src/coreclr/debug/ee/loongarch64/{loongarch64walker.cpp => walker.cpp} (99%) rename src/coreclr/{unwinder/s390x/unwinder_s390x.cpp => debug/ee/ppc64le/walker.cpp} (70%) create mode 100644 src/coreclr/debug/ee/riscv64/dbghelpers.S create mode 100644 src/coreclr/debug/ee/riscv64/primitives.cpp create mode 100644 src/coreclr/debug/ee/riscv64/walker.cpp create mode 100644 src/coreclr/debug/ee/s390x/walker.cpp create mode 100644 src/coreclr/debug/shared/riscv64/primitives.cpp rename src/coreclr/unwinder/amd64/{unwinder_amd64.cpp => unwinder.cpp} (99%) rename src/coreclr/unwinder/amd64/{unwinder_amd64.h => unwinder.h} (98%) rename src/coreclr/unwinder/arm/{unwinder_arm.cpp => unwinder.cpp} (99%) rename src/coreclr/unwinder/arm/{unwinder_arm.h => unwinder.h} (98%) rename src/coreclr/unwinder/arm64/{unwinder_arm64.cpp => unwinder.cpp} (99%) rename src/coreclr/unwinder/arm64/{unwinder_arm64.h => unwinder.h} (98%) rename src/coreclr/unwinder/{unwinder.cpp => baseunwinder.cpp} (98%) rename src/coreclr/unwinder/{unwinder.h => baseunwinder.h} (100%) rename src/coreclr/unwinder/i386/{unwinder_i386.cpp => unwinder.cpp} (99%) rename src/coreclr/unwinder/i386/{unwinder_i386.h => unwinder.h} (97%) rename src/coreclr/unwinder/loongarch64/{unwinder_loongarch64.cpp => unwinder.cpp} (99%) rename src/coreclr/unwinder/loongarch64/{unwinder_loongarch64.h => unwinder.h} (98%) create mode 100644 src/coreclr/unwinder/ppc64le/unwinder.cpp rename src/coreclr/unwinder/{ppc64le/unwinder_ppc64le.cpp => riscv64/unwinder.cpp} (75%) create mode 100644 src/coreclr/unwinder/riscv64/unwinder.h create mode 100644 src/coreclr/unwinder/s390x/unwinder.cpp rename src/coreclr/vm/arm/{armsinglestepper.cpp => singlestepper.cpp} (100%) rename src/coreclr/vm/arm64/{arm64singlestepper.cpp => singlestepper.cpp} (100%) create mode 100644 src/coreclr/vm/riscv64/asmconstants.h create mode 100644 src/coreclr/vm/riscv64/asmhelpers.S create mode 100644 src/coreclr/vm/riscv64/calldescrworkerloongarch64.S create mode 100644 src/coreclr/vm/riscv64/cgencpu.h create mode 100644 src/coreclr/vm/riscv64/crthelpers.S create mode 100644 src/coreclr/vm/riscv64/excepcpu.h create mode 100644 src/coreclr/vm/riscv64/gmscpu.h create mode 100644 src/coreclr/vm/riscv64/pinvokestubs.S create mode 100644 src/coreclr/vm/riscv64/profiler.cpp create mode 100644 src/coreclr/vm/riscv64/stubs.cpp create mode 100644 src/coreclr/vm/riscv64/thunktemplates.S create mode 100644 src/coreclr/vm/riscv64/unixstubs.cpp create mode 100644 src/coreclr/vm/riscv64/virtualcallstubcpu.hpp diff --git a/src/coreclr/debug/daccess/riscv64/primitives.cpp b/src/coreclr/debug/daccess/riscv64/primitives.cpp new file mode 100644 index 0000000..74dda92 --- /dev/null +++ b/src/coreclr/debug/daccess/riscv64/primitives.cpp @@ -0,0 +1,8 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +// + +#include "stdafx.h" + +#include "../../shared/riscv64/primitives.cpp" diff --git a/src/coreclr/debug/ee/CMakeLists.txt b/src/coreclr/debug/ee/CMakeLists.txt index 5e562df..106f4be 100644 --- a/src/coreclr/debug/ee/CMakeLists.txt +++ b/src/coreclr/debug/ee/CMakeLists.txt @@ -47,22 +47,12 @@ set(CORDBEE_HEADERS_DAC ${CORDBEE_HEADERS_DAC_AND_WKS} ) +list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/walker.cpp) + if(CLR_CMAKE_TARGET_ARCH_AMD64) - list(APPEND CORDBEE_SOURCES_WKS - ${ARCH_SOURCES_DIR}/debuggerregdisplayhelper.cpp - ${ARCH_SOURCES_DIR}/amd64walker.cpp - ) + list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/debuggerregdisplayhelper.cpp) elseif(CLR_CMAKE_TARGET_ARCH_I386) - list(APPEND CORDBEE_SOURCES_WKS - ${ARCH_SOURCES_DIR}/debuggerregdisplayhelper.cpp - ${ARCH_SOURCES_DIR}/x86walker.cpp - ) -elseif(CLR_CMAKE_TARGET_ARCH_ARM) - list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/armwalker.cpp) -elseif(CLR_CMAKE_TARGET_ARCH_ARM64) - list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/arm64walker.cpp) -elseif(CLR_CMAKE_TARGET_ARCH_LOONGARCH64) - list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/loongarch64walker.cpp) + list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/debuggerregdisplayhelper.cpp) endif() convert_to_absolute_path(CORDBEE_SOURCES_DAC ${CORDBEE_SOURCES_DAC}) diff --git a/src/coreclr/debug/ee/amd64/amd64walker.cpp b/src/coreclr/debug/ee/amd64/walker.cpp similarity index 99% rename from src/coreclr/debug/ee/amd64/amd64walker.cpp rename to src/coreclr/debug/ee/amd64/walker.cpp index 06cbc48..0108f1a 100644 --- a/src/coreclr/debug/ee/amd64/amd64walker.cpp +++ b/src/coreclr/debug/ee/amd64/walker.cpp @@ -1,9 +1,7 @@ // Licensed to the .NET Foundation under one or more agreements. // The .NET Foundation licenses this file to you under the MIT license. -//***************************************************************************** -// File: Amd64walker.cpp -// +//***************************************************************************** // // AMD64 instruction decoding/stepping logic // diff --git a/src/coreclr/debug/ee/arm/armwalker.cpp b/src/coreclr/debug/ee/arm/walker.cpp similarity index 99% rename from src/coreclr/debug/ee/arm/armwalker.cpp rename to src/coreclr/debug/ee/arm/walker.cpp index 6963acd..d71a8ae 100644 --- a/src/coreclr/debug/ee/arm/armwalker.cpp +++ b/src/coreclr/debug/ee/arm/walker.cpp @@ -1,9 +1,7 @@ // Licensed to the .NET Foundation under one or more agreements. // The .NET Foundation licenses this file to you under the MIT license. -//***************************************************************************** -// File: armwalker.cpp -// +//***************************************************************************** // // ARM instruction decoding/stepping logic // diff --git a/src/coreclr/debug/ee/arm64/arm64walker.cpp b/src/coreclr/debug/ee/arm64/walker.cpp similarity index 99% rename from src/coreclr/debug/ee/arm64/arm64walker.cpp rename to src/coreclr/debug/ee/arm64/walker.cpp index 4a605b8..12b9e3b 100644 --- a/src/coreclr/debug/ee/arm64/arm64walker.cpp +++ b/src/coreclr/debug/ee/arm64/walker.cpp @@ -1,9 +1,7 @@ // Licensed to the .NET Foundation under one or more agreements. // The .NET Foundation licenses this file to you under the MIT license. -//***************************************************************************** -// File: Arm64walker.cpp -// +//***************************************************************************** // // ARM64 instruction decoding/stepping logic // diff --git a/src/coreclr/debug/ee/i386/x86walker.cpp b/src/coreclr/debug/ee/i386/walker.cpp similarity index 99% rename from src/coreclr/debug/ee/i386/x86walker.cpp rename to src/coreclr/debug/ee/i386/walker.cpp index cb262e7..ed01079 100644 --- a/src/coreclr/debug/ee/i386/x86walker.cpp +++ b/src/coreclr/debug/ee/i386/walker.cpp @@ -1,9 +1,7 @@ // Licensed to the .NET Foundation under one or more agreements. // The .NET Foundation licenses this file to you under the MIT license. -//***************************************************************************** -// File: x86walker.cpp -// +//***************************************************************************** // // x86 instruction decoding/stepping logic // diff --git a/src/coreclr/debug/ee/loongarch64/loongarch64walker.cpp b/src/coreclr/debug/ee/loongarch64/walker.cpp similarity index 99% rename from src/coreclr/debug/ee/loongarch64/loongarch64walker.cpp rename to src/coreclr/debug/ee/loongarch64/walker.cpp index fa2021b..01cf8de 100644 --- a/src/coreclr/debug/ee/loongarch64/loongarch64walker.cpp +++ b/src/coreclr/debug/ee/loongarch64/walker.cpp @@ -2,9 +2,6 @@ // The .NET Foundation licenses this file to you under the MIT license. //***************************************************************************** -// File: Loongarch64walker.cpp -// - // // LOONGARCH64 instruction decoding/stepping logic // diff --git a/src/coreclr/unwinder/s390x/unwinder_s390x.cpp b/src/coreclr/debug/ee/ppc64le/walker.cpp similarity index 70% rename from src/coreclr/unwinder/s390x/unwinder_s390x.cpp rename to src/coreclr/debug/ee/ppc64le/walker.cpp index 66cb24b..b267497 100644 --- a/src/coreclr/unwinder/s390x/unwinder_s390x.cpp +++ b/src/coreclr/debug/ee/ppc64le/walker.cpp @@ -1,11 +1,4 @@ // Licensed to the .NET Foundation under one or more agreements. // The .NET Foundation licenses this file to you under the MIT license. -// - -#include "stdafx.h" -#include "utilcode.h" -#include "crosscomp.h" - #error Unsupported platform - diff --git a/src/coreclr/debug/ee/riscv64/dbghelpers.S b/src/coreclr/debug/ee/riscv64/dbghelpers.S new file mode 100644 index 0000000..3515f38 --- /dev/null +++ b/src/coreclr/debug/ee/riscv64/dbghelpers.S @@ -0,0 +1,7 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#include "asmconstants.h" +#include "unixasmmacros.inc" + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/debug/ee/riscv64/primitives.cpp b/src/coreclr/debug/ee/riscv64/primitives.cpp new file mode 100644 index 0000000..c4b50b4 --- /dev/null +++ b/src/coreclr/debug/ee/riscv64/primitives.cpp @@ -0,0 +1,10 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +// + +#include "stdafx.h" +#include "threads.h" +#include "../../shared/riscv64/primitives.cpp" + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/debug/ee/riscv64/walker.cpp b/src/coreclr/debug/ee/riscv64/walker.cpp new file mode 100644 index 0000000..c428cd8 --- /dev/null +++ b/src/coreclr/debug/ee/riscv64/walker.cpp @@ -0,0 +1,19 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +//***************************************************************************** +// +// RISCV64 instruction decoding/stepping logic +// +//***************************************************************************** + +#include "stdafx.h" +#include "walker.h" +#include "frames.h" +#include "openum.h" + +#ifdef TARGET_RISCV64 + +#error "TODO-RISCV64: missing implementation" + +#endif diff --git a/src/coreclr/debug/ee/s390x/walker.cpp b/src/coreclr/debug/ee/s390x/walker.cpp new file mode 100644 index 0000000..b267497 --- /dev/null +++ b/src/coreclr/debug/ee/s390x/walker.cpp @@ -0,0 +1,4 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#error Unsupported platform diff --git a/src/coreclr/debug/shared/riscv64/primitives.cpp b/src/coreclr/debug/shared/riscv64/primitives.cpp new file mode 100644 index 0000000..50eae7b --- /dev/null +++ b/src/coreclr/debug/shared/riscv64/primitives.cpp @@ -0,0 +1,15 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +//***************************************************************************** +// File: primitives.cpp +// + +// +// Platform-specific debugger primitives +// +//***************************************************************************** + +#include "primitives.h" + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/gc/env/gcenv.interlocked.h b/src/coreclr/gc/env/gcenv.interlocked.h index f04b428..dfeed83 100644 --- a/src/coreclr/gc/env/gcenv.interlocked.h +++ b/src/coreclr/gc/env/gcenv.interlocked.h @@ -12,7 +12,7 @@ class Interlocked private: #ifndef _MSC_VER - static void ArmInterlockedOperationBarrier(); + static void InterlockedOperationBarrier(); #endif // !_MSC_VER public: diff --git a/src/coreclr/gc/env/gcenv.interlocked.inl b/src/coreclr/gc/env/gcenv.interlocked.inl index 03d487a..136348b 100644 --- a/src/coreclr/gc/env/gcenv.interlocked.inl +++ b/src/coreclr/gc/env/gcenv.interlocked.inl @@ -11,15 +11,12 @@ #endif // _MSC_VER #ifndef _MSC_VER -__forceinline void Interlocked::ArmInterlockedOperationBarrier() +__forceinline void Interlocked::InterlockedOperationBarrier() { -#ifdef HOST_ARM64 - // See PAL_ArmInterlockedOperationBarrier() in the PAL +#if defined(HOST_ARM64) || defined(HOST_LOONGARCH64) + // See PAL_InterlockedOperationBarrier() in the PAL __sync_synchronize(); -#endif // HOST_ARM64 -#ifdef HOST_LOONGARCH64 - __sync_synchronize(); -#endif //HOST_LOONGARCH64 +#endif } #endif // !_MSC_VER @@ -36,7 +33,7 @@ __forceinline T Interlocked::Increment(T volatile *addend) return _InterlockedIncrement((long*)addend); #else T result = __sync_add_and_fetch(addend, 1); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } @@ -54,7 +51,7 @@ __forceinline T Interlocked::Decrement(T volatile *addend) return _InterlockedDecrement((long*)addend); #else T result = __sync_sub_and_fetch(addend, 1); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } @@ -73,7 +70,7 @@ __forceinline T Interlocked::Exchange(T volatile *destination, T value) return _InterlockedExchange((long*)destination, value); #else T result = __atomic_exchange_n(destination, value, __ATOMIC_ACQ_REL); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } @@ -94,7 +91,7 @@ __forceinline T Interlocked::CompareExchange(T volatile *destination, T exchange return _InterlockedCompareExchange((long*)destination, exchange, comparand); #else T result = __sync_val_compare_and_swap(destination, comparand, exchange); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } @@ -113,7 +110,7 @@ __forceinline T Interlocked::ExchangeAdd(T volatile *addend, T value) return _InterlockedExchangeAdd((long*)addend, value); #else T result = __sync_fetch_and_add(addend, value); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } @@ -126,7 +123,7 @@ __forceinline T Interlocked::ExchangeAdd64(T volatile* addend, T value) return _InterlockedExchangeAdd64((int64_t*)addend, value); #else T result = __sync_fetch_and_add(addend, value); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } @@ -144,7 +141,7 @@ __forceinline T Interlocked::ExchangeAddPtr(T volatile* addend, T value) #endif #else T result = __sync_fetch_and_add(addend, value); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } @@ -161,7 +158,7 @@ __forceinline void Interlocked::And(T volatile *destination, T value) _InterlockedAnd((long*)destination, value); #else __sync_and_and_fetch(destination, value); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); #endif } @@ -177,7 +174,7 @@ __forceinline void Interlocked::Or(T volatile *destination, T value) _InterlockedOr((long*)destination, value); #else __sync_or_and_fetch(destination, value); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); #endif } @@ -198,7 +195,7 @@ __forceinline T Interlocked::ExchangePointer(T volatile * destination, T value) #endif #else T result = (T)(TADDR)__atomic_exchange_n((void* volatile *)destination, value, __ATOMIC_ACQ_REL); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } @@ -214,7 +211,7 @@ __forceinline T Interlocked::ExchangePointer(T volatile * destination, std::null #endif #else T result = (T)(TADDR)__atomic_exchange_n((void* volatile *)destination, value, __ATOMIC_ACQ_REL); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } @@ -238,7 +235,7 @@ __forceinline T Interlocked::CompareExchangePointer(T volatile *destination, T e #endif #else T result = (T)(TADDR)__sync_val_compare_and_swap((void* volatile *)destination, comparand, exchange); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } @@ -254,7 +251,7 @@ __forceinline T Interlocked::CompareExchangePointer(T volatile *destination, T e #endif #else T result = (T)(TADDR)__sync_val_compare_and_swap((void* volatile *)destination, (void*)comparand, (void*)exchange); - ArmInterlockedOperationBarrier(); + InterlockedOperationBarrier(); return result; #endif } diff --git a/src/coreclr/inc/crosscomp.h b/src/coreclr/inc/crosscomp.h index 9a78c69..79c246a 100644 --- a/src/coreclr/inc/crosscomp.h +++ b/src/coreclr/inc/crosscomp.h @@ -554,7 +554,7 @@ typedef struct _T_KNONVOLATILE_CONTEXT_POINTERS { #elif defined(TARGET_LINUX) && defined(TARGET_ARM) #define DAC_CS_NATIVE_DATA_SIZE 80 #elif defined(TARGET_LINUX) && defined(TARGET_ARM64) -#define DAC_CS_NATIVE_DATA_SIZE 116 +#define DAC_CS_NATIVE_DATA_SIZE 104 #elif defined(TARGET_LINUX) && defined(TARGET_LOONGARCH64) #define DAC_CS_NATIVE_DATA_SIZE 96 #elif defined(TARGET_LINUX) && defined(TARGET_X86) diff --git a/src/coreclr/jit/hashbv.h b/src/coreclr/jit/hashbv.h index 1ee3f35..ea9007b 100644 --- a/src/coreclr/jit/hashbv.h +++ b/src/coreclr/jit/hashbv.h @@ -4,7 +4,7 @@ #ifndef HASHBV_H #define HASHBV_H -#if defined(_M_AMD64) || defined(_M_X86) +#if defined(HOST_AMD64) || defined(HOST_X86) #include #endif diff --git a/src/coreclr/nativeaot/Runtime/arm64/AsmMacros.h b/src/coreclr/nativeaot/Runtime/arm64/AsmMacros.h index b857d1c..d6e3074 100644 --- a/src/coreclr/nativeaot/Runtime/arm64/AsmMacros.h +++ b/src/coreclr/nativeaot/Runtime/arm64/AsmMacros.h @@ -249,7 +249,7 @@ __SECTIONREL_tls_CurrentThread SETS "$__SECTIONREL_tls_CurrentThread":CC:"_" ;; MACRO - ArmInterlockedOperationBarrier + InterlockedOperationBarrier dmb ish MEND diff --git a/src/coreclr/nativeaot/Runtime/arm64/Interlocked.S b/src/coreclr/nativeaot/Runtime/arm64/Interlocked.S index 4b5aa6f..fa29bc2 100644 --- a/src/coreclr/nativeaot/Runtime/arm64/Interlocked.S +++ b/src/coreclr/nativeaot/Runtime/arm64/Interlocked.S @@ -20,7 +20,7 @@ ALTERNATE_ENTRY RhpLockCmpXchg32AVLocation cbnz w9, 1b 2: // exit - ArmInterlockedOperationBarrier + InterlockedOperationBarrier ret LEAF_END RhpLockCmpXchg32, _TEXT @@ -40,6 +40,6 @@ ALTERNATE_ENTRY RhpLockCmpXchg64AVLocation stlxr w9, x1, [x8] // if (x0 == x2) { try *x8 = x1 and goto loop if failed or goto exit } cbnz w9, 1b 2: // exit - ArmInterlockedOperationBarrier + InterlockedOperationBarrier ret LEAF_END RhpLockCmpXchg64, _TEXT diff --git a/src/coreclr/nativeaot/Runtime/arm64/Interlocked.asm b/src/coreclr/nativeaot/Runtime/arm64/Interlocked.asm index 19ba145..49df6cb 100644 --- a/src/coreclr/nativeaot/Runtime/arm64/Interlocked.asm +++ b/src/coreclr/nativeaot/Runtime/arm64/Interlocked.asm @@ -22,7 +22,7 @@ cbnz w9, %bt1 2 ;; exit - ArmInterlockedOperationBarrier + InterlockedOperationBarrier ret LEAF_END RhpLockCmpXchg32 @@ -43,7 +43,7 @@ cbnz w9, %bt1 2 ;; exit - ArmInterlockedOperationBarrier + InterlockedOperationBarrier ret LEAF_END RhpLockCmpXchg64 diff --git a/src/coreclr/nativeaot/Runtime/arm64/WriteBarriers.S b/src/coreclr/nativeaot/Runtime/arm64/WriteBarriers.S index 3a6cce9..4a3c3ed 100644 --- a/src/coreclr/nativeaot/Runtime/arm64/WriteBarriers.S +++ b/src/coreclr/nativeaot/Runtime/arm64/WriteBarriers.S @@ -270,7 +270,7 @@ CmpXchgRetry: CmpXchgNoUpdate: // x10 still contains the original value. mov x0, x10 - ArmInterlockedOperationBarrier + InterlockedOperationBarrier ret lr LEAF_END RhpCheckedLockCmpXchg, _TEXT @@ -311,7 +311,7 @@ ExchangeRetry: // x10 still contains the original value. mov x0, x10 - ArmInterlockedOperationBarrier + InterlockedOperationBarrier ret LEAF_END RhpCheckedXchg, _TEXT diff --git a/src/coreclr/nativeaot/Runtime/arm64/WriteBarriers.asm b/src/coreclr/nativeaot/Runtime/arm64/WriteBarriers.asm index 3889b08..005e80a 100644 --- a/src/coreclr/nativeaot/Runtime/arm64/WriteBarriers.asm +++ b/src/coreclr/nativeaot/Runtime/arm64/WriteBarriers.asm @@ -277,7 +277,7 @@ CmpXchgRetry CmpXchgNoUpdate ;; x10 still contains the original value. mov x0, x10 - ArmInterlockedOperationBarrier + InterlockedOperationBarrier ret lr LEAF_END RhpCheckedLockCmpXchg @@ -320,7 +320,7 @@ ExchangeRetry ;; x10 still contains the original value. mov x0, x10 - ArmInterlockedOperationBarrier + InterlockedOperationBarrier ret LEAF_END RhpCheckedXchg diff --git a/src/coreclr/nativeaot/Runtime/unix/unixasmmacrosarm64.inc b/src/coreclr/nativeaot/Runtime/unix/unixasmmacrosarm64.inc index 1fb8e47..1bd91a7 100644 --- a/src/coreclr/nativeaot/Runtime/unix/unixasmmacrosarm64.inc +++ b/src/coreclr/nativeaot/Runtime/unix/unixasmmacrosarm64.inc @@ -303,7 +303,7 @@ C_FUNC(\Name): EPILOG_RESTORE_REG_PAIR_INDEXED fp, lr, 96 .endm -.macro ArmInterlockedOperationBarrier +.macro InterlockedOperationBarrier dmb ish .endm diff --git a/src/coreclr/pal/inc/pal.h b/src/coreclr/pal/inc/pal.h index a48d0aa..7cab500 100644 --- a/src/coreclr/pal/inc/pal.h +++ b/src/coreclr/pal/inc/pal.h @@ -80,50 +80,6 @@ typedef PVOID NATIVE_LIBRARY_HANDLE; extern bool g_arm64_atomics_present; #endif -/******************* Processor-specific glue *****************************/ - -#ifndef _MSC_VER - -#if defined(__i686__) && !defined(_M_IX86) -#define _M_IX86 600 -#elif defined(__i586__) && !defined(_M_IX86) -#define _M_IX86 500 -#elif defined(__i486__) && !defined(_M_IX86) -#define _M_IX86 400 -#elif defined(__i386__) && !defined(_M_IX86) -#define _M_IX86 300 -#elif defined(__x86_64__) && !defined(_M_AMD64) -#define _M_AMD64 100 -#elif defined(__arm__) && !defined(_M_ARM) -#define _M_ARM 7 -#elif defined(__aarch64__) && !defined(_M_ARM64) -#define _M_ARM64 1 -#elif defined(__loongarch64) && !defined(_M_LOONGARCH64) -#define _M_LOONGARCH64 1 -#elif defined(__s390x__) && !defined(_M_S390X) -#define _M_S390X 1 -#elif defined(__powerpc__) && !defined(_M_PPC64) -#define _M_PPC64 1 -#endif - -#if defined(_M_IX86) && !defined(HOST_X86) -#define HOST_X86 -#elif defined(_M_AMD64) && !defined(HOST_AMD64) -#define HOST_AMD64 -#elif defined(_M_ARM) && !defined(HOST_ARM) -#define HOST_ARM -#elif defined(_M_ARM64) && !defined(HOST_ARM64) -#define HOST_ARM64 -#elif defined(_M_LOONGARCH64) && !defined(HOST_LOONGARCH64) -#define HOST_LOONGARCH64 -#elif defined(_M_S390X) && !defined(HOST_S390X) -#define HOST_S390X -#elif defined(_M_PPC64) && !defined(HOST_POWERPC64) -#define HOST_POWERPC64 -#endif - -#endif // !_MSC_VER - /******************* ABI-specific glue *******************************/ #define MAX_PATH 260 @@ -2678,7 +2634,7 @@ PALIMPORT BOOL PALAPI PAL_GetUnwindInfoSize(SIZE_T baseAddress, ULONG64 ehFrameH #elif defined(__linux__) && defined(HOST_ARM) #define PAL_CS_NATIVE_DATA_SIZE 80 #elif defined(__linux__) && defined(HOST_ARM64) -#define PAL_CS_NATIVE_DATA_SIZE 116 +#define PAL_CS_NATIVE_DATA_SIZE 104 #elif defined(__linux__) && defined(__i386__) #define PAL_CS_NATIVE_DATA_SIZE 76 #elif defined(__linux__) && defined(__x86_64__) @@ -2697,8 +2653,9 @@ PALIMPORT BOOL PALAPI PAL_GetUnwindInfoSize(SIZE_T baseAddress, ULONG64 ehFrameH #define PAL_CS_NATIVE_DATA_SIZE 48 #elif defined(__linux__) && defined(__loongarch64) #define PAL_CS_NATIVE_DATA_SIZE 96 +#elif defined(__linux__) && defined(_riscv) && __riscv_xlen == 64 +#define PAL_CS_NATIVE_DATA_SIZE 96 #else -#warning #error PAL_CS_NATIVE_DATA_SIZE is not defined for this architecture #endif @@ -3443,9 +3400,9 @@ BitScanReverse64( return qwMask != 0; } -FORCEINLINE void PAL_ArmInterlockedOperationBarrier() +FORCEINLINE void PAL_InterlockedOperationBarrier() { -#ifdef HOST_ARM64 +#if defined(HOST_ARM64) || defined(HOST_LOONGARCH64) || defined(HOST_RISCV64) // On arm64, most of the __sync* functions generate a code sequence like: // loop: // ldaxr (load acquire exclusive) @@ -3458,9 +3415,6 @@ FORCEINLINE void PAL_ArmInterlockedOperationBarrier() // require the load to occur after the store. This memory barrier should be used following a call to a __sync* function to // prevent that reordering. Code generated for arm32 includes a 'dmb' after 'cbnz', so no issue there at the moment. __sync_synchronize(); -#endif // HOST_ARM64 -#ifdef HOST_LOONGARCH64 - __sync_synchronize(); #endif } @@ -3495,7 +3449,7 @@ EXTERN_C PALIMPORT inline RETURN_TYPE PALAPI METHOD_DECL \ else \ { \ RETURN_TYPE result = INTRINSIC_NAME; \ - PAL_ArmInterlockedOperationBarrier(); \ + PAL_InterlockedOperationBarrier(); \ return result; \ } \ } \ @@ -3507,7 +3461,7 @@ EXTERN_C PALIMPORT inline RETURN_TYPE PALAPI METHOD_DECL \ EXTERN_C PALIMPORT inline RETURN_TYPE PALAPI METHOD_DECL \ { \ RETURN_TYPE result = INTRINSIC_NAME; \ - PAL_ArmInterlockedOperationBarrier(); \ + PAL_InterlockedOperationBarrier(); \ return result; \ } \ @@ -3788,6 +3742,8 @@ YieldProcessor() __asm__ __volatile__( "yield"); #elif defined(HOST_LOONGARCH64) __asm__ volatile( "dbar 0; \n"); +#elif defined(HOST_RISV64) + __asm__ __volatile__( "wfi"); #else return; #endif diff --git a/src/coreclr/pal/src/safecrt/cruntime.h b/src/coreclr/pal/src/safecrt/cruntime.h index 87dc02c..50b1e8a 100644 --- a/src/coreclr/pal/src/safecrt/cruntime.h +++ b/src/coreclr/pal/src/safecrt/cruntime.h @@ -35,14 +35,14 @@ #endif /* defined (_SYSCRT) && defined (HOST_64BIT) */ #if !defined (UNALIGNED) -#if defined (_M_AMD64) +#if defined (TARGET_AMD64) #define UNALIGNED __unaligned -#else /* defined (_M_AMD64) */ +#else /* defined (TARGET_AMD64) */ #define UNALIGNED -#endif /* defined (_M_AMD64) */ +#endif /* defined (TARGET_AMD64) */ #endif /* !defined (UNALIGNED) */ -#ifdef _M_IX86 +#ifdef TARGET_X86 /* * 386/486 */ @@ -56,7 +56,7 @@ #define REG8 #define REG9 -#elif defined (_M_AMD64) +#elif defined (TARGET_AMD64) /* * AMD64 */ @@ -70,7 +70,7 @@ #define REG8 register #define REG9 register -#else /* defined (_M_AMD64) */ +#else /* defined (TARGET_AMD64) */ #pragma message ("Machine register set not defined") @@ -88,7 +88,7 @@ #define REG8 #define REG9 -#endif /* defined (_M_AMD64) */ +#endif /* defined (TARGET_AMD64) */ /* * Are the macro definitions below still needed in this file? diff --git a/src/coreclr/unwinder/CMakeLists.txt b/src/coreclr/unwinder/CMakeLists.txt index e00e322..10b2d7c 100644 --- a/src/coreclr/unwinder/CMakeLists.txt +++ b/src/coreclr/unwinder/CMakeLists.txt @@ -8,13 +8,13 @@ include_directories(${CLR_DIR}/gcdump) include_directories(${CLR_DIR}/debug/daccess) set(UNWINDER_SOURCES - unwinder.cpp + baseunwinder.cpp ) # Include platform specific unwinder for applicable (native and cross-target) builds. include_directories(${ARCH_SOURCES_DIR}) list(APPEND UNWINDER_SOURCES - ${ARCH_SOURCES_DIR}/unwinder_${ARCH_SOURCES_DIR}.cpp + ${ARCH_SOURCES_DIR}/unwinder.cpp ) convert_to_absolute_path(UNWINDER_SOURCES ${UNWINDER_SOURCES}) diff --git a/src/coreclr/unwinder/amd64/unwinder_amd64.cpp b/src/coreclr/unwinder/amd64/unwinder.cpp similarity index 99% rename from src/coreclr/unwinder/amd64/unwinder_amd64.cpp rename to src/coreclr/unwinder/amd64/unwinder.cpp index fc9e08b..cf4b96f 100644 --- a/src/coreclr/unwinder/amd64/unwinder_amd64.cpp +++ b/src/coreclr/unwinder/amd64/unwinder.cpp @@ -4,7 +4,7 @@ // #include "stdafx.h" -#include "unwinder_amd64.h" +#include "unwinder.h" typedef DPTR(M128A) PTR_M128A; diff --git a/src/coreclr/unwinder/amd64/unwinder_amd64.h b/src/coreclr/unwinder/amd64/unwinder.h similarity index 98% rename from src/coreclr/unwinder/amd64/unwinder_amd64.h rename to src/coreclr/unwinder/amd64/unwinder.h index c7a7683..1c71422 100644 --- a/src/coreclr/unwinder/amd64/unwinder_amd64.h +++ b/src/coreclr/unwinder/amd64/unwinder.h @@ -6,7 +6,7 @@ #ifndef __unwinder_amd64_h__ #define __unwinder_amd64_h__ -#include "unwinder.h" +#include "baseunwinder.h" //--------------------------------------------------------------------------------------- diff --git a/src/coreclr/unwinder/arm/unwinder_arm.cpp b/src/coreclr/unwinder/arm/unwinder.cpp similarity index 99% rename from src/coreclr/unwinder/arm/unwinder_arm.cpp rename to src/coreclr/unwinder/arm/unwinder.cpp index c63613d..0bbf611 100644 --- a/src/coreclr/unwinder/arm/unwinder_arm.cpp +++ b/src/coreclr/unwinder/arm/unwinder.cpp @@ -6,7 +6,7 @@ #include "stdafx.h" #include "utilcode.h" -#include "unwinder_arm.h" +#include "unwinder.h" #define DBS_EXTEND64(x) ((DWORD64)x) #define MEMORY_READ_BYTE(params, addr) (*dac_cast(addr)) diff --git a/src/coreclr/unwinder/arm/unwinder_arm.h b/src/coreclr/unwinder/arm/unwinder.h similarity index 98% rename from src/coreclr/unwinder/arm/unwinder_arm.h rename to src/coreclr/unwinder/arm/unwinder.h index cb73307..396a48e 100644 --- a/src/coreclr/unwinder/arm/unwinder_arm.h +++ b/src/coreclr/unwinder/arm/unwinder.h @@ -6,7 +6,7 @@ #ifndef __unwinder_arm__ #define __unwinder_arm__ -#include "unwinder.h" +#include "baseunwinder.h" //--------------------------------------------------------------------------------------- diff --git a/src/coreclr/unwinder/arm64/unwinder_arm64.cpp b/src/coreclr/unwinder/arm64/unwinder.cpp similarity index 99% rename from src/coreclr/unwinder/arm64/unwinder_arm64.cpp rename to src/coreclr/unwinder/arm64/unwinder.cpp index 1eddb18..6a4c25e 100644 --- a/src/coreclr/unwinder/arm64/unwinder_arm64.cpp +++ b/src/coreclr/unwinder/arm64/unwinder.cpp @@ -7,7 +7,7 @@ #include "utilcode.h" #include "crosscomp.h" -#include "unwinder_arm64.h" +#include "unwinder.h" typedef struct _ARM64_KTRAP_FRAME { diff --git a/src/coreclr/unwinder/arm64/unwinder_arm64.h b/src/coreclr/unwinder/arm64/unwinder.h similarity index 98% rename from src/coreclr/unwinder/arm64/unwinder_arm64.h rename to src/coreclr/unwinder/arm64/unwinder.h index 701a3e4..aa03c5a 100644 --- a/src/coreclr/unwinder/arm64/unwinder_arm64.h +++ b/src/coreclr/unwinder/arm64/unwinder.h @@ -6,7 +6,7 @@ #ifndef __unwinder_arm64__ #define __unwinder_arm64__ -#include "unwinder.h" +#include "baseunwinder.h" //--------------------------------------------------------------------------------------- diff --git a/src/coreclr/unwinder/unwinder.cpp b/src/coreclr/unwinder/baseunwinder.cpp similarity index 98% rename from src/coreclr/unwinder/unwinder.cpp rename to src/coreclr/unwinder/baseunwinder.cpp index 08829fa..e059b93 100644 --- a/src/coreclr/unwinder/unwinder.cpp +++ b/src/coreclr/unwinder/baseunwinder.cpp @@ -4,7 +4,7 @@ // #include "stdafx.h" -#include "unwinder.h" +#include "baseunwinder.h" EXTERN_C void GetRuntimeStackWalkInfo(IN ULONG64 ControlPc, OUT UINT_PTR* pModuleBase, diff --git a/src/coreclr/unwinder/unwinder.h b/src/coreclr/unwinder/baseunwinder.h similarity index 100% rename from src/coreclr/unwinder/unwinder.h rename to src/coreclr/unwinder/baseunwinder.h diff --git a/src/coreclr/unwinder/i386/unwinder_i386.cpp b/src/coreclr/unwinder/i386/unwinder.cpp similarity index 99% rename from src/coreclr/unwinder/i386/unwinder_i386.cpp rename to src/coreclr/unwinder/i386/unwinder.cpp index f4af20e..5ee1193 100644 --- a/src/coreclr/unwinder/i386/unwinder_i386.cpp +++ b/src/coreclr/unwinder/i386/unwinder.cpp @@ -4,7 +4,7 @@ // #include "stdafx.h" -#include "unwinder_i386.h" +#include "unwinder.h" #ifdef FEATURE_EH_FUNCLETS BOOL OOPStackUnwinderX86::Unwind(T_CONTEXT* pContextRecord, T_KNONVOLATILE_CONTEXT_POINTERS* pContextPointers) diff --git a/src/coreclr/unwinder/i386/unwinder_i386.h b/src/coreclr/unwinder/i386/unwinder.h similarity index 97% rename from src/coreclr/unwinder/i386/unwinder_i386.h rename to src/coreclr/unwinder/i386/unwinder.h index 904ec80..9e60af2 100644 --- a/src/coreclr/unwinder/i386/unwinder_i386.h +++ b/src/coreclr/unwinder/i386/unwinder.h @@ -6,7 +6,7 @@ #ifndef __unwinder_i386_h__ #define __unwinder_i386_h__ -#include "unwinder.h" +#include "baseunwinder.h" #ifdef FEATURE_EH_FUNCLETS //--------------------------------------------------------------------------------------- diff --git a/src/coreclr/unwinder/loongarch64/unwinder_loongarch64.cpp b/src/coreclr/unwinder/loongarch64/unwinder.cpp similarity index 99% rename from src/coreclr/unwinder/loongarch64/unwinder_loongarch64.cpp rename to src/coreclr/unwinder/loongarch64/unwinder.cpp index 1d64d0d..47d36cc 100644 --- a/src/coreclr/unwinder/loongarch64/unwinder_loongarch64.cpp +++ b/src/coreclr/unwinder/loongarch64/unwinder.cpp @@ -7,7 +7,7 @@ #include "utilcode.h" #include "crosscomp.h" -#include "unwinder_loongarch64.h" +#include "unwinder.h" typedef struct _LOONGARCH64_KTRAP_FRAME { diff --git a/src/coreclr/unwinder/loongarch64/unwinder_loongarch64.h b/src/coreclr/unwinder/loongarch64/unwinder.h similarity index 98% rename from src/coreclr/unwinder/loongarch64/unwinder_loongarch64.h rename to src/coreclr/unwinder/loongarch64/unwinder.h index 44ce7d6..5742579 100644 --- a/src/coreclr/unwinder/loongarch64/unwinder_loongarch64.h +++ b/src/coreclr/unwinder/loongarch64/unwinder.h @@ -6,7 +6,7 @@ #ifndef __unwinder_loongarch64__ #define __unwinder_loongarch64__ -#include "unwinder.h" +#include "baseunwinder.h" //--------------------------------------------------------------------------------------- // diff --git a/src/coreclr/unwinder/ppc64le/unwinder.cpp b/src/coreclr/unwinder/ppc64le/unwinder.cpp new file mode 100644 index 0000000..b267497 --- /dev/null +++ b/src/coreclr/unwinder/ppc64le/unwinder.cpp @@ -0,0 +1,4 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#error Unsupported platform diff --git a/src/coreclr/unwinder/ppc64le/unwinder_ppc64le.cpp b/src/coreclr/unwinder/riscv64/unwinder.cpp similarity index 75% rename from src/coreclr/unwinder/ppc64le/unwinder_ppc64le.cpp rename to src/coreclr/unwinder/riscv64/unwinder.cpp index 66cb24b..bec3a8d 100644 --- a/src/coreclr/unwinder/ppc64le/unwinder_ppc64le.cpp +++ b/src/coreclr/unwinder/riscv64/unwinder.cpp @@ -7,5 +7,6 @@ #include "utilcode.h" #include "crosscomp.h" -#error Unsupported platform +#include "unwinder.h" +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/unwinder/riscv64/unwinder.h b/src/coreclr/unwinder/riscv64/unwinder.h new file mode 100644 index 0000000..efcd109 --- /dev/null +++ b/src/coreclr/unwinder/riscv64/unwinder.h @@ -0,0 +1,13 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +// + +#ifndef __unwinder_riscv64__ +#define __unwinder_riscv64__ + +#include "baseunwinder.h" + +#error "TODO-RISCV64: missing implementation" + +#endif // __unwinder_riscv64__ diff --git a/src/coreclr/unwinder/s390x/unwinder.cpp b/src/coreclr/unwinder/s390x/unwinder.cpp new file mode 100644 index 0000000..b267497 --- /dev/null +++ b/src/coreclr/unwinder/s390x/unwinder.cpp @@ -0,0 +1,4 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#error Unsupported platform diff --git a/src/coreclr/vm/CMakeLists.txt b/src/coreclr/vm/CMakeLists.txt index cbf94be..b97a405 100644 --- a/src/coreclr/vm/CMakeLists.txt +++ b/src/coreclr/vm/CMakeLists.txt @@ -829,7 +829,7 @@ elseif(CLR_CMAKE_TARGET_ARCH_ARM) set(VM_SOURCES_WKS_ARCH ${ARCH_SOURCES_DIR}/profiler.cpp - ${ARCH_SOURCES_DIR}/armsinglestepper.cpp + ${ARCH_SOURCES_DIR}/singlestepper.cpp exceptionhandling.cpp gcinfodecoder.cpp ) @@ -855,7 +855,7 @@ elseif(CLR_CMAKE_TARGET_ARCH_ARM64) if(CLR_CMAKE_HOST_UNIX) list(APPEND VM_SOURCES_WKS_ARCH - ${ARCH_SOURCES_DIR}/arm64singlestepper.cpp + ${ARCH_SOURCES_DIR}/singlestepper.cpp ) endif(CLR_CMAKE_HOST_UNIX) elseif(CLR_CMAKE_TARGET_ARCH_LOONGARCH64) diff --git a/src/coreclr/vm/arm/armsinglestepper.cpp b/src/coreclr/vm/arm/singlestepper.cpp similarity index 100% rename from src/coreclr/vm/arm/armsinglestepper.cpp rename to src/coreclr/vm/arm/singlestepper.cpp diff --git a/src/coreclr/vm/arm64/arm64singlestepper.cpp b/src/coreclr/vm/arm64/singlestepper.cpp similarity index 100% rename from src/coreclr/vm/arm64/arm64singlestepper.cpp rename to src/coreclr/vm/arm64/singlestepper.cpp diff --git a/src/coreclr/vm/riscv64/asmconstants.h b/src/coreclr/vm/riscv64/asmconstants.h new file mode 100644 index 0000000..9a0cdd4 --- /dev/null +++ b/src/coreclr/vm/riscv64/asmconstants.h @@ -0,0 +1,4 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/asmhelpers.S b/src/coreclr/vm/riscv64/asmhelpers.S new file mode 100644 index 0000000..3515f38 --- /dev/null +++ b/src/coreclr/vm/riscv64/asmhelpers.S @@ -0,0 +1,7 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#include "asmconstants.h" +#include "unixasmmacros.inc" + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/calldescrworkerloongarch64.S b/src/coreclr/vm/riscv64/calldescrworkerloongarch64.S new file mode 100644 index 0000000..a7cd5b6 --- /dev/null +++ b/src/coreclr/vm/riscv64/calldescrworkerloongarch64.S @@ -0,0 +1,7 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#include "unixasmmacros.inc" +#include "asmconstants.h" + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/cgencpu.h b/src/coreclr/vm/riscv64/cgencpu.h new file mode 100644 index 0000000..9a0cdd4 --- /dev/null +++ b/src/coreclr/vm/riscv64/cgencpu.h @@ -0,0 +1,4 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/crthelpers.S b/src/coreclr/vm/riscv64/crthelpers.S new file mode 100644 index 0000000..f6c1fb2 --- /dev/null +++ b/src/coreclr/vm/riscv64/crthelpers.S @@ -0,0 +1,6 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#include "unixasmmacros.inc" + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/excepcpu.h b/src/coreclr/vm/riscv64/excepcpu.h new file mode 100644 index 0000000..4800154 --- /dev/null +++ b/src/coreclr/vm/riscv64/excepcpu.h @@ -0,0 +1,7 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#ifndef __excepcpu_h__ +#define __excepcpu_h__ + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/gmscpu.h b/src/coreclr/vm/riscv64/gmscpu.h new file mode 100644 index 0000000..9a0cdd4 --- /dev/null +++ b/src/coreclr/vm/riscv64/gmscpu.h @@ -0,0 +1,4 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/pinvokestubs.S b/src/coreclr/vm/riscv64/pinvokestubs.S new file mode 100644 index 0000000..3515f38 --- /dev/null +++ b/src/coreclr/vm/riscv64/pinvokestubs.S @@ -0,0 +1,7 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#include "asmconstants.h" +#include "unixasmmacros.inc" + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/profiler.cpp b/src/coreclr/vm/riscv64/profiler.cpp new file mode 100644 index 0000000..8d7dc92 --- /dev/null +++ b/src/coreclr/vm/riscv64/profiler.cpp @@ -0,0 +1,6 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#include "common.h" + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/stubs.cpp b/src/coreclr/vm/riscv64/stubs.cpp new file mode 100644 index 0000000..9a0cdd4 --- /dev/null +++ b/src/coreclr/vm/riscv64/stubs.cpp @@ -0,0 +1,4 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/thunktemplates.S b/src/coreclr/vm/riscv64/thunktemplates.S new file mode 100644 index 0000000..a7cd5b6 --- /dev/null +++ b/src/coreclr/vm/riscv64/thunktemplates.S @@ -0,0 +1,7 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#include "unixasmmacros.inc" +#include "asmconstants.h" + +#error "TODO-RISCV64: missing implementation" diff --git a/src/coreclr/vm/riscv64/unixstubs.cpp b/src/coreclr/vm/riscv64/unixstubs.cpp new file mode 100644 index 0000000..d51902a --- /dev/null +++ b/src/coreclr/vm/riscv64/unixstubs.cpp @@ -0,0 +1,12 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#include "common.h" + +extern "C" +{ + void RedirectForThrowControl() + { + PORTABILITY_ASSERT("Implement for PAL"); + } +}; diff --git a/src/coreclr/vm/riscv64/virtualcallstubcpu.hpp b/src/coreclr/vm/riscv64/virtualcallstubcpu.hpp new file mode 100644 index 0000000..9a0cdd4 --- /dev/null +++ b/src/coreclr/vm/riscv64/virtualcallstubcpu.hpp @@ -0,0 +1,4 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#error "TODO-RISCV64: missing implementation" -- 2.7.4