From 53652feab7dd651309301bea70600f8ccd2685a0 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Fri, 8 Mar 2019 19:16:26 +0000
Subject: [PATCH] [X86] Add test case for PR22473

llvm-svn: 355712
---
 llvm/test/CodeGen/X86/pr22473.ll | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/pr22473.ll

diff --git a/llvm/test/CodeGen/X86/pr22473.ll b/llvm/test/CodeGen/X86/pr22473.ll
new file mode 100644
index 0000000..145f81d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr22473.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=X64
+
+define zeroext i1 @PR22473(i8*, i8) {
+; X86-LABEL: PR22473:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb (%eax), %al
+; X86-NEXT:    cmpb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    sete %al
+; X86-NEXT:    retl
+;
+; X64-LABEL: PR22473:
+; X64:       # %bb.0:
+; X64-NEXT:    cmpb %sil, (%rdi)
+; X64-NEXT:    sete %al
+; X64-NEXT:    retq
+  %3 = load i8, i8* %0, align 1
+  %4 = icmp eq i8 %3, %1
+  ret i1 %4
+}
-- 
2.7.4