From 531acf548a01d5e040de5f6335b04b6d43a217d4 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Mon, 20 Mar 2023 12:15:02 +0800 Subject: [PATCH] ac/llvm: move ac_fixup_ls_hs_input_vgprs to amd common MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit To be shared with radeonsi. Reviewed-by: Marek Olšák Signed-off-by: Qiang Yu Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 20 ++++++++++++++++++++ src/amd/llvm/ac_nir_to_llvm.h | 3 +++ src/amd/vulkan/radv_nir_to_llvm.c | 20 +------------------- 3 files changed, 24 insertions(+), 19 deletions(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 8d0d3d6..bf51487 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -5144,3 +5144,23 @@ bool ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi, return true; } + +/* Fixup the HW not emitting the TCS regs if there are no HS threads. */ +void ac_fixup_ls_hs_input_vgprs(struct ac_llvm_context *ac, struct ac_shader_abi *abi, + const struct ac_shader_args *args) +{ + LLVMValueRef count = ac_unpack_param(ac, ac_get_arg(ac, args->merged_wave_info), 8, 8); + LLVMValueRef hs_empty = LLVMBuildICmp(ac->builder, LLVMIntEQ, count, ac->i32_0, ""); + + abi->instance_id = + LLVMBuildSelect(ac->builder, hs_empty, ac_get_arg(ac, args->vertex_id), + abi->instance_id, ""); + + abi->vs_rel_patch_id = + LLVMBuildSelect(ac->builder, hs_empty, ac_get_arg(ac, args->tcs_rel_ids), + abi->vs_rel_patch_id, ""); + + abi->vertex_id = + LLVMBuildSelect(ac->builder, hs_empty, ac_get_arg(ac, args->tcs_patch_id), + abi->vertex_id, ""); +} diff --git a/src/amd/llvm/ac_nir_to_llvm.h b/src/amd/llvm/ac_nir_to_llvm.h index 33888f1..e0c6f2f 100644 --- a/src/amd/llvm/ac_nir_to_llvm.h +++ b/src/amd/llvm/ac_nir_to_llvm.h @@ -50,4 +50,7 @@ static inline unsigned ac_llvm_reg_index_soa(unsigned index, unsigned chan) bool ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi, const struct ac_shader_args *args, struct nir_shader *nir); +void ac_fixup_ls_hs_input_vgprs(struct ac_llvm_context *ac, struct ac_shader_abi *abi, + const struct ac_shader_args *args); + #endif /* AC_NIR_TO_LLVM_H */ diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 7f2e31b..0cde5b1 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -614,24 +614,6 @@ ac_llvm_finalize_module(struct radv_shader_context *ctx, LLVMPassManagerRef pass ac_llvm_context_dispose(&ctx->ac); } -/* Fixup the HW not emitting the TCS regs if there are no HS threads. */ -static void -ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx) -{ - LLVMValueRef count = - ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.merged_wave_info), 8, 8); - LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count, ctx->ac.i32_0, ""); - ctx->abi.instance_id = - LLVMBuildSelect(ctx->ac.builder, hs_empty, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id), - ctx->abi.instance_id, ""); - ctx->abi.vs_rel_patch_id = - LLVMBuildSelect(ctx->ac.builder, hs_empty, ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids), - ctx->abi.vs_rel_patch_id, ""); - ctx->abi.vertex_id = - LLVMBuildSelect(ctx->ac.builder, hs_empty, ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id), - ctx->abi.vertex_id, ""); -} - static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged) { @@ -748,7 +730,7 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, if (options->has_ls_vgpr_init_bug && shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL) - ac_nir_fixup_ls_hs_input_vgprs(&ctx); + ac_fixup_ls_hs_input_vgprs(&ctx.ac, &ctx.abi, &args->ac); if (is_ngg) { if (!info->is_ngg_passthrough) -- 2.7.4