From 530c0b8a8beb80ea4ebad70bec23bfe69c0cab23 Mon Sep 17 00:00:00 2001 From: Evoke Zhang Date: Tue, 25 Dec 2018 13:10:00 +0800 Subject: [PATCH] lcd: update phy config for tl1 [1/1] PD#SWPL-3109 Problem: tl1 tcon phy config need update Solution: 1.update tcon phy config for tl1 2.optimize phy config with independent file Verify: x301 Change-Id: I869cab8fc28fc9d323ca0365fc6eead1c6bc53d7 Signed-off-by: Evoke Zhang --- MAINTAINERS | 2 + drivers/amlogic/media/vout/lcd/Makefile | 4 +- drivers/amlogic/media/vout/lcd/lcd_common.c | 66 --- drivers/amlogic/media/vout/lcd/lcd_common.h | 59 +-- drivers/amlogic/media/vout/lcd/lcd_debug.c | 140 +----- drivers/amlogic/media/vout/lcd/lcd_phy_config.c | 554 +++++++++++++++++++++ drivers/amlogic/media/vout/lcd/lcd_phy_config.h | 87 ++++ .../amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c | 178 ------- drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c | 271 ---------- 9 files changed, 677 insertions(+), 684 deletions(-) create mode 100644 drivers/amlogic/media/vout/lcd/lcd_phy_config.c create mode 100644 drivers/amlogic/media/vout/lcd/lcd_phy_config.h diff --git a/MAINTAINERS b/MAINTAINERS index bc4e9eb..ffc6f35 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14745,6 +14745,8 @@ M: Evoke Zhang F: arch/arm/boot/dts/amlogic/mesontl1_skt-panel.dtsi F: arch/arm/boot/dts/amlogic/mesontl1_x301-panel.dtsi F: arch/arm/boot/dts/amlogic/mesontl1_t309-panel.dtsi +F: drivers/amlogic/media/vout/lcd/lcd_phy_config.c +F: drivers/amlogic/media/vout/lcd/lcd_phy_config.h AMLOGIC MESONAXG RSR DTS M: Yeping Miao diff --git a/drivers/amlogic/media/vout/lcd/Makefile b/drivers/amlogic/media/vout/lcd/Makefile index c5dab01..8b3baf1 100644 --- a/drivers/amlogic/media/vout/lcd/Makefile +++ b/drivers/amlogic/media/vout/lcd/Makefile @@ -1,6 +1,6 @@ obj-$(CONFIG_AMLOGIC_LCD) += lcd_vout.o lcd_reg.o lcd_common.o lcd_notify.o \ - lcd_debug.o lcd_clk_config.o lcd_unifykey.o \ - lcd_tcon.o + lcd_debug.o lcd_clk_config.o lcd_phy_config.o \ + lcd_unifykey.o lcd_tcon.o obj-$(CONFIG_AMLOGIC_LCD_TV) += lcd_tv/ obj-$(CONFIG_AMLOGIC_LCD_TABLET) += lcd_tablet/ obj-$(CONFIG_AMLOGIC_LCD_EXTERN) += lcd_extern/ diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.c b/drivers/amlogic/media/vout/lcd/lcd_common.c index 0c5fe32..5beccbd 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_common.c +++ b/drivers/amlogic/media/vout/lcd/lcd_common.c @@ -401,72 +401,6 @@ void lcd_tcon_pinmux_set(int status) pconf->pinmux_flag = index; } -unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf) -{ - unsigned int channel_on = 0; - - if (pconf->lcd_control.lvds_config->dual_port == 0) { - if (pconf->lcd_control.lvds_config->lane_reverse == 0) { - switch (pconf->lcd_basic.lcd_bits) { - case 6: - channel_on = 0xf; - break; - case 8: - channel_on = 0x1f; - break; - case 10: - default: - channel_on = 0x3f; - break; - } - } else { - switch (pconf->lcd_basic.lcd_bits) { - case 6: - channel_on = 0x3c; - break; - case 8: - channel_on = 0x3e; - break; - case 10: - default: - channel_on = 0x3f; - break; - } - } - if (pconf->lcd_control.lvds_config->port_swap == 1) - channel_on = (channel_on << 6); /* use channel B */ - } else { - if (pconf->lcd_control.lvds_config->lane_reverse == 0) { - switch (pconf->lcd_basic.lcd_bits) { - case 6: - channel_on = 0x3cf; - break; - case 8: - channel_on = 0x7df; - break; - case 10: - default: - channel_on = 0xfff; - break; - } - } else { - switch (pconf->lcd_basic.lcd_bits) { - case 6: - channel_on = 0xf3c; - break; - case 8: - channel_on = 0xfbe; - break; - case 10: - default: - channel_on = 0xfff; - break; - } - } - } - return channel_on; -} - int lcd_power_load_from_dts(struct lcd_config_s *pconf, struct device_node *child) { diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.h b/drivers/amlogic/media/vout/lcd/lcd_common.h index 3e790508..54441aa 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_common.h +++ b/drivers/amlogic/media/vout/lcd/lcd_common.h @@ -34,57 +34,11 @@ /* 20180928: tl1 support, optimize clk config */ /* 20181012: tl1 support tcon */ /* 20181212: tl1 update p2p config and pll setting */ -#define LCD_DRV_VERSION "20181212" +/* 20181225: update phy config */ +#define LCD_DRV_VERSION "20181225" #define VPP_OUT_SATURATE (1 << 0) -/* -------------------------- */ -/* lvsd phy parameters define */ -/* -------------------------- */ -#define LVDS_PHY_CNTL1_G9TV 0x606cca80 -#define LVDS_PHY_CNTL2_G9TV 0x0000006c -#define LVDS_PHY_CNTL3_G9TV 0x00000800 - -#define LVDS_PHY_CNTL1_TL1 0x6c60ca80 -#define LVDS_PHY_CNTL2_TL1 0x00000070 -#define LVDS_PHY_CNTL3_TL1 0x03ff0c00 -/* -------------------------- */ - -/* -------------------------- */ -/* vbyone phy parameters define */ -/* -------------------------- */ -#define VX1_PHY_CNTL1_G9TV 0x6e0ec900 -#define VX1_PHY_CNTL1_G9TV_PULLUP 0x6e0f4d00 -#define VX1_PHY_CNTL2_G9TV 0x0000007c -#define VX1_PHY_CNTL3_G9TV 0x00ff0800 -/* -------------------------- */ - -/* -------------------------- */ -/* minilvds phy parameters define */ -/* -------------------------- */ -#define MLVDS_PHY_CNTL1_TL1 0x6c60ca80 -#define MLVDS_PHY_CNTL2_TL1 0x00000070 -#define MLVDS_PHY_CNTL3_TL1 0x03ff0c00 - - -/* ******** mipi_dsi_phy ******** */ -/* bit[15:11] */ -#define MIPI_PHY_LANE_BIT 11 -#define MIPI_PHY_LANE_WIDTH 5 - -/* MIPI-DSI */ -#define DSI_LANE_0 (1 << 4) -#define DSI_LANE_1 (1 << 3) -#define DSI_LANE_CLK (1 << 2) -#define DSI_LANE_2 (1 << 1) -#define DSI_LANE_3 (1 << 0) -#define DSI_LANE_COUNT_1 (DSI_LANE_CLK | DSI_LANE_0) -#define DSI_LANE_COUNT_2 (DSI_LANE_CLK | DSI_LANE_0 | DSI_LANE_1) -#define DSI_LANE_COUNT_3 (DSI_LANE_CLK | DSI_LANE_0 |\ - DSI_LANE_1 | DSI_LANE_2) -#define DSI_LANE_COUNT_4 (DSI_LANE_CLK | DSI_LANE_0 |\ - DSI_LANE_1 | DSI_LANE_2 | DSI_LANE_3) - extern struct mutex lcd_vout_mutex; extern unsigned char lcd_resume_flag; extern int lcd_vout_serve_bypass; @@ -101,7 +55,7 @@ extern unsigned int lcd_cpu_gpio_get(unsigned int index); extern void lcd_ttl_pinmux_set(int status); extern void lcd_vbyone_pinmux_set(int status); extern void lcd_tcon_pinmux_set(int status); -extern unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf); + extern int lcd_power_load_from_dts(struct lcd_config_s *pconf, struct device_node *child); extern int lcd_power_load_from_unifykey(struct lcd_config_s *pconf, @@ -117,6 +71,13 @@ extern int lcd_vmode_change(struct lcd_config_s *pconf); extern void lcd_venc_change(struct lcd_config_s *pconf); extern void lcd_if_enable_retry(struct lcd_config_s *pconf); +/* lcd phy */ +extern void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status); +extern void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status); +extern void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status); +extern void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status); +extern void lcd_mipi_phy_set(struct lcd_config_s *pconf, int status); + /* lcd tcon */ extern unsigned int lcd_tcon_reg_read(unsigned int addr); extern void lcd_tcon_reg_write(unsigned int addr, unsigned int val); diff --git a/drivers/amlogic/media/vout/lcd/lcd_debug.c b/drivers/amlogic/media/vout/lcd/lcd_debug.c index e09c5dd..259cb42 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_debug.c +++ b/drivers/amlogic/media/vout/lcd/lcd_debug.c @@ -3499,10 +3499,7 @@ static void lcd_phy_config_update(unsigned int *para, int cnt) { struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); struct lcd_config_s *pconf; - struct lvds_config_s *lvdsconf; - int type; - unsigned int data32, vswing, preem, ext_pullup; - unsigned int rinner_table[] = {0xa, 0xa, 0x6, 0x4}; + struct lvds_config_s *lvds_conf; if (lcd_drv->data->chip_type == LCD_CHIP_TL1) { LCDPR("%s: not support yet\n", __func__); @@ -3510,55 +3507,29 @@ static void lcd_phy_config_update(unsigned int *para, int cnt) } pconf = lcd_drv->lcd_config; - type = pconf->lcd_basic.lcd_type; - switch (type) { + switch (pconf->lcd_basic.lcd_type) { case LCD_LVDS: - lvdsconf = pconf->lcd_control.lvds_config; + lvds_conf = pconf->lcd_control.lvds_config; if (cnt == 4) { - if ((para[0] > 7) || (para[1] > 7) || - (para[2] > 3) || (para[3] > 7)) { - LCDERR("%s: wrong value:\n", __func__); - pr_info("vswing=%d, preem=%d\n", - para[0], para[1]); - pr_info("clk vswing=%d, preem=%d\n", - para[2], para[3]); - return; - } + lvds_conf->phy_vswing = para[0]; + lvds_conf->phy_preem = para[1]; + lvds_conf->phy_clk_vswing = para[2]; + lvds_conf->phy_clk_preem = para[3]; - lvdsconf->phy_vswing = para[0]; - lvdsconf->phy_preem = para[1]; - lvdsconf->phy_clk_vswing = para[2]; - lvdsconf->phy_clk_preem = para[3]; - - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL1); - data32 &= ~((0x7 << 26) | (0x7 << 0)); - data32 |= ((para[0] << 26) | (para[1] << 0)); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL3); - data32 &= ~((0x3 << 8) | (0x7 << 5)); - data32 |= ((para[2] << 8) | (para[3] << 5)); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + if (lcd_drv->lcd_status & LCD_STATUS_IF_ON) + lcd_lvds_phy_set(pconf, 1); LCDPR("%s:\n", __func__); pr_info("vswing=0x%x, preemphasis=0x%x\n", para[0], para[1]); - pr_info("clk_vswing=0x%x, clk_preem=0x%x\n", + pr_info("clk_vswing=0x%x, clk_preem=0x%x\n", para[2], para[3]); } else if (cnt == 2) { - if ((para[0] > 7) || (para[1] > 7)) { - LCDERR("%s: wrong value:\n", __func__); - pr_info("vswing=%d, preem=%d\n", - para[0], para[1]); - return; - } - - lvdsconf->phy_vswing = para[0]; - lvdsconf->phy_preem = para[1]; + lvds_conf->phy_vswing = para[0]; + lvds_conf->phy_preem = para[1]; - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL1); - data32 &= ~((0x7 << 26) | (0x7 << 0)); - data32 |= ((para[0] << 26) | (para[1] << 0)); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + if (lcd_drv->lcd_status & LCD_STATUS_IF_ON) + lcd_lvds_phy_set(pconf, 1); LCDPR("%s: vswing=0x%x, preemphasis=0x%x\n", __func__, para[0], para[1]); @@ -3569,33 +3540,11 @@ static void lcd_phy_config_update(unsigned int *para, int cnt) break; case LCD_VBYONE: if (cnt >= 2) { - ext_pullup = (para[0] >> 4) & 0x3; - vswing = para[0] & 0xf; - preem = para[1]; - if ((vswing > 7) || (preem > 7)) { - LCDERR("%s: wrong value:\n", __func__); - pr_info("vswing=%d, preemphasis=%d\n", - vswing, preem); - return; - } - pconf->lcd_control.vbyone_config->phy_vswing = para[0]; pconf->lcd_control.vbyone_config->phy_preem = para[1]; - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL1); - data32 &= ~((0x7 << 3) | (1 << 10) | - (1 << 15) | (1 << 16)); - data32 |= (vswing << 3); - if (ext_pullup) - data32 |= ((1 << 10) | (1 << 16)); - else - data32 |= (1 << 15); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL2); - data32 &= ~((0x7 << 20) | (0xf << 8)); - data32 |= ((preem << 20) | - (rinner_table[ext_pullup] << 8)); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + if (lcd_drv->lcd_status & LCD_STATUS_IF_ON) + lcd_vbyone_phy_set(pconf, 1); LCDPR("%s: vswing=0x%x, preemphasis=0x%x\n", __func__, para[0], para[1]); @@ -3606,34 +3555,11 @@ static void lcd_phy_config_update(unsigned int *para, int cnt) break; case LCD_MLVDS: if (cnt >= 2) { - if ((para[0] > 7) || (para[1] > 3)) { - LCDERR("%s: wrong value:\n", __func__); - pr_info("vswing=%d, preemphasis=%d\n", - para[0], para[1]); - return; - } - pconf->lcd_control.mlvds_config->phy_vswing = para[0]; pconf->lcd_control.mlvds_config->phy_preem = para[1]; - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL1); - data32 &= ~((0x7 << 3) | (0x7 << 0) | (0x3 << 23)); - data32 |= ((para[0] << 3) | (para[0] << 0) | - (para[1] << 23)); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL2); - data32 &= ~((0x3 << 14) | (0x3 << 12) | - (0x3 << 26) | (0x3 << 24)); - data32 |= ((para[1] << 14) | (para[1] << 12) | - (para[1] << 26) | (para[1] << 24)); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL3); - data32 &= ~((0x3 << 6) | (0x3 << 4) | - (0x3 << 2) | (0x3 << 0) | (0x3 << 30)); - data32 |= ((para[1] << 6) | (para[1] << 4) | - (para[1] << 2) | (para[1] << 0) | - (para[1] << 30)); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + if (lcd_drv->lcd_status & LCD_STATUS_IF_ON) + lcd_mlvds_phy_set(pconf, 1); LCDPR("%s: vswing=0x%x, preemphasis=0x%x\n", __func__, para[0], para[1]); @@ -3644,34 +3570,11 @@ static void lcd_phy_config_update(unsigned int *para, int cnt) break; case LCD_P2P: if (cnt >= 2) { - if ((para[0] > 7) || (para[1] > 3)) { - LCDERR("%s: wrong value:\n", __func__); - pr_info("vswing=%d, preemphasis=%d\n", - para[0], para[1]); - return; - } - pconf->lcd_control.p2p_config->phy_vswing = para[0]; pconf->lcd_control.p2p_config->phy_preem = para[1]; - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL1); - data32 &= ~((0x7 << 3) | (0x7 << 0) | (0x3 << 23)); - data32 |= ((para[0] << 3) | (para[0] << 0) | - (para[1] << 23)); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL2); - data32 &= ~((0x3 << 14) | (0x3 << 12) | - (0x3 << 26) | (0x3 << 24)); - data32 |= ((para[1] << 14) | (para[1] << 12) | - (para[1] << 26) | (para[1] << 24)); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); - data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL3); - data32 &= ~((0x3 << 6) | (0x3 << 4) | - (0x3 << 2) | (0x3 << 0) | (0x3 << 30)); - data32 |= ((para[1] << 6) | (para[1] << 4) | - (para[1] << 2) | (para[1] << 0) | - (para[1] << 30)); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + if (lcd_drv->lcd_status & LCD_STATUS_IF_ON) + lcd_p2p_phy_set(pconf, 1); LCDPR("%s: vswing=0x%x, preemphasis=0x%x\n", __func__, para[0], para[1]); @@ -3682,7 +3585,8 @@ static void lcd_phy_config_update(unsigned int *para, int cnt) break; default: LCDERR("%s: not support lcd_type: %s\n", - __func__, lcd_type_type_to_str(type)); + __func__, + lcd_type_type_to_str(pconf->lcd_basic.lcd_type)); break; } } diff --git a/drivers/amlogic/media/vout/lcd/lcd_phy_config.c b/drivers/amlogic/media/vout/lcd/lcd_phy_config.c new file mode 100644 index 0000000..ad9ac39 --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_phy_config.c @@ -0,0 +1,554 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_phy_config.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lcd_reg.h" +#include "lcd_phy_config.h" +#include "lcd_common.h" + +static unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf) +{ + unsigned int channel_on = 0; + + if (pconf->lcd_control.lvds_config->dual_port == 0) { + if (pconf->lcd_control.lvds_config->lane_reverse == 0) { + switch (pconf->lcd_basic.lcd_bits) { + case 6: + channel_on = 0xf; + break; + case 8: + channel_on = 0x1f; + break; + case 10: + default: + channel_on = 0x3f; + break; + } + } else { + switch (pconf->lcd_basic.lcd_bits) { + case 6: + channel_on = 0x3c; + break; + case 8: + channel_on = 0x3e; + break; + case 10: + default: + channel_on = 0x3f; + break; + } + } + if (pconf->lcd_control.lvds_config->port_swap == 1) + channel_on = (channel_on << 6); /* use channel B */ + } else { + if (pconf->lcd_control.lvds_config->lane_reverse == 0) { + switch (pconf->lcd_basic.lcd_bits) { + case 6: + channel_on = 0x3cf; + break; + case 8: + channel_on = 0x7df; + break; + case 10: + default: + channel_on = 0xfff; + break; + } + } else { + switch (pconf->lcd_basic.lcd_bits) { + case 6: + channel_on = 0xf3c; + break; + case 8: + channel_on = 0xfbe; + break; + case 10: + default: + channel_on = 0xfff; + break; + } + } + } + return channel_on; +} + +void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status) +{ + unsigned int vswing, preem, clk_vswing, clk_preem, channel_on; + unsigned int data32, size; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lvds_config_s *lvds_conf; + + if (lcd_debug_print_flag) + LCDPR("%s: %d\n", __func__, status); + + lvds_conf = pconf->lcd_control.lvds_config; + if (status) { + vswing = lvds_conf->phy_vswing & 0xf; + preem = lvds_conf->phy_preem & 0xf; + clk_vswing = lvds_conf->phy_clk_vswing & 0xf; + clk_preem = lvds_conf->phy_clk_preem & 0xf; + if (lcd_debug_print_flag) + LCDPR("vswing=0x%x, prrem=0x%x\n", vswing, preem); + + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + size = sizeof(lvds_vx1_p2p_phy_preem_tl1) / + sizeof(unsigned int); + if (preem >= size) { + LCDERR("%s: invalid preem=0x%x, use default\n", + __func__, preem); + preem = 0; + } + data32 = lvds_vx1_p2p_phy_preem_tl1[preem]; + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, + 0xff2027e0 | vswing); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32); + break; + default: + if (vswing > 7) { + LCDERR("%s: invalid vswing=0x%x, use default\n", + __func__, vswing); + vswing = LVDS_PHY_VSWING_DFT; + } + if (preem > 7) { + LCDERR("%s: invalid preem=0x%x, use default\n", + __func__, preem); + preem = LVDS_PHY_PREEM_DFT; + } + if (clk_vswing > 3) { + LCDERR( + "%s: invalid clk_vswing=0x%x, use default\n", + __func__, clk_vswing); + clk_vswing = LVDS_PHY_CLK_VSWING_DFT; + } + if (clk_preem > 7) { + LCDERR( + "%s: invalid clk_preem=0x%x, use default\n", + __func__, clk_preem); + clk_preem = LVDS_PHY_CLK_PREEM_DFT; + } + channel_on = lcd_lvds_channel_on_value(pconf); + + data32 = LVDS_PHY_CNTL1_G9TV | + (vswing << 26) | (preem << 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + data32 = LVDS_PHY_CNTL2_G9TV; + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + data32 = LVDS_PHY_CNTL3_G9TV | + (channel_on << 16) | + (clk_vswing << 8) | + (clk_preem << 5); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + break; + } + } else { + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0); + break; + default: + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); + break; + } + } +} + +void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status) +{ + unsigned int vswing, preem, ext_pullup; + unsigned int data32, size; + unsigned int rinner_table[] = {0xa, 0xa, 0x6, 0x4}; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct vbyone_config_s *vbyone_conf; + + if (lcd_debug_print_flag) + LCDPR("%s: %d\n", __func__, status); + + vbyone_conf = pconf->lcd_control.vbyone_config; + if (status) { + ext_pullup = (vbyone_conf->phy_vswing >> 4) & 0x3; + vswing = vbyone_conf->phy_vswing & 0xf; + preem = vbyone_conf->phy_preem & 0xf; + if (lcd_debug_print_flag) { + LCDPR("vswing=0x%x, prrem=0x%x\n", + vbyone_conf->phy_vswing, preem); + } + + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + size = sizeof(lvds_vx1_p2p_phy_preem_tl1) / + sizeof(unsigned int); + if (preem >= size) { + LCDERR("%s: invalid preem=0x%x, use default\n", + __func__, preem); + preem = 0x1; + } + data32 = lvds_vx1_p2p_phy_preem_tl1[preem]; + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, + 0xf02027a0 | vswing); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32); + break; + default: + if (vswing > 7) { + LCDERR("%s: invalid vswing=0x%x, use default\n", + __func__, vswing); + vswing = VX1_PHY_VSWING_DFT; + } + if (preem > 7) { + LCDERR("%s: invalid preem=0x%x, use default\n", + __func__, preem); + preem = VX1_PHY_PREEM_DFT; + } + if (ext_pullup) { + data32 = VX1_PHY_CNTL1_G9TV_PULLUP | + (vswing << 3); + } else { + data32 = VX1_PHY_CNTL1_G9TV | (vswing << 3); + } + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + data32 = VX1_PHY_CNTL2_G9TV | (preem << 20) | + (rinner_table[ext_pullup] << 8); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + data32 = VX1_PHY_CNTL3_G9TV; + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + break; + } + } else { + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0); + break; + default: + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); + break; + } + } +} + +void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status) +{ + unsigned int vswing, preem; + unsigned int data32, size; + struct mlvds_config_s *mlvds_conf; + + if (lcd_debug_print_flag) + LCDPR("%s: %d\n", __func__, status); + + mlvds_conf = pconf->lcd_control.mlvds_config; + if (status) { + vswing = mlvds_conf->phy_vswing & 0xf; + preem = mlvds_conf->phy_preem & 0xf; + if (lcd_debug_print_flag) + LCDPR("vswing=0x%x, prrem=0x%x\n", vswing, preem); + + size = sizeof(lvds_vx1_p2p_phy_preem_tl1) / + sizeof(unsigned int); + if (preem >= size) { + LCDERR("%s: invalid preem=0x%x, use default\n", + __func__, preem); + preem = 0; + } + data32 = lvds_vx1_p2p_phy_preem_tl1[preem]; + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, + 0xff2027e0 | vswing); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32); + } else { + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0); + } +} + +void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status) +{ + unsigned int vswing, preem; + unsigned int data32, size, cntl16; + struct p2p_config_s *p2p_conf; + + if (lcd_debug_print_flag) + LCDPR("%s: %d\n", __func__, status); + + p2p_conf = pconf->lcd_control.p2p_config; + if (status) { + vswing = p2p_conf->phy_vswing & 0xf; + preem = p2p_conf->phy_preem & 0xf; + if (lcd_debug_print_flag) + LCDPR("vswing=0x%x, prrem=0x%x\n", vswing, preem); + + switch (p2p_conf->p2p_type) { + case P2P_CEDS: + case P2P_CMPI: + case P2P_ISP: + case P2P_EPI: + size = sizeof(lvds_vx1_p2p_phy_preem_tl1) / + sizeof(unsigned int); + if (preem >= size) { + LCDERR("%s: invalid preem=0x%x, use default\n", + __func__, preem); + preem = 0x1; + } + data32 = lvds_vx1_p2p_phy_preem_tl1[preem]; + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, + 0xff2027a0 | vswing); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32); + break; + case P2P_CHPI: /* low common mode */ + case P2P_CSPI: + case P2P_USIT: + size = sizeof(p2p_low_common_phy_preem_tl1) / + sizeof(unsigned int); + if (preem >= size) { + LCDERR("%s: invalid preem=0x%x, use default\n", + __func__, preem); + preem = 0x1; + } + data32 = p2p_low_common_phy_preem_tl1[preem]; + if (p2p_conf->p2p_type == P2P_CHPI) { + /* cntl[30]=1, weakly pull down */ + cntl16 = 0x80000000; + } else { + cntl16 = 0x80000000; + } + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0xfe60027f); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, cntl16); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32); + break; + default: + LCDERR("%s: invalid p2p_type %d\n", + __func__, p2p_conf->p2p_type); + break; + } + } else { + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0); + } +} + +void lcd_mipi_phy_set(struct lcd_config_s *pconf, int status) +{ + unsigned int phy_reg, phy_bit, phy_width; + unsigned int lane_cnt; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + if (status) { + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_G12A: + case LCD_CHIP_G12B: + /* HHI_MIPI_CNTL0 */ + /* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */ + lcd_hiu_write(HHI_MIPI_CNTL0, + (0xa487 << 16) | (0x8 << 0)); + + /* HHI_MIPI_CNTL1 */ + /* DIF_REF_CTL2:15-0bit; bandgap bit16 */ + lcd_hiu_write(HHI_MIPI_CNTL1, + (0x1 << 16) | (0x002e << 0)); + + /* HHI_MIPI_CNTL2 */ + /* DIF_TX_CTL1:31-16bit, DIF_TX_CTL0:15-0bit */ + lcd_hiu_write(HHI_MIPI_CNTL2, + (0x2680 << 16) | (0x45a << 0)); + break; + default: /* LCD_CHIP_AXG */ + /* HHI_MIPI_CNTL0 */ + /* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */ + lcd_hiu_setb(HHI_MIPI_CNTL0, 0x1b8, 16, 10); + lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 26, 1); /* bandgap */ + lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 29, 1); /* current */ + lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 31, 1); + lcd_hiu_setb(HHI_MIPI_CNTL0, 0x8, 0, 16); + + /* HHI_MIPI_CNTL1 */ + /* DIF_REF_CTL2:15-0bit */ + lcd_hiu_write(HHI_MIPI_CNTL1, (0x001e << 0)); + + /* HHI_MIPI_CNTL2 */ + /* DIF_TX_CTL1:31-16bit, DIF_TX_CTL0:15-0bit */ + lcd_hiu_write(HHI_MIPI_CNTL2, + (0x26e0 << 16) | (0x459 << 0)); + break; + } + + phy_reg = HHI_MIPI_CNTL2; + phy_bit = MIPI_PHY_LANE_BIT; + phy_width = MIPI_PHY_LANE_WIDTH; + switch (pconf->lcd_control.mipi_config->lane_num) { + case 1: + lane_cnt = DSI_LANE_COUNT_1; + break; + case 2: + lane_cnt = DSI_LANE_COUNT_2; + break; + case 3: + lane_cnt = DSI_LANE_COUNT_3; + break; + case 4: + lane_cnt = DSI_LANE_COUNT_4; + break; + default: + lane_cnt = 0; + break; + } + lcd_hiu_setb(phy_reg, lane_cnt, phy_bit, phy_width); + } else { + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_G12A: + case LCD_CHIP_G12B: + lcd_hiu_write(HHI_MIPI_CNTL0, 0); + lcd_hiu_write(HHI_MIPI_CNTL1, 0); + lcd_hiu_write(HHI_MIPI_CNTL2, 0); + break; + default:/* LCD_CHIP_AXG */ + lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 16, 10); + lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 31, 1); + lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 0, 16); + lcd_hiu_write(HHI_MIPI_CNTL1, 0x6); + lcd_hiu_write(HHI_MIPI_CNTL2, 0x00200000); + break; + } + } +} diff --git a/drivers/amlogic/media/vout/lcd/lcd_phy_config.h b/drivers/amlogic/media/vout/lcd/lcd_phy_config.h new file mode 100644 index 0000000..3ed875e --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_phy_config.h @@ -0,0 +1,87 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_phy_config.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AML_LCD_PHY_CONFIG_H__ +#define __AML_LCD_PHY_CONFIG_H__ + +/* -------------------------- */ +/* lvsd phy parameters define */ +/* -------------------------- */ +#define LVDS_PHY_CNTL1_G9TV 0x606cca80 +#define LVDS_PHY_CNTL2_G9TV 0x0000006c +#define LVDS_PHY_CNTL3_G9TV 0x00000800 + +#define LVDS_PHY_CNTL1_TXHD 0x6c60ca80 +#define LVDS_PHY_CNTL2_TXHD 0x00000070 +#define LVDS_PHY_CNTL3_TXHD 0x03ff0c00 +/* -------------------------- */ + +/* -------------------------- */ +/* vbyone phy parameters define */ +/* -------------------------- */ +#define VX1_PHY_CNTL1_G9TV 0x6e0ec900 +#define VX1_PHY_CNTL1_G9TV_PULLUP 0x6e0f4d00 +#define VX1_PHY_CNTL2_G9TV 0x0000007c +#define VX1_PHY_CNTL3_G9TV 0x00ff0800 +/* -------------------------- */ + +/* -------------------------- */ +/* minilvds phy parameters define */ +/* -------------------------- */ +#define MLVDS_PHY_CNTL1_TXHD 0x6c60ca80 +#define MLVDS_PHY_CNTL2_TXHD 0x00000070 +#define MLVDS_PHY_CNTL3_TXHD 0x03ff0c00 +/* -------------------------- */ + +/* ******** MIPI_DSI_PHY ******** */ +/* bit[15:11] */ +#define MIPI_PHY_LANE_BIT 11 +#define MIPI_PHY_LANE_WIDTH 5 + +/* MIPI-DSI */ +#define DSI_LANE_0 (1 << 4) +#define DSI_LANE_1 (1 << 3) +#define DSI_LANE_CLK (1 << 2) +#define DSI_LANE_2 (1 << 1) +#define DSI_LANE_3 (1 << 0) +#define DSI_LANE_COUNT_1 (DSI_LANE_CLK | DSI_LANE_0) +#define DSI_LANE_COUNT_2 (DSI_LANE_CLK | DSI_LANE_0 | DSI_LANE_1) +#define DSI_LANE_COUNT_3 (DSI_LANE_CLK | DSI_LANE_0 |\ + DSI_LANE_1 | DSI_LANE_2) +#define DSI_LANE_COUNT_4 (DSI_LANE_CLK | DSI_LANE_0 |\ + DSI_LANE_1 | DSI_LANE_2 | DSI_LANE_3) + +static unsigned int lvds_vx1_p2p_phy_preem_tl1[] = { + 0x06020602, + 0x26022602, + 0x46024602, + 0x66026602, + 0x86028602, + 0xa602a602, + 0xf602f602, +}; + +static unsigned int p2p_low_common_phy_preem_tl1[] = { + 0x070b070b, + 0x170b170b, + 0x370b370b, + 0x770b770b, + 0xf70bf70b, + 0xff0bff0b, +}; + +#endif diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c index da26d57..e55447a 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c @@ -60,184 +60,6 @@ static int lcd_type_supported(struct lcd_config_s *pconf) return ret; } -static void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status) -{ - unsigned int vswing, preem, clk_vswing, clk_preem, channel_on; - unsigned int data32; - - if (lcd_debug_print_flag) - LCDPR("%s: %d\n", __func__, status); - - if (status) { - vswing = pconf->lcd_control.lvds_config->phy_vswing; - preem = pconf->lcd_control.lvds_config->phy_preem; - clk_vswing = pconf->lcd_control.lvds_config->phy_clk_vswing; - clk_preem = pconf->lcd_control.lvds_config->phy_clk_preem; - if (vswing > 7) { - LCDERR("%s: wrong vswing_level=%d, use default\n", - __func__, vswing); - vswing = LVDS_PHY_VSWING_DFT; - } - channel_on = lcd_lvds_channel_on_value(pconf); - - if (preem > 7) { - LCDERR("%s: wrong preem=%d, use default\n", - __func__, preem); - preem = LVDS_PHY_PREEM_DFT; - } - if (clk_vswing > 3) { - LCDERR("%s: wrong clk_vswing=%d, use default\n", - __func__, clk_vswing); - clk_vswing = LVDS_PHY_CLK_VSWING_DFT; - } - if (clk_preem > 7) { - LCDERR("%s: wrong clk_preem=%d, use default\n", - __func__, clk_preem); - clk_preem = LVDS_PHY_CLK_PREEM_DFT; - } - - data32 = LVDS_PHY_CNTL1_G9TV | - (vswing << 26) | (preem << 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); - data32 = LVDS_PHY_CNTL2_G9TV; - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); - data32 = LVDS_PHY_CNTL3_G9TV | - (channel_on << 16) | - (clk_vswing << 8) | (clk_preem << 5); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); - } else { - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); - } -} - -static void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status) -{ - unsigned int vswing, preem, ext_pullup; - unsigned int data32; - unsigned int rinner_table[] = {0xa, 0xa, 0x6, 0x4}; - - if (lcd_debug_print_flag) - LCDPR("%s: %d\n", __func__, status); - - if (status) { - ext_pullup = (pconf->lcd_control.vbyone_config->phy_vswing >> 4) - & 0x3; - vswing = pconf->lcd_control.vbyone_config->phy_vswing & 0xf; - preem = pconf->lcd_control.vbyone_config->phy_preem; - if (vswing > 7) { - LCDERR("%s: wrong vswing_level=%d, use default\n", - __func__, vswing); - vswing = VX1_PHY_VSWING_DFT; - } - if (preem > 7) { - LCDERR("%s: wrong preemphasis_level=%d, use default\n", - __func__, preem); - preem = VX1_PHY_PREEM_DFT; - } - if (ext_pullup) - data32 = VX1_PHY_CNTL1_G9TV_PULLUP | (vswing << 3); - else - data32 = VX1_PHY_CNTL1_G9TV | (vswing << 3); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); - data32 = VX1_PHY_CNTL2_G9TV | (preem << 20) | - (rinner_table[ext_pullup] << 8); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); - data32 = VX1_PHY_CNTL3_G9TV; - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); - } else { - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); - } -} - -static void lcd_mipi_phy_set(struct lcd_config_s *pconf, int status) -{ - unsigned int phy_reg, phy_bit, phy_width; - unsigned int lane_cnt; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - - if (status) { - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - /* HHI_MIPI_CNTL0 */ - /* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */ - lcd_hiu_write(HHI_MIPI_CNTL0, - (0xa487 << 16) | (0x8 << 0)); - - /* HHI_MIPI_CNTL1 */ - /* DIF_REF_CTL2:15-0bit */ - lcd_hiu_write(HHI_MIPI_CNTL1, - (0x1 << 16) | (0x002e << 0)); - - /* HHI_MIPI_CNTL2 */ - /* DIF_TX_CTL1:31-16bit, DIF_TX_CTL0:15-0bit */ - lcd_hiu_write(HHI_MIPI_CNTL2, - (0x2680 << 16) | (0x45a << 0)); - break; - default: /* LCD_CHIP_AXG */ - /* HHI_MIPI_CNTL0 */ - /* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */ - lcd_hiu_setb(HHI_MIPI_CNTL0, 0x1b8, 16, 10); - lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 26, 1); /* bandgap */ - lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 29, 1); /* current */ - lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 31, 1); - lcd_hiu_setb(HHI_MIPI_CNTL0, 0x8, 0, 16); - - /* HHI_MIPI_CNTL1 */ - /* DIF_REF_CTL2:15-0bit */ - lcd_hiu_write(HHI_MIPI_CNTL1, (0x001e << 0)); - - /* HHI_MIPI_CNTL2 */ - /* DIF_TX_CTL1:31-16bit, DIF_TX_CTL0:15-0bit */ - lcd_hiu_write(HHI_MIPI_CNTL2, - (0x26e0 << 16) | (0xfc59 << 0)); - break; - } - - phy_reg = HHI_MIPI_CNTL2; - phy_bit = MIPI_PHY_LANE_BIT; - phy_width = MIPI_PHY_LANE_WIDTH; - switch (pconf->lcd_control.mipi_config->lane_num) { - case 1: - lane_cnt = DSI_LANE_COUNT_1; - break; - case 2: - lane_cnt = DSI_LANE_COUNT_2; - break; - case 3: - lane_cnt = DSI_LANE_COUNT_3; - break; - case 4: - lane_cnt = DSI_LANE_COUNT_4; - break; - default: - lane_cnt = 0; - break; - } - lcd_hiu_setb(phy_reg, lane_cnt, phy_bit, phy_width); - } else { - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - lcd_hiu_write(HHI_MIPI_CNTL0, 0); - lcd_hiu_write(HHI_MIPI_CNTL1, 0); - lcd_hiu_write(HHI_MIPI_CNTL2, 0); - break; - default:/* LCD_CHIP_AXG */ - lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 16, 10); - lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 31, 1); - lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 0, 16); - lcd_hiu_write(HHI_MIPI_CNTL1, 0x6); - lcd_hiu_write(HHI_MIPI_CNTL2, 0x00200000); - break; - } - } -} - static void lcd_encl_tcon_set(struct lcd_config_s *pconf) { struct lcd_timing_s *tcon_adr = &pconf->lcd_timing; diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c index 8f85c3f..89b6e7a 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c @@ -73,277 +73,6 @@ static int lcd_type_supported(struct lcd_config_s *pconf) return ret; } -static void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status) -{ - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - unsigned int vswing, preem, ext_pullup; - unsigned int data32; - unsigned int rinner_table[] = {0xa, 0xa, 0x6, 0x4}; - - if (lcd_debug_print_flag) - LCDPR("%s: %d\n", __func__, status); - - if (status) { - ext_pullup = (pconf->lcd_control.vbyone_config->phy_vswing >> 4) - & 0x3; - vswing = pconf->lcd_control.vbyone_config->phy_vswing & 0xf; - preem = pconf->lcd_control.vbyone_config->phy_preem; - if (vswing > 7) { - LCDERR("%s: wrong vswing_level=%d, use default\n", - __func__, vswing); - vswing = VX1_PHY_VSWING_DFT; - } - if (preem > 7) { - LCDERR("%s: wrong preemphasis_level=%d, use default\n", - __func__, preem); - preem = VX1_PHY_PREEM_DFT; - } - - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_TL1: - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0xf02027af); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x26022602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x26022602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x26022602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0x26022602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0x26022602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0x26022602); - break; - default: - if (ext_pullup) { - data32 = VX1_PHY_CNTL1_G9TV_PULLUP | - (vswing << 3); - } else { - data32 = VX1_PHY_CNTL1_G9TV | (vswing << 3); - } - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); - data32 = VX1_PHY_CNTL2_G9TV | (preem << 20) | - (rinner_table[ext_pullup] << 8); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); - data32 = VX1_PHY_CNTL3_G9TV; - /*lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x00000a7c);*/ - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); - break; - } - } else { - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_TL1: - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0); - break; - default: - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); - break; - } - } -} - -static void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status) -{ - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - unsigned int vswing, preem, clk_vswing, clk_preem, channel_on; - unsigned int data32; - - if (lcd_debug_print_flag) - LCDPR("%s: %d\n", __func__, status); - - if (status) { - vswing = pconf->lcd_control.lvds_config->phy_vswing; - preem = pconf->lcd_control.lvds_config->phy_preem; - clk_vswing = pconf->lcd_control.lvds_config->phy_clk_vswing; - clk_preem = pconf->lcd_control.lvds_config->phy_clk_preem; - if (vswing > 7) { - LCDERR("%s: wrong vswing=%d, use default\n", - __func__, vswing); - vswing = LVDS_PHY_VSWING_DFT; - } - channel_on = lcd_lvds_channel_on_value(pconf); - - if (preem > 7) { - LCDERR("%s: wrong preem=%d, use default\n", - __func__, preem); - preem = LVDS_PHY_PREEM_DFT; - } - if (clk_vswing > 3) { - LCDERR("%s: wrong clk_vswing=%d, use default\n", - __func__, clk_vswing); - clk_vswing = LVDS_PHY_CLK_VSWING_DFT; - } - if (clk_preem > 7) { - LCDERR("%s: wrong clk_preem=%d, use default\n", - __func__, clk_preem); - clk_preem = LVDS_PHY_CLK_PREEM_DFT; - } - - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_TL1: - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0xff2027ef); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x06020602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x06020602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x06020602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0x06020602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0x06020602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0x06020602); - break; - default: - data32 = LVDS_PHY_CNTL1_G9TV | - (vswing << 26) | (preem << 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); - data32 = LVDS_PHY_CNTL2_G9TV; - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); - data32 = LVDS_PHY_CNTL3_G9TV | - (channel_on << 16) | - (clk_vswing << 8) | (clk_preem << 5); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); - break; - } - } else { - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_TL1: - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0); - break; - default: - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); - break; - } - } -} - -static void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status) -{ - unsigned int vswing, preem; - unsigned int data32; - - if (lcd_debug_print_flag) - LCDPR("%s: %d\n", __func__, status); - - if (status) { - vswing = pconf->lcd_control.mlvds_config->phy_vswing; - preem = pconf->lcd_control.mlvds_config->phy_preem; - if (vswing > 7) { - LCDERR("%s: wrong vswing_level=%d, use default\n", - __func__, vswing); - vswing = LVDS_PHY_VSWING_DFT; - } - if (preem > 3) { - LCDERR("%s: wrong preemphasis_level=%d, use default\n", - __func__, preem); - preem = LVDS_PHY_PREEM_DFT; - } - - data32 = MLVDS_PHY_CNTL1_TL1 | - (vswing << 3) | (vswing << 0) | (preem << 23); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); - data32 = MLVDS_PHY_CNTL2_TL1 | - (preem << 14) | (preem << 12) | - (preem << 26) | (preem << 24); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); - data32 = MLVDS_PHY_CNTL3_TL1 | - (preem << 6) | (preem << 4) | - (preem << 2) | (preem << 0) | (preem << 30); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); - } else { - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); - } -} - -static void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status) -{ - if (lcd_debug_print_flag) - LCDPR("%s: %d\n", __func__, status); - - if (status) { - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0xff2027af); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x06020602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x06020602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x06020602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0x06020602); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); - switch (pconf->lcd_control.p2p_config->p2p_type) { - case P2P_CHPI: - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0x06020602); - lcd_hiu_setb(HHI_DIF_CSI_PHY_CNTL6, 1, 30, 1); - break; - default: - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0x06020602); - break; - } - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0x06020602); - } else { - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0); - lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0); - } -} - static void lcd_encl_tcon_set(struct lcd_config_s *pconf) { unsigned int lcd_bits; -- 2.7.4