From 52d631dcc70144b6ce8293db78cd6de635331c83 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Tue, 27 Mar 2012 16:41:55 +0100 Subject: [PATCH] PPC: Fix TLB invalidation bug within the PPC interrupt handler. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR bits at the start of the interrupt handler, the logic towards the end of the handler to force a TLB flush if either one of these bits were set would never be triggered. This patch simply changes the IR/DR bit check in the TLB flush logic to use the original MSR value (albeit with some interrupt-specific bits cleared) so that the IR/DR bits are preserved at the point where the check takes place. Signed-off-by: Mark Cave-Ayland Acked-by: David Gibson Signed-off-by: Andreas Färber --- target-ppc/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/helper.c b/target-ppc/helper.c index e13b749..f0ea1c3 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2960,7 +2960,7 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) if (asrr1 != -1) env->spr[asrr1] = env->spr[srr1]; /* If we disactivated any translation, flush TLBs */ - if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) + if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) tlb_flush(env, 1); if (msr_ile) { -- 2.7.4