From 52a779762688dee1a6042dc41f35e1f7a7048b85 Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Wed, 19 May 2021 09:02:27 -0400 Subject: [PATCH] Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542 --- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 4 - llvm/include/llvm/Target/GlobalISel/Combine.td | 9 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 53 - llvm/lib/Target/AArch64/AArch64Combine.td | 3 +- ...izer-combiner-icmp-to-true-false-known-bits.mir | 575 ------ llvm/test/CodeGen/AArch64/fold-global-offsets.ll | 17 +- .../CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 104 +- llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 1910 ++++++++++++----- llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 2183 +++++++++++++------- llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 2110 ++++++++++++------- llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll | 88 +- llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll | 112 +- llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 1426 +++++++++---- llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll | 1866 ++++++++--------- llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll | 1012 ++++----- 15 files changed, 6742 insertions(+), 4730 deletions(-) delete mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h index 93ec4de..f931930 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h @@ -513,10 +513,6 @@ public: bool matchRotateOutOfRange(MachineInstr &MI); void applyRotateOutOfRange(MachineInstr &MI); - /// \returns true if a G_ICMP instruction \p MI can be replaced with a true - /// or false constant based off of KnownBits information. - bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo); - /// Try to transform \p MI by using all of the above /// combine functions. Returns true if changed. bool tryCombine(MachineInstr &MI); diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td index b230385..3c28faa 100644 --- a/llvm/include/llvm/Target/GlobalISel/Combine.td +++ b/llvm/include/llvm/Target/GlobalISel/Combine.td @@ -114,7 +114,6 @@ class GIApplyKind; class GIApplyKindWithArgs; def register_matchinfo: GIDefMatchData<"Register">; -def int64_matchinfo: GIDefMatchData<"int64_t">; def build_fn_matchinfo : GIDefMatchData<"std::function">; @@ -614,12 +613,6 @@ def rotate_out_of_range : GICombineRule< (apply [{ Helper.applyRotateOutOfRange(*${root}); }]) >; -def icmp_to_true_false_known_bits : GICombineRule< - (defs root:$d, int64_matchinfo:$matchinfo), - (match (wip_match_opcode G_ICMP):$d, - [{ return Helper.matchICmpToTrueFalseKnownBits(*${d}, ${matchinfo}); }]), - (apply [{ Helper.replaceInstWithConstant(*${d}, ${matchinfo}); }])>; - def funnel_shift_combines : GICombineGroup<[funnel_shift_to_rotate]>; // FIXME: These should use the custom predicate feature once it lands. @@ -641,7 +634,7 @@ def const_combines : GICombineGroup<[constant_fp_op, const_ptradd_to_i2p]>; def known_bits_simplifications : GICombineGroup<[ redundant_and, redundant_sext_inreg, redundant_or, urem_pow2_to_mask, - zext_trunc_fold, icmp_to_true_false_known_bits]>; + zext_trunc_fold]>; def width_reduction_combines : GICombineGroup<[reduce_shl_of_extend]>; diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index 29c3b89..5d0f63a 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -3926,59 +3926,6 @@ void CombinerHelper::applyRotateOutOfRange(MachineInstr &MI) { Observer.changedInstr(MI); } -bool CombinerHelper::matchICmpToTrueFalseKnownBits(MachineInstr &MI, - int64_t &MatchInfo) { - assert(MI.getOpcode() == TargetOpcode::G_ICMP); - auto Pred = static_cast(MI.getOperand(1).getPredicate()); - auto KnownLHS = KB->getKnownBits(MI.getOperand(2).getReg()); - auto KnownRHS = KB->getKnownBits(MI.getOperand(3).getReg()); - Optional KnownVal; - switch (Pred) { - default: - llvm_unreachable("Unexpected G_ICMP predicate?"); - case CmpInst::ICMP_EQ: - KnownVal = KnownBits::eq(KnownLHS, KnownRHS); - break; - case CmpInst::ICMP_NE: - KnownVal = KnownBits::ne(KnownLHS, KnownRHS); - break; - case CmpInst::ICMP_SGE: - KnownVal = KnownBits::sge(KnownLHS, KnownRHS); - break; - case CmpInst::ICMP_SGT: - KnownVal = KnownBits::sgt(KnownLHS, KnownRHS); - break; - case CmpInst::ICMP_SLE: - KnownVal = KnownBits::sle(KnownLHS, KnownRHS); - break; - case CmpInst::ICMP_SLT: - KnownVal = KnownBits::slt(KnownLHS, KnownRHS); - break; - case CmpInst::ICMP_UGE: - KnownVal = KnownBits::uge(KnownLHS, KnownRHS); - break; - case CmpInst::ICMP_UGT: - KnownVal = KnownBits::ugt(KnownLHS, KnownRHS); - break; - case CmpInst::ICMP_ULE: - KnownVal = KnownBits::ule(KnownLHS, KnownRHS); - break; - case CmpInst::ICMP_ULT: - KnownVal = KnownBits::ult(KnownLHS, KnownRHS); - break; - } - if (!KnownVal) - return false; - MatchInfo = - *KnownVal - ? getICmpTrueVal(getTargetLowering(), - /*IsVector = */ - MRI.getType(MI.getOperand(0).getReg()).isVector(), - /* IsFP = */ false) - : 0; - return true; -} - bool CombinerHelper::tryCombine(MachineInstr &MI) { if (tryCombineCopy(MI)) return true; diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td index fa4b88d..54e8959 100644 --- a/llvm/lib/Target/AArch64/AArch64Combine.td +++ b/llvm/lib/Target/AArch64/AArch64Combine.td @@ -210,7 +210,6 @@ def AArch64PostLegalizerCombinerHelper redundant_and, xor_of_and_with_same_reg, extractvecelt_pairwise_add, redundant_or, mul_const, redundant_sext_inreg, - form_bitfield_extract, rotate_out_of_range, - icmp_to_true_false_known_bits]> { + form_bitfield_extract, rotate_out_of_range]> { let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule"; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir deleted file mode 100644 index ed6a331..0000000 --- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir +++ /dev/null @@ -1,575 +0,0 @@ -# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -debugify-and-strip-all-safe -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombinerhelper-only-enable-rule="icmp_to_true_false_known_bits" -global-isel -verify-machineinstrs %s -o - | FileCheck %s - ---- | - define i1 @eq_true(i32* %ptr) { unreachable } - define i1 @ne_true(i32* %ptr) { unreachable } - define i1 @sge_true(i32* %ptr) { unreachable } - define i1 @sgt_true(i32* %ptr) { unreachable } - define i1 @sle_true(i32* %ptr) { unreachable } - define i1 @slt_true(i32* %ptr) { unreachable } - define i1 @uge_true(i32* %ptr) { unreachable } - define i1 @ugt_true(i32* %ptr) { unreachable } - define i1 @ule_true(i32* %ptr) { unreachable } - define i1 @ult_true(i32* %ptr) { unreachable } - - define i1 @eq_false(i32* %ptr) { unreachable } - define i1 @ne_false(i32* %ptr) { unreachable } - define i1 @sge_false(i32* %ptr) { unreachable } - define i1 @sgt_false(i32* %ptr) { unreachable } - define i1 @sle_false(i32* %ptr) { unreachable } - define i1 @slt_false(i32* %ptr) { unreachable } - define i1 @uge_false(i32* %ptr) { unreachable } - define i1 @ugt_false(i32* %ptr) { unreachable } - define i1 @ule_false(i32* %ptr) { unreachable } - define i1 @ult_false(i32* %ptr) { unreachable } - - define i1 @eq_unknown(i32* %ptr) { unreachable } - define i1 @ne_unknown(i32* %ptr) { unreachable } - - define i1 @vector_true(i32* %ptr) { unreachable } - define i1 @vector_false(i32* %ptr) { unreachable } - - !0 = !{i32 1, i32 2} - !1 = !{i32 1, i32 3} - -... ---- -name: eq_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: eq_true - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 1 - %cmp:_(s1) = G_ICMP intpred(eq), %cst(s32), %cst - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: ne_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: ne_true - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst_1:_(s32) = G_CONSTANT i32 1 - %cst_2:_(s32) = G_CONSTANT i32 2 - %cmp:_(s1) = G_ICMP intpred(ne), %cst_1(s32), %cst_2 - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: sge_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: sge_true - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 2 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(sge), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: sgt_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: sgt_true - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 3 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(sgt), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: sle_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: sle_true - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 1 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(sle), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - - -... ---- -name: slt_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: slt_true - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 -1 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(slt), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: uge_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: uge_true - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 2 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(uge), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: ugt_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: ugt_true - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 -1 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(ugt), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: ule_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: ule_true - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 1 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(ule), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: ult_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: ult_true - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 0 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(ule), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: eq_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: eq_false - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 0 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(eq), %load_eq_1(s32), %cst - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: ne_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: ne_false - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst_1:_(s32) = G_CONSTANT i32 1 - %cst_2:_(s32) = G_CONSTANT i32 1 - %cmp:_(s1) = G_ICMP intpred(ne), %cst_1(s32), %cst_2 - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: sge_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: sge_false - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 -1 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(sge), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: sgt_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: sgt_false - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 1 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(sgt), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: sle_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: sle_false - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 3 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(sle), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - - -... ---- -name: slt_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: slt_false - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 2 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(slt), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: uge_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: uge_false - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 0 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(uge), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: ugt_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: ugt_false - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 1 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(ugt), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: ule_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: ule_false - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 -1 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(ule), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: ult_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: ult_false - ; CHECK: liveins: $x0 - ; CHECK: %cmp:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 2 - %load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0) - %cmp:_(s1) = G_ICMP intpred(ule), %cst, %load_eq_1(s32) - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: eq_unknown -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: eq_unknown - ; CHECK: liveins: $x0 - ; CHECK: %ptr:_(p0) = COPY $x0 - ; CHECK: %cst:_(s32) = G_CONSTANT i32 1 - ; CHECK: %load_between_1_2:_(s32) = G_LOAD %ptr(p0) :: (load 4, - ; CHECK: %cmp:_(s1) = G_ICMP intpred(eq), %load_between_1_2(s32), %cst - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 1 - %load_between_1_2:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !1) - %cmp:_(s1) = G_ICMP intpred(eq), %load_between_1_2(s32), %cst - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: ne_unknown -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - - ; CHECK-LABEL: name: ne_unknown - ; CHECK: liveins: $x0 - ; CHECK: %ptr:_(p0) = COPY $x0 - ; CHECK: %cst:_(s32) = G_CONSTANT i32 1 - ; CHECK: %load_between_1_2:_(s32) = G_LOAD %ptr(p0) :: (load 4, - ; CHECK: %cmp:_(s1) = G_ICMP intpred(ne), %load_between_1_2(s32), %cst - ; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - ; CHECK: $w0 = COPY %cmp_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 1 - %load_between_1_2:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !1) - %cmp:_(s1) = G_ICMP intpred(ne), %load_between_1_2(s32), %cst - %cmp_ext:_(s32) = G_ZEXT %cmp(s1) - $w0 = COPY %cmp_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: vector_true -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - ; CHECK-LABEL: name: vector_true - ; CHECK: liveins: $x0 - ; CHECK: %cst:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1) - ; CHECK: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) - ; CHECK: %extract_ext:_(s32) = G_ZEXT %extract(s1) - ; CHECK: $w0 = COPY %extract_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 1 - %bv:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst - %cmp:_(<2 x s1>) = G_ICMP intpred(eq), %bv(<2 x s32>), %bv - %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) - %extract_ext:_(s32) = G_ZEXT %extract(s1) - $w0 = COPY %extract_ext(s32) - RET_ReallyLR implicit $w0 - -... ---- -name: vector_false -tracksRegLiveness: true -body: | - bb.0: - liveins: $x0 - ; CHECK-LABEL: name: vector_false - ; CHECK: liveins: $x0 - ; CHECK: %cst:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1) - ; CHECK: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) - ; CHECK: %extract_ext:_(s32) = G_ZEXT %extract(s1) - ; CHECK: $w0 = COPY %extract_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 - %ptr:_(p0) = COPY $x0 - %cst:_(s32) = G_CONSTANT i32 1 - %bv:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst - %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %bv(<2 x s32>), %bv - %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) - %extract_ext:_(s32) = G_ZEXT %extract(s1) - $w0 = COPY %extract_ext(s32) - RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/fold-global-offsets.ll b/llvm/test/CodeGen/AArch64/fold-global-offsets.ll index 1cb891f..24168f9 100644 --- a/llvm/test/CodeGen/AArch64/fold-global-offsets.ll +++ b/llvm/test/CodeGen/AArch64/fold-global-offsets.ll @@ -134,14 +134,15 @@ define i32 @f7() { ; GISEL-NEXT: mov w9, #64 ; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: sub x8, x9, #64 // =64 -; GISEL-NEXT: fmov x10, d1 -; GISEL-NEXT: fmov x9, d0 -; GISEL-NEXT: lsl x11, x10, x8 -; GISEL-NEXT: lsr x8, x10, x8 -; GISEL-NEXT: orr x10, x11, x9, lsr #0 -; GISEL-NEXT: tst wzr, #0x1 -; GISEL-NEXT: csel x8, x10, x8, ne -; GISEL-NEXT: csel x8, x9, x8, ne +; GISEL-NEXT: fmov x11, d1 +; GISEL-NEXT: fmov x10, d0 +; GISEL-NEXT: lsl x12, x11, x8 +; GISEL-NEXT: cmp x9, #64 // =64 +; GISEL-NEXT: lsr x8, x11, x8 +; GISEL-NEXT: orr x11, x12, x10, lsr #0 +; GISEL-NEXT: csel x8, x11, x8, lo +; GISEL-NEXT: cmp x9, #0 // =0 +; GISEL-NEXT: csel x8, x10, x8, eq ; GISEL-NEXT: ldr w0, [x8, #20] ; GISEL-NEXT: ret diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll index a6c2ea7..d73f487 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll @@ -1137,64 +1137,72 @@ define float @v_test_sitofp_i64_byte_to_f32(i64 %arg0) { ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_movk_i32 s6, 0xff -; SI-NEXT: v_and_b32_e32 v0, s6, v0 -; SI-NEXT: v_add_i32_e32 v0, vcc, 0, v0 -; SI-NEXT: v_ffbh_u32_e32 v2, v0 -; SI-NEXT: v_addc_u32_e64 v1, s[4:5], 0, 0, vcc -; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v2 -; SI-NEXT: v_ffbh_u32_e32 v3, v1 -; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; SI-NEXT: v_mov_b32_e32 v3, 0xbe -; SI-NEXT: v_sub_i32_e32 v4, vcc, v3, v2 -; SI-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 -; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] -; SI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v3 -; SI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc -; SI-NEXT: v_and_b32_e32 v3, s6, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v1 -; SI-NEXT: v_lshlrev_b32_e32 v0, 23, v0 +; SI-NEXT: v_and_b32_e32 v2, s6, v0 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0, v2 +; SI-NEXT: v_ffbh_u32_e32 v4, v2 +; SI-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc +; SI-NEXT: v_add_i32_e32 v4, vcc, 32, v4 +; SI-NEXT: v_ffbh_u32_e32 v5, v3 +; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; SI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc +; SI-NEXT: v_mov_b32_e32 v5, 0xbe +; SI-NEXT: v_sub_i32_e32 v6, vcc, v5, v4 +; SI-NEXT: v_lshl_b64 v[4:5], v[2:3], v4 +; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; SI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v5 +; SI-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc +; SI-NEXT: v_and_b32_e32 v5, s6, v3 +; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v3 +; SI-NEXT: v_lshlrev_b32_e32 v2, 23, v2 ; SI-NEXT: s_mov_b32 s4, 0 ; SI-NEXT: s_movk_i32 s5, 0x80 -; SI-NEXT: v_or_b32_e32 v0, v0, v1 -; SI-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[2:3] -; SI-NEXT: v_and_b32_e32 v1, 1, v0 -; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; SI-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3] -; SI-NEXT: v_cndmask_b32_e64 v1, v1, 1, vcc -; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[4:5] +; SI-NEXT: v_and_b32_e32 v3, 1, v2 +; SI-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; SI-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[4:5] +; SI-NEXT: v_mov_b32_e32 v0, 0 +; SI-NEXT: v_cndmask_b32_e64 v3, v3, 1, vcc +; SI-NEXT: v_mov_b32_e32 v1, v0 +; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; SI-NEXT: v_cndmask_b32_e64 v0, v2, -v2, vcc ; SI-NEXT: s_setpc_b64 s[30:31] ; ; VI-LABEL: v_test_sitofp_i64_byte_to_f32: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_movk_i32 s6, 0xff -; VI-NEXT: v_and_b32_e32 v0, s6, v0 -; VI-NEXT: v_add_u32_e32 v0, vcc, 0, v0 -; VI-NEXT: v_ffbh_u32_e32 v2, v0 -; VI-NEXT: v_addc_u32_e64 v1, s[4:5], 0, 0, vcc -; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v2 -; VI-NEXT: v_ffbh_u32_e32 v3, v1 -; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; VI-NEXT: v_mov_b32_e32 v3, 0xbe -; VI-NEXT: v_sub_u32_e32 v4, vcc, v3, v2 -; VI-NEXT: v_lshlrev_b64 v[2:3], v2, v[0:1] -; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] -; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v3 -; VI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc -; VI-NEXT: v_and_b32_e32 v3, s6, v1 -; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1 -; VI-NEXT: v_lshlrev_b32_e32 v0, 23, v0 +; VI-NEXT: v_and_b32_e32 v2, s6, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0, v2 +; VI-NEXT: v_ffbh_u32_e32 v4, v2 +; VI-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v4 +; VI-NEXT: v_ffbh_u32_e32 v5, v3 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; VI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc +; VI-NEXT: v_mov_b32_e32 v5, 0xbe +; VI-NEXT: v_sub_u32_e32 v6, vcc, v5, v4 +; VI-NEXT: v_lshlrev_b64 v[4:5], v4, v[2:3] +; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; VI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v5 +; VI-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc +; VI-NEXT: v_and_b32_e32 v5, s6, v3 +; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v3 +; VI-NEXT: v_lshlrev_b32_e32 v2, 23, v2 ; VI-NEXT: s_mov_b32 s4, 0 ; VI-NEXT: s_movk_i32 s5, 0x80 -; VI-NEXT: v_or_b32_e32 v0, v0, v1 -; VI-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[2:3] -; VI-NEXT: v_and_b32_e32 v1, 1, v0 -; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; VI-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3] -; VI-NEXT: v_cndmask_b32_e64 v1, v1, 1, vcc -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1 +; VI-NEXT: v_or_b32_e32 v2, v2, v3 +; VI-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[4:5] +; VI-NEXT: v_and_b32_e32 v3, 1, v2 +; VI-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; VI-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[4:5] +; VI-NEXT: v_mov_b32_e32 v0, 0 +; VI-NEXT: v_cndmask_b32_e64 v3, v3, 1, vcc +; VI-NEXT: v_mov_b32_e32 v1, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v3 +; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; VI-NEXT: v_cndmask_b32_e64 v0, v2, -v2, vcc ; VI-NEXT: s_setpc_b64 s[30:31] %masked = and i64 %arg0, 255 %itofp = sitofp i64 %masked to float diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll index 5529060..033309c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll @@ -4736,11 +4736,23 @@ define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg ; GFX6-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1] ; GFX6-NEXT: s_cmp_lg_u32 s17, 0 ; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX6-NEXT: s_sub_i32 s9, 64, 1 +; GFX6-NEXT: s_sub_i32 s9, 1, 64 +; GFX6-NEXT: s_sub_i32 s14, 64, 1 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s17, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[12:13], s[4:5], 1 +; GFX6-NEXT: s_lshl_b64 s[14:15], s[6:7], s14 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], 1 -; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], 1 -; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], s9 -; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; GFX6-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] +; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], s9 +; GFX6-NEXT: s_cmp_lg_u32 s16, 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], s[12:13], s[6:7] +; GFX6-NEXT: s_cmp_lg_u32 s17, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX6-NEXT: s_cmp_lg_u32 s16, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 ; GFX6-NEXT: s_sub_i32 s14, s8, 64 ; GFX6-NEXT: s_sub_i32 s12, 64, s8 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64 @@ -4784,11 +4796,23 @@ define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg ; GFX8-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1] ; GFX8-NEXT: s_cmp_lg_u32 s17, 0 ; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX8-NEXT: s_sub_i32 s9, 64, 1 +; GFX8-NEXT: s_sub_i32 s9, 1, 64 +; GFX8-NEXT: s_sub_i32 s14, 64, 1 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s17, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[12:13], s[4:5], 1 +; GFX8-NEXT: s_lshl_b64 s[14:15], s[6:7], s14 ; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], 1 -; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], 1 -; GFX8-NEXT: s_lshl_b64 s[6:7], s[6:7], s9 -; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; GFX8-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] +; GFX8-NEXT: s_lshr_b64 s[6:7], s[6:7], s9 +; GFX8-NEXT: s_cmp_lg_u32 s16, 0 +; GFX8-NEXT: s_cselect_b64 s[6:7], s[12:13], s[6:7] +; GFX8-NEXT: s_cmp_lg_u32 s17, 0 +; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX8-NEXT: s_cmp_lg_u32 s16, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 ; GFX8-NEXT: s_sub_i32 s14, s8, 64 ; GFX8-NEXT: s_sub_i32 s12, 64, s8 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64 @@ -4832,11 +4856,23 @@ define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg ; GFX9-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1] ; GFX9-NEXT: s_cmp_lg_u32 s17, 0 ; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX9-NEXT: s_sub_i32 s9, 64, 1 +; GFX9-NEXT: s_sub_i32 s9, 1, 64 +; GFX9-NEXT: s_sub_i32 s14, 64, 1 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s17, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[12:13], s[4:5], 1 +; GFX9-NEXT: s_lshl_b64 s[14:15], s[6:7], s14 ; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], 1 -; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 1 -; GFX9-NEXT: s_lshl_b64 s[6:7], s[6:7], s9 -; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; GFX9-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] +; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], s9 +; GFX9-NEXT: s_cmp_lg_u32 s16, 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], s[12:13], s[6:7] +; GFX9-NEXT: s_cmp_lg_u32 s17, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX9-NEXT: s_cmp_lg_u32 s16, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 ; GFX9-NEXT: s_sub_i32 s14, s8, 64 ; GFX9-NEXT: s_sub_i32 s12, 64, s8 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64 @@ -4880,24 +4916,36 @@ define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg ; GFX10-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] ; GFX10-NEXT: s_cmp_lg_u32 s17, 0 ; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX10-NEXT: s_sub_i32 s9, 64, 1 +; GFX10-NEXT: s_sub_i32 s9, 1, 64 +; GFX10-NEXT: s_sub_i32 s10, 64, 1 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: s_cselect_b32 s17, 1, 0 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], 1 -; GFX10-NEXT: s_lshl_b64 s[4:5], s[6:7], s9 -; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], 1 -; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] +; GFX10-NEXT: s_lshl_b64 s[10:11], s[6:7], s10 +; GFX10-NEXT: s_lshr_b64 s[14:15], s[6:7], 1 +; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11] +; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], s9 +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7] +; GFX10-NEXT: s_cmp_lg_u32 s17, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1] +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[14:15], 0 ; GFX10-NEXT: s_sub_i32 s14, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cselect_b32 s15, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: s_cselect_b32 s16, 1, 0 -; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s8 -; GFX10-NEXT: s_lshl_b64 s[10:11], s[6:7], s9 -; GFX10-NEXT: s_lshr_b64 s[8:9], s[6:7], s8 -; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11] -; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 +; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s8 +; GFX10-NEXT: s_lshl_b64 s[10:11], s[4:5], s9 +; GFX10-NEXT: s_lshr_b64 s[8:9], s[4:5], s8 +; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] +; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s14 ; GFX10-NEXT: s_cmp_lg_u32 s15, 0 -; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX10-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] ; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] ; GFX10-NEXT: s_cmp_lg_u32 s15, 0 @@ -4931,26 +4979,44 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) { ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v14 -; GFX6-NEXT: s_sub_i32 s4, 64, 1 +; GFX6-NEXT: s_sub_i32 s4, 1, 64 +; GFX6-NEXT: s_sub_i32 s5, 64, 1 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 ; GFX6-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc ; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], 1 -; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], s4 -; GFX6-NEXT: v_lshr_b64 v[4:5], v[6:7], 1 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], s5 +; GFX6-NEXT: s_cselect_b32 s6, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s7, 1, 0 +; GFX6-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[6:7], s4 +; GFX6-NEXT: s_and_b32 s4, 1, s6 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_and_b32 s4, 1, s7 +; GFX6-NEXT: v_lshr_b64 v[8:9], v[6:7], 1 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_and_b32 s4, 1, s6 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc ; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 64, v15 -; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX6-NEXT: v_or_b32_e32 v1, v1, v3 -; GFX6-NEXT: v_lshr_b64 v[2:3], v[0:1], v15 -; GFX6-NEXT: v_lshl_b64 v[6:7], v[4:5], v6 ; GFX6-NEXT: v_subrev_i32_e32 v14, vcc, 64, v15 -; GFX6-NEXT: v_or_b32_e32 v6, v2, v6 -; GFX6-NEXT: v_or_b32_e32 v7, v3, v7 -; GFX6-NEXT: v_lshr_b64 v[2:3], v[4:5], v14 +; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], v15 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], v6 +; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], v15 +; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v14 +; GFX6-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15 -; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], v15 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc +; GFX6-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15 -; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc @@ -4982,26 +5048,44 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) { ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v14 -; GFX8-NEXT: s_sub_i32 s4, 64, 1 +; GFX8-NEXT: s_sub_i32 s4, 1, 64 +; GFX8-NEXT: s_sub_i32 s5, 64, 1 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 ; GFX8-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc ; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[4:5] -; GFX8-NEXT: v_lshlrev_b64 v[2:3], s4, v[6:7] -; GFX8-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7] +; GFX8-NEXT: v_lshlrev_b64 v[2:3], s5, v[6:7] +; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s4, v[6:7] +; GFX8-NEXT: s_and_b32 s4, 1, s6 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_and_b32 s4, 1, s7 +; GFX8-NEXT: v_lshrrev_b64 v[8:9], 1, v[6:7] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_and_b32 s4, 1, s6 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc ; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 64, v15 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 -; GFX8-NEXT: v_lshrrev_b64 v[2:3], v15, v[0:1] -; GFX8-NEXT: v_lshlrev_b64 v[6:7], v6, v[4:5] ; GFX8-NEXT: v_subrev_u32_e32 v14, vcc, 64, v15 -; GFX8-NEXT: v_or_b32_e32 v6, v2, v6 -; GFX8-NEXT: v_or_b32_e32 v7, v3, v7 -; GFX8-NEXT: v_lshrrev_b64 v[2:3], v14, v[4:5] +; GFX8-NEXT: v_lshrrev_b64 v[4:5], v15, v[0:1] +; GFX8-NEXT: v_lshlrev_b64 v[6:7], v6, v[2:3] +; GFX8-NEXT: v_lshrrev_b64 v[8:9], v15, v[2:3] +; GFX8-NEXT: v_lshrrev_b64 v[2:3], v14, v[2:3] +; GFX8-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15 -; GFX8-NEXT: v_lshrrev_b64 v[8:9], v15, v[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc +; GFX8-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc @@ -5033,26 +5117,44 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) { ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v14 -; GFX9-NEXT: s_sub_i32 s4, 64, 1 +; GFX9-NEXT: s_sub_i32 s4, 1, 64 +; GFX9-NEXT: s_sub_i32 s5, 64, 1 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 ; GFX9-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc ; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[4:5] -; GFX9-NEXT: v_lshlrev_b64 v[2:3], s4, v[6:7] -; GFX9-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7] +; GFX9-NEXT: v_lshlrev_b64 v[2:3], s5, v[6:7] +; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s4, v[6:7] +; GFX9-NEXT: s_and_b32 s4, 1, s6 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_and_b32 s4, 1, s7 +; GFX9-NEXT: v_lshrrev_b64 v[8:9], 1, v[6:7] +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_and_b32 s4, 1, s6 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc ; GFX9-NEXT: v_sub_u32_e32 v6, 64, v15 -; GFX9-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX9-NEXT: v_or_b32_e32 v1, v1, v3 -; GFX9-NEXT: v_lshrrev_b64 v[2:3], v15, v[0:1] -; GFX9-NEXT: v_lshlrev_b64 v[6:7], v6, v[4:5] ; GFX9-NEXT: v_subrev_u32_e32 v14, 64, v15 -; GFX9-NEXT: v_or_b32_e32 v6, v2, v6 -; GFX9-NEXT: v_or_b32_e32 v7, v3, v7 -; GFX9-NEXT: v_lshrrev_b64 v[2:3], v14, v[4:5] +; GFX9-NEXT: v_lshrrev_b64 v[4:5], v15, v[0:1] +; GFX9-NEXT: v_lshlrev_b64 v[6:7], v6, v[2:3] +; GFX9-NEXT: v_lshrrev_b64 v[8:9], v15, v[2:3] +; GFX9-NEXT: v_lshrrev_b64 v[2:3], v14, v[2:3] +; GFX9-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15 -; GFX9-NEXT: v_lshrrev_b64 v[8:9], v15, v[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc +; GFX9-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc @@ -5067,52 +5169,68 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: v_xor_b32_e32 v9, -1, v8 ; GFX10-NEXT: s_movk_i32 s4, 0x7f -; GFX10-NEXT: v_xor_b32_e32 v10, -1, v8 ; GFX10-NEXT: v_and_b32_e32 v18, s4, v8 -; GFX10-NEXT: s_sub_i32 s5, 64, 1 -; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5] -; GFX10-NEXT: v_lshlrev_b64 v[8:9], s5, v[6:7] -; GFX10-NEXT: v_and_b32_e32 v19, s4, v10 -; GFX10-NEXT: v_sub_nc_u32_e32 v11, 64, v18 -; GFX10-NEXT: v_lshlrev_b64 v[12:13], v18, v[2:3] +; GFX10-NEXT: v_and_b32_e32 v19, s4, v9 +; GFX10-NEXT: s_sub_i32 s4, 64, 1 +; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[4:5] +; GFX10-NEXT: v_lshlrev_b64 v[10:11], s4, v[6:7] +; GFX10-NEXT: s_sub_i32 s4, 1, 64 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: v_lshrrev_b64 v[12:13], s4, v[6:7] +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: v_or_b32_e32 v8, v8, v10 +; GFX10-NEXT: v_or_b32_e32 v9, v9, v11 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_and_b32 s5, 1, vcc_lo +; GFX10-NEXT: s_and_b32 s4, 1, s4 +; GFX10-NEXT: v_sub_nc_u32_e32 v14, 64, v18 ; GFX10-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7] -; GFX10-NEXT: v_subrev_nc_u32_e32 v20, 64, v18 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v8, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v9, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s5 +; GFX10-NEXT: v_lshrrev_b64 v[8:9], v14, v[0:1] +; GFX10-NEXT: v_lshlrev_b64 v[10:11], v18, v[2:3] ; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v19 -; GFX10-NEXT: v_lshrrev_b64 v[10:11], v11, v[0:1] -; GFX10-NEXT: v_or_b32_e32 v4, v4, v8 -; GFX10-NEXT: v_or_b32_e32 v5, v5, v9 -; GFX10-NEXT: v_lshlrev_b64 v[8:9], v18, v[0:1] +; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v6, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, v7, s4 +; GFX10-NEXT: v_subrev_nc_u32_e32 v20, 64, v18 +; GFX10-NEXT: v_or_b32_e32 v10, v8, v10 +; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v19 +; GFX10-NEXT: v_lshrrev_b64 v[14:15], v19, v[4:5] ; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7] +; GFX10-NEXT: v_lshlrev_b64 v[12:13], v18, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v20, v[0:1] -; GFX10-NEXT: v_or_b32_e32 v12, v10, v12 -; GFX10-NEXT: v_lshrrev_b64 v[14:15], v19, v[4:5] -; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v19 ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18 -; GFX10-NEXT: v_or_b32_e32 v13, v11, v13 -; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v19 -; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v19 -; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[6:7] +; GFX10-NEXT: v_or_b32_e32 v11, v9, v11 +; GFX10-NEXT: v_lshrrev_b64 v[8:9], v8, v[6:7] ; GFX10-NEXT: v_or_b32_e32 v14, v14, v16 +; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v19 ; GFX10-NEXT: v_or_b32_e32 v15, v15, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v0, v12, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v13, v1, v13, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v10, v0, v10, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v11, v1, v11, vcc_lo ; GFX10-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7] ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v18 -; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v14, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v6, v11, v15, s4 -; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v2, v12, v2, s6 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v13, v3, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v14, s4 +; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v19 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v9, v15, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, v2, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, v5, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v1, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v0, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, v4, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v1, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, v3, s6 +; GFX10-NEXT: v_or_b32_e32 v0, v12, v4 ; GFX10-NEXT: v_or_b32_e32 v1, v7, v5 -; GFX10-NEXT: v_or_b32_e32 v3, v3, v9 ; GFX10-NEXT: v_or_b32_e32 v2, v2, v6 -; GFX10-NEXT: v_or_b32_e32 v0, v8, v4 +; GFX10-NEXT: v_or_b32_e32 v3, v3, v8 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt) ret i128 %result @@ -5129,26 +5247,38 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, ; GFX6-NEXT: v_lshr_b64 v[0:1], s[0:1], v0 ; GFX6-NEXT: v_lshl_b64 v[2:3], s[2:3], v6 ; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 64, v6 -; GFX6-NEXT: v_lshl_b64 v[4:5], s[0:1], v6 +; GFX6-NEXT: s_sub_i32 s10, 1, 64 +; GFX6-NEXT: s_sub_i32 s8, 64, 1 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 ; GFX6-NEXT: v_or_b32_e32 v2, v0, v2 ; GFX6-NEXT: v_or_b32_e32 v3, v1, v3 ; GFX6-NEXT: v_lshl_b64 v[0:1], s[0:1], v8 ; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6 -; GFX6-NEXT: s_sub_i32 s8, 64, 1 +; GFX6-NEXT: s_cselect_b32 s11, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc +; GFX6-NEXT: s_cselect_b32 s12, 1, 0 ; GFX6-NEXT: v_mov_b32_e32 v2, s2 -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX6-NEXT: v_mov_b32_e32 v3, s3 ; GFX6-NEXT: s_lshr_b64 s[2:3], s[4:5], 1 -; GFX6-NEXT: s_lshl_b64 s[4:5], s[6:7], s8 +; GFX6-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 +; GFX6-NEXT: v_lshl_b64 v[4:5], s[0:1], v6 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], 1 +; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], s10 +; GFX6-NEXT: s_cmp_lg_u32 s11, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] +; GFX6-NEXT: s_cmp_lg_u32 s11, 0 +; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 ; GFX6-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v10, v1, v3, vcc ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v7 -; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX6-NEXT: v_lshr_b64 v[0:1], s[2:3], v7 ; GFX6-NEXT: v_lshl_b64 v[2:3], s[0:1], v2 ; GFX6-NEXT: v_subrev_i32_e32 v11, vcc, 64, v7 @@ -5182,26 +5312,38 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, ; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] ; GFX8-NEXT: v_lshlrev_b64 v[2:3], v6, s[2:3] ; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, 64, v6 -; GFX8-NEXT: v_lshlrev_b64 v[4:5], v6, s[0:1] +; GFX8-NEXT: s_sub_i32 s10, 1, 64 +; GFX8-NEXT: s_sub_i32 s8, 64, 1 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 ; GFX8-NEXT: v_or_b32_e32 v2, v0, v2 ; GFX8-NEXT: v_or_b32_e32 v3, v1, v3 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, s[0:1] ; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6 -; GFX8-NEXT: s_sub_i32 s8, 64, 1 +; GFX8-NEXT: s_cselect_b32 s11, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc +; GFX8-NEXT: s_cselect_b32 s12, 1, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, s2 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: s_lshr_b64 s[2:3], s[4:5], 1 -; GFX8-NEXT: s_lshl_b64 s[4:5], s[6:7], s8 +; GFX8-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 +; GFX8-NEXT: v_lshlrev_b64 v[4:5], v6, s[0:1] ; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], 1 +; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX8-NEXT: s_lshr_b64 s[6:7], s[6:7], s10 +; GFX8-NEXT: s_cmp_lg_u32 s11, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] +; GFX8-NEXT: s_cmp_lg_u32 s11, 0 +; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v1, v3, vcc ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 64, v7 -; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX8-NEXT: v_lshrrev_b64 v[0:1], v7, s[2:3] ; GFX8-NEXT: v_lshlrev_b64 v[2:3], v2, s[0:1] ; GFX8-NEXT: v_subrev_u32_e32 v11, vcc, 64, v7 @@ -5235,24 +5377,36 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, ; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[2:3], v6, s[2:3] ; GFX9-NEXT: v_subrev_u32_e32 v8, 64, v6 -; GFX9-NEXT: v_lshlrev_b64 v[4:5], v6, s[0:1] +; GFX9-NEXT: s_sub_i32 s10, 1, 64 +; GFX9-NEXT: s_sub_i32 s8, 64, 1 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 ; GFX9-NEXT: v_or_b32_e32 v2, v0, v2 ; GFX9-NEXT: v_or_b32_e32 v3, v1, v3 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, s[0:1] ; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6 -; GFX9-NEXT: s_sub_i32 s8, 64, 1 +; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc +; GFX9-NEXT: s_cselect_b32 s12, 1, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, s2 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], 1 -; GFX9-NEXT: s_lshl_b64 s[4:5], s[6:7], s8 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc +; GFX9-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 +; GFX9-NEXT: v_lshlrev_b64 v[4:5], v6, s[0:1] ; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], 1 -; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] +; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], s10 +; GFX9-NEXT: s_cmp_lg_u32 s11, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] +; GFX9-NEXT: s_cmp_lg_u32 s11, 0 +; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 ; GFX9-NEXT: v_sub_u32_e32 v2, 64, v7 ; GFX9-NEXT: v_cndmask_b32_e32 v10, v1, v3, vcc ; GFX9-NEXT: v_lshrrev_b64 v[0:1], v7, s[2:3] @@ -5281,45 +5435,57 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, ; GFX10-LABEL: v_fshl_i128_ssv: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_movk_i32 s8, 0x7f -; GFX10-NEXT: v_xor_b32_e32 v4, -1, v0 +; GFX10-NEXT: s_sub_i32 s14, 1, 64 ; GFX10-NEXT: v_and_b32_e32 v12, s8, v0 -; GFX10-NEXT: s_sub_i32 s9, 64, 1 -; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 1 -; GFX10-NEXT: v_and_b32_e32 v13, s8, v4 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v12 -; GFX10-NEXT: v_lshlrev_b64 v[0:1], v12, s[2:3] -; GFX10-NEXT: s_lshl_b64 s[8:9], s[6:7], s9 -; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], 1 -; GFX10-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9] -; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, s[0:1] +; GFX10-NEXT: v_xor_b32_e32 v0, -1, v0 +; GFX10-NEXT: s_sub_i32 s10, 64, 1 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: v_sub_nc_u32_e32 v1, 64, v12 +; GFX10-NEXT: s_cselect_b32 s15, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: v_and_b32_e32 v13, s8, v0 +; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: v_lshrrev_b64 v[0:1], v1, s[0:1] +; GFX10-NEXT: v_lshlrev_b64 v[2:3], v12, s[2:3] +; GFX10-NEXT: s_lshr_b64 s[8:9], s[4:5], 1 +; GFX10-NEXT: s_lshl_b64 s[10:11], s[6:7], s10 +; GFX10-NEXT: s_lshr_b64 s[12:13], s[6:7], 1 +; GFX10-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] +; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 +; GFX10-NEXT: s_cmp_lg_u32 s15, 0 +; GFX10-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX10-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7] +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: v_sub_nc_u32_e32 v0, 64, v13 +; GFX10-NEXT: s_cselect_b64 s[6:7], s[4:5], s[6:7] +; GFX10-NEXT: s_cmp_lg_u32 s15, 0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v12 +; GFX10-NEXT: s_cselect_b64 s[8:9], s[12:13], 0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v14, 64, v13 -; GFX10-NEXT: v_lshrrev_b64 v[6:7], v13, s[8:9] +; GFX10-NEXT: v_lshrrev_b64 v[6:7], v13, s[6:7] +; GFX10-NEXT: v_lshlrev_b64 v[8:9], v0, s[8:9] +; GFX10-NEXT: v_lshlrev_b64 v[10:11], v10, s[0:1] +; GFX10-NEXT: v_or_b32_e32 v3, v1, v3 ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v12 +; GFX10-NEXT: v_lshrrev_b64 v[0:1], v14, s[8:9] ; GFX10-NEXT: v_lshlrev_b64 v[4:5], v12, s[0:1] -; GFX10-NEXT: v_or_b32_e32 v2, v2, v0 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, 64, v13 -; GFX10-NEXT: v_lshlrev_b64 v[10:11], v10, s[0:1] -; GFX10-NEXT: v_or_b32_e32 v3, v3, v1 -; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 64, v13 -; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 0, v13 -; GFX10-NEXT: v_lshlrev_b64 v[8:9], v0, s[6:7] -; GFX10-NEXT: v_lshrrev_b64 v[0:1], v14, s[6:7] -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo ; GFX10-NEXT: v_or_b32_e32 v6, v6, v8 +; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 64, v13 ; GFX10-NEXT: v_or_b32_e32 v7, v7, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v3, vcc_lo -; GFX10-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7] +; GFX10-NEXT: v_lshrrev_b64 v[2:3], v13, s[8:9] ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s0 +; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 0, v13 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v7, s0 +; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s6, s1 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s7, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v8, s2, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v7, v10, s3, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s8, s1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s9, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v7, v10, s3, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 ; GFX10-NEXT: v_or_b32_e32 v0, v4, v0 ; GFX10-NEXT: v_or_b32_e32 v1, v5, v1 @@ -5353,41 +5519,57 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 ; GFX6-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] ; GFX6-NEXT: s_cmp_lg_u32 s13, 0 -; GFX6-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] -; GFX6-NEXT: s_sub_i32 s2, 64, 1 -; GFX6-NEXT: v_lshl_b64 v[4:5], v[2:3], s2 -; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 1 -; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 1 -; GFX6-NEXT: s_sub_i32 s3, 64, s4 -; GFX6-NEXT: s_sub_i32 s2, s4, 64 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX6-NEXT: s_sub_i32 s1, 64, 1 +; GFX6-NEXT: s_sub_i32 s0, 1, 64 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], 1 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s1 +; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], 1 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s0 +; GFX6-NEXT: s_and_b32 s0, 1, s5 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: s_and_b32 s0, 1, s8 +; GFX6-NEXT: v_or_b32_e32 v4, v4, v6 +; GFX6-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 +; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] +; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[0:1] +; GFX6-NEXT: s_sub_i32 s0, s4, 64 +; GFX6-NEXT: s_sub_i32 s1, 64, s4 ; GFX6-NEXT: s_cmp_lt_u32 s4, 64 -; GFX6-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX6-NEXT: v_or_b32_e32 v1, v1, v5 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc ; GFX6-NEXT: s_cselect_b32 s5, 1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s4, 0 ; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s4 -; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s3 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s1 ; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], s4 ; GFX6-NEXT: s_cselect_b32 s8, 1, 0 -; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s2 -; GFX6-NEXT: s_and_b32 s2, 1, s5 -; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s0 +; GFX6-NEXT: s_and_b32 s0, 1, s5 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX6-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX6-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX6-NEXT: s_and_b32 s2, 1, s8 +; GFX6-NEXT: s_and_b32 s0, 1, s8 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc -; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 -; GFX6-NEXT: s_and_b32 s2, 1, s5 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: s_and_b32 s0, 1, s5 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc ; GFX6-NEXT: v_or_b32_e32 v0, s6, v0 ; GFX6-NEXT: v_or_b32_e32 v1, s7, v1 -; GFX6-NEXT: v_or_b32_e32 v2, s0, v2 -; GFX6-NEXT: v_or_b32_e32 v3, s1, v3 +; GFX6-NEXT: v_or_b32_e32 v2, s2, v2 +; GFX6-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_fshl_i128_svs: @@ -5411,41 +5593,57 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 ; GFX8-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] ; GFX8-NEXT: s_cmp_lg_u32 s13, 0 -; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] -; GFX8-NEXT: s_sub_i32 s2, 64, 1 -; GFX8-NEXT: v_lshlrev_b64 v[4:5], s2, v[2:3] -; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1] -; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3] -; GFX8-NEXT: s_sub_i32 s3, 64, s4 -; GFX8-NEXT: s_sub_i32 s2, s4, 64 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX8-NEXT: s_sub_i32 s1, 64, 1 +; GFX8-NEXT: s_sub_i32 s0, 1, 64 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: v_lshrrev_b64 v[4:5], 1, v[0:1] +; GFX8-NEXT: v_lshlrev_b64 v[6:7], s1, v[2:3] +; GFX8-NEXT: v_lshrrev_b64 v[8:9], 1, v[2:3] +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: v_lshrrev_b64 v[2:3], s0, v[2:3] +; GFX8-NEXT: s_and_b32 s0, 1, s5 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_and_b32 s0, 1, s8 +; GFX8-NEXT: v_or_b32_e32 v4, v4, v6 +; GFX8-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 +; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] +; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[0:1] +; GFX8-NEXT: s_sub_i32 s0, s4, 64 +; GFX8-NEXT: s_sub_i32 s1, 64, s4 ; GFX8-NEXT: s_cmp_lt_u32 s4, 64 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v5 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc ; GFX8-NEXT: s_cselect_b32 s5, 1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s4, 0 ; GFX8-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] -; GFX8-NEXT: v_lshlrev_b64 v[6:7], s3, v[2:3] +; GFX8-NEXT: v_lshlrev_b64 v[6:7], s1, v[2:3] ; GFX8-NEXT: v_lshrrev_b64 v[8:9], s4, v[2:3] ; GFX8-NEXT: s_cselect_b32 s8, 1, 0 -; GFX8-NEXT: v_lshrrev_b64 v[2:3], s2, v[2:3] -; GFX8-NEXT: s_and_b32 s2, 1, s5 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX8-NEXT: v_lshrrev_b64 v[2:3], s0, v[2:3] +; GFX8-NEXT: s_and_b32 s0, 1, s5 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX8-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX8-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX8-NEXT: s_and_b32 s2, 1, s8 +; GFX8-NEXT: s_and_b32 s0, 1, s8 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 -; GFX8-NEXT: s_and_b32 s2, 1, s5 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_and_b32 s0, 1, s5 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc ; GFX8-NEXT: v_or_b32_e32 v0, s6, v0 ; GFX8-NEXT: v_or_b32_e32 v1, s7, v1 -; GFX8-NEXT: v_or_b32_e32 v2, s0, v2 -; GFX8-NEXT: v_or_b32_e32 v3, s1, v3 +; GFX8-NEXT: v_or_b32_e32 v2, s2, v2 +; GFX8-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_fshl_i128_svs: @@ -5469,48 +5667,64 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 ; GFX9-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 -; GFX9-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] -; GFX9-NEXT: s_sub_i32 s2, 64, 1 -; GFX9-NEXT: v_lshlrev_b64 v[4:5], s2, v[2:3] -; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1] -; GFX9-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3] -; GFX9-NEXT: s_sub_i32 s3, 64, s4 -; GFX9-NEXT: s_sub_i32 s2, s4, 64 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX9-NEXT: s_sub_i32 s1, 64, 1 +; GFX9-NEXT: s_sub_i32 s0, 1, 64 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: v_lshrrev_b64 v[4:5], 1, v[0:1] +; GFX9-NEXT: v_lshlrev_b64 v[6:7], s1, v[2:3] +; GFX9-NEXT: v_lshrrev_b64 v[8:9], 1, v[2:3] +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: v_lshrrev_b64 v[2:3], s0, v[2:3] +; GFX9-NEXT: s_and_b32 s0, 1, s5 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_and_b32 s0, 1, s8 +; GFX9-NEXT: v_or_b32_e32 v4, v4, v6 +; GFX9-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[0:1] +; GFX9-NEXT: s_sub_i32 s0, s4, 64 +; GFX9-NEXT: s_sub_i32 s1, 64, s4 ; GFX9-NEXT: s_cmp_lt_u32 s4, 64 -; GFX9-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX9-NEXT: v_or_b32_e32 v1, v1, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc ; GFX9-NEXT: s_cselect_b32 s5, 1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s4, 0 ; GFX9-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] -; GFX9-NEXT: v_lshlrev_b64 v[6:7], s3, v[2:3] +; GFX9-NEXT: v_lshlrev_b64 v[6:7], s1, v[2:3] ; GFX9-NEXT: v_lshrrev_b64 v[8:9], s4, v[2:3] ; GFX9-NEXT: s_cselect_b32 s8, 1, 0 -; GFX9-NEXT: v_lshrrev_b64 v[2:3], s2, v[2:3] -; GFX9-NEXT: s_and_b32 s2, 1, s5 -; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX9-NEXT: v_lshrrev_b64 v[2:3], s0, v[2:3] +; GFX9-NEXT: s_and_b32 s0, 1, s5 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX9-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX9-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX9-NEXT: s_and_b32 s2, 1, s8 +; GFX9-NEXT: s_and_b32 s0, 1, s8 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc -; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 -; GFX9-NEXT: s_and_b32 s2, 1, s5 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_and_b32 s0, 1, s5 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc ; GFX9-NEXT: v_or_b32_e32 v0, s6, v0 ; GFX9-NEXT: v_or_b32_e32 v1, s7, v1 -; GFX9-NEXT: v_or_b32_e32 v2, s0, v2 -; GFX9-NEXT: v_or_b32_e32 v3, s1, v3 +; GFX9-NEXT: v_or_b32_e32 v2, s2, v2 +; GFX9-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_fshl_i128_svs: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_movk_i32 s6, 0x7f ; GFX10-NEXT: s_mov_b32 s7, 0 -; GFX10-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1] +; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[0:1] ; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX10-NEXT: s_sub_i32 s5, s8, 64 @@ -5530,24 +5744,40 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX10-NEXT: s_cmp_lg_u32 s13, 0 ; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX10-NEXT: s_sub_i32 s0, 64, 1 -; GFX10-NEXT: v_lshlrev_b64 v[4:5], s0, v[2:3] +; GFX10-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3] +; GFX10-NEXT: s_sub_i32 s0, 1, 64 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 +; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo +; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3] +; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 ; GFX10-NEXT: s_sub_i32 s0, 64, s4 -; GFX10-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX10-NEXT: v_or_b32_e32 v1, v1, v5 +; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3] ; GFX10-NEXT: s_sub_i32 s0, s4, 64 ; GFX10-NEXT: s_cmp_lt_u32 s4, 64 ; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] -; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] ; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s4, 0 -; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3] -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 -; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo ; GFX10-NEXT: s_and_b32 s0, 1, s0 +; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3] ; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 @@ -5593,30 +5823,42 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 -; GFX6-NEXT: s_sub_i32 s5, 64, 1 +; GFX6-NEXT: s_sub_i32 s5, 1, 64 +; GFX6-NEXT: s_sub_i32 s10, 64, 1 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s12, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s13, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[8:9], s[0:1], 1 +; GFX6-NEXT: s_lshl_b64 s[10:11], s[2:3], s10 ; GFX6-NEXT: s_lshr_b64 s[6:7], s[2:3], 1 -; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 1 -; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s5 -; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] -; GFX6-NEXT: s_sub_i32 s10, s4, 64 +; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] +; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], s5 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX6-NEXT: s_cmp_lg_u32 s13, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 +; GFX6-NEXT: s_sub_i32 s10, s4, 64 ; GFX6-NEXT: s_sub_i32 s8, 64, s4 ; GFX6-NEXT: s_cmp_lt_u32 s4, 64 ; GFX6-NEXT: s_cselect_b32 s11, 1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s4, 0 ; GFX6-NEXT: s_cselect_b32 s12, 1, 0 -; GFX6-NEXT: s_lshr_b64 s[2:3], s[6:7], s4 -; GFX6-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 +; GFX6-NEXT: s_lshr_b64 s[6:7], s[2:3], s4 +; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX6-NEXT: s_lshr_b64 s[4:5], s[0:1], s4 ; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] -; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], s10 +; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; GFX6-NEXT: s_cmp_lg_u32 s11, 0 -; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX6-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 -; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX6-NEXT: s_cmp_lg_u32 s11, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc -; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 ; GFX6-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX6-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX6-NEXT: v_or_b32_e32 v2, s2, v2 @@ -5649,30 +5891,42 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 -; GFX8-NEXT: s_sub_i32 s5, 64, 1 +; GFX8-NEXT: s_sub_i32 s5, 1, 64 +; GFX8-NEXT: s_sub_i32 s10, 64, 1 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s12, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s13, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[8:9], s[0:1], 1 +; GFX8-NEXT: s_lshl_b64 s[10:11], s[2:3], s10 ; GFX8-NEXT: s_lshr_b64 s[6:7], s[2:3], 1 -; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 1 -; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], s5 -; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] +; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], s5 +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX8-NEXT: s_cmp_lg_u32 s13, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 ; GFX8-NEXT: s_sub_i32 s10, s4, 64 ; GFX8-NEXT: s_sub_i32 s8, 64, s4 ; GFX8-NEXT: s_cmp_lt_u32 s4, 64 ; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s12, 1, 0 -; GFX8-NEXT: s_lshr_b64 s[2:3], s[6:7], s4 -; GFX8-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 +; GFX8-NEXT: s_lshr_b64 s[6:7], s[2:3], s4 +; GFX8-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX8-NEXT: s_lshr_b64 s[4:5], s[0:1], s4 ; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] -; GFX8-NEXT: s_lshr_b64 s[6:7], s[6:7], s10 +; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 -; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX8-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] ; GFX8-NEXT: s_cmp_lg_u32 s12, 0 -; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc -; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 ; GFX8-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX8-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX8-NEXT: v_or_b32_e32 v2, s2, v2 @@ -5705,30 +5959,42 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 -; GFX9-NEXT: s_sub_i32 s5, 64, 1 +; GFX9-NEXT: s_sub_i32 s5, 1, 64 +; GFX9-NEXT: s_sub_i32 s10, 64, 1 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s12, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s13, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[8:9], s[0:1], 1 +; GFX9-NEXT: s_lshl_b64 s[10:11], s[2:3], s10 ; GFX9-NEXT: s_lshr_b64 s[6:7], s[2:3], 1 -; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], 1 -; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s5 -; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] +; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], s5 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX9-NEXT: s_cmp_lg_u32 s13, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 ; GFX9-NEXT: s_sub_i32 s10, s4, 64 ; GFX9-NEXT: s_sub_i32 s8, 64, s4 ; GFX9-NEXT: s_cmp_lt_u32 s4, 64 ; GFX9-NEXT: s_cselect_b32 s11, 1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s4, 0 ; GFX9-NEXT: s_cselect_b32 s12, 1, 0 -; GFX9-NEXT: s_lshr_b64 s[2:3], s[6:7], s4 -; GFX9-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 +; GFX9-NEXT: s_lshr_b64 s[6:7], s[2:3], s4 +; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX9-NEXT: s_lshr_b64 s[4:5], s[0:1], s4 ; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] -; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], s10 +; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; GFX9-NEXT: s_cmp_lg_u32 s11, 0 -; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX9-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] ; GFX9-NEXT: s_cmp_lg_u32 s12, 0 -; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX9-NEXT: s_cmp_lg_u32 s11, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc -; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 ; GFX9-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX9-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX9-NEXT: v_or_b32_e32 v2, s2, v2 @@ -5740,52 +6006,64 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX10-NEXT: s_movk_i32 s6, 0x7f ; GFX10-NEXT: s_mov_b32 s7, 0 ; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] -; GFX10-NEXT: s_andn2_b64 s[6:7], s[6:7], s[4:5] -; GFX10-NEXT: s_sub_i32 s4, 64, s8 +; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] +; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_sub_i32 s5, s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 -; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] -; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] +; GFX10-NEXT: v_lshrrev_b64 v[4:5], s9, v[0:1] ; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 +; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] -; GFX10-NEXT: s_cselect_b32 s7, 1, 0 -; GFX10-NEXT: s_and_b32 s4, 1, vcc_lo +; GFX10-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] +; GFX10-NEXT: s_and_b32 s5, 1, vcc_lo +; GFX10-NEXT: s_and_b32 s12, 1, s6 +; GFX10-NEXT: s_sub_i32 s13, 1, 64 +; GFX10-NEXT: s_sub_i32 s8, 64, 1 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4 -; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 1 -; GFX10-NEXT: s_and_b32 s7, 1, s7 -; GFX10-NEXT: s_sub_i32 s10, s6, 64 -; GFX10-NEXT: s_sub_i32 s8, 64, s6 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v5, s4 -; GFX10-NEXT: s_sub_i32 s4, 64, 1 ; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo -; GFX10-NEXT: s_lshl_b64 s[4:5], s[2:3], s4 -; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1 -; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] -; GFX10-NEXT: s_cmp_lt_u32 s6, 64 ; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 +; GFX10-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: s_cselect_b32 s14, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], 1 +; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 +; GFX10-NEXT: s_lshr_b64 s[10:11], s[2:3], 1 +; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] +; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s13 +; GFX10-NEXT: s_cmp_lg_u32 s5, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX10-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3] +; GFX10-NEXT: s_cmp_lg_u32 s14, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo +; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] +; GFX10-NEXT: s_cmp_lg_u32 s5, 0 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s12 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[10:11], 0 +; GFX10-NEXT: s_sub_i32 s10, s4, 64 +; GFX10-NEXT: s_sub_i32 s5, 64, s4 +; GFX10-NEXT: s_cmp_lt_u32 s4, 64 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 -; GFX10-NEXT: s_cmp_eq_u32 s6, 0 -; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s7 +; GFX10-NEXT: s_cmp_eq_u32 s4, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo ; GFX10-NEXT: s_cselect_b32 s12, 1, 0 -; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s6 -; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 -; GFX10-NEXT: s_lshr_b64 s[6:7], s[2:3], s6 -; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] +; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s4 +; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s5 +; GFX10-NEXT: s_lshr_b64 s[4:5], s[2:3], s4 +; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo -; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] +; GFX10-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3] ; GFX10-NEXT: s_cmp_lg_u32 s12, 0 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: v_or_b32_e32 v0, s0, v6 -; GFX10-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 ; GFX10-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 @@ -5798,58 +6076,170 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i define amdgpu_ps i128 @s_fshl_i128_65(i128 inreg %lhs, i128 inreg %rhs) { ; GFX6-LABEL: s_fshl_i128_65: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_sub_i32 s2, 0x41, 64 -; GFX6-NEXT: s_sub_i32 s4, 64, 63 +; GFX6-NEXT: s_movk_i32 s8, 0x41 +; GFX6-NEXT: s_sub_i32 s16, s8, 64 +; GFX6-NEXT: s_sub_i32 s12, 64, s8 +; GFX6-NEXT: s_cmp_lt_u32 s8, 64 +; GFX6-NEXT: s_cselect_b32 s17, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s8, 0 +; GFX6-NEXT: s_cselect_b32 s18, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[12:13], s[0:1], s12 +; GFX6-NEXT: s_lshl_b64 s[14:15], s[2:3], s8 +; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], s8 +; GFX6-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] +; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s16 +; GFX6-NEXT: s_cmp_lg_u32 s17, 0 +; GFX6-NEXT: s_cselect_b64 s[10:11], s[10:11], 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1] +; GFX6-NEXT: s_cmp_lg_u32 s18, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX6-NEXT: s_sub_i32 s14, 63, 64 +; GFX6-NEXT: s_sub_i32 s12, 64, 63 +; GFX6-NEXT: s_cmp_lt_u32 63, 64 ; GFX6-NEXT: s_mov_b32 s9, 0 -; GFX6-NEXT: s_lshl_b64 s[2:3], s[0:1], s2 -; GFX6-NEXT: s_lshr_b32 s8, s7, 31 +; GFX6-NEXT: s_cselect_b32 s15, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 63, 0 +; GFX6-NEXT: s_cselect_b32 s16, 1, 0 ; GFX6-NEXT: s_lshr_b32 s0, s5, 31 ; GFX6-NEXT: s_mov_b32 s1, s9 -; GFX6-NEXT: s_lshl_b64 s[4:5], s[6:7], s4 -; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] -; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX6-NEXT: s_lshl_b64 s[12:13], s[6:7], s12 +; GFX6-NEXT: s_lshr_b32 s8, s7, 31 +; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[12:13] +; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 +; GFX6-NEXT: s_cmp_lg_u32 s15, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7] +; GFX6-NEXT: s_cmp_lg_u32 s16, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1] +; GFX6-NEXT: s_cmp_lg_u32 s15, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], s[8:9], 0 +; GFX6-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1] +; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: s_fshl_i128_65: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_sub_i32 s2, 0x41, 64 -; GFX8-NEXT: s_sub_i32 s4, 64, 63 +; GFX8-NEXT: s_movk_i32 s8, 0x41 +; GFX8-NEXT: s_sub_i32 s16, s8, 64 +; GFX8-NEXT: s_sub_i32 s12, 64, s8 +; GFX8-NEXT: s_cmp_lt_u32 s8, 64 +; GFX8-NEXT: s_cselect_b32 s17, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s8, 0 +; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[12:13], s[0:1], s12 +; GFX8-NEXT: s_lshl_b64 s[14:15], s[2:3], s8 +; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], s8 +; GFX8-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] +; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s16 +; GFX8-NEXT: s_cmp_lg_u32 s17, 0 +; GFX8-NEXT: s_cselect_b64 s[10:11], s[10:11], 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1] +; GFX8-NEXT: s_cmp_lg_u32 s18, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX8-NEXT: s_sub_i32 s14, 63, 64 +; GFX8-NEXT: s_sub_i32 s12, 64, 63 +; GFX8-NEXT: s_cmp_lt_u32 63, 64 ; GFX8-NEXT: s_mov_b32 s9, 0 -; GFX8-NEXT: s_lshl_b64 s[2:3], s[0:1], s2 -; GFX8-NEXT: s_lshr_b32 s8, s7, 31 +; GFX8-NEXT: s_cselect_b32 s15, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 63, 0 +; GFX8-NEXT: s_cselect_b32 s16, 1, 0 ; GFX8-NEXT: s_lshr_b32 s0, s5, 31 ; GFX8-NEXT: s_mov_b32 s1, s9 -; GFX8-NEXT: s_lshl_b64 s[4:5], s[6:7], s4 -; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] -; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX8-NEXT: s_lshl_b64 s[12:13], s[6:7], s12 +; GFX8-NEXT: s_lshr_b32 s8, s7, 31 +; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[12:13] +; GFX8-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 +; GFX8-NEXT: s_cmp_lg_u32 s15, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7] +; GFX8-NEXT: s_cmp_lg_u32 s16, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1] +; GFX8-NEXT: s_cmp_lg_u32 s15, 0 +; GFX8-NEXT: s_cselect_b64 s[4:5], s[8:9], 0 +; GFX8-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1] +; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_fshl_i128_65: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_sub_i32 s2, 0x41, 64 -; GFX9-NEXT: s_sub_i32 s4, 64, 63 +; GFX9-NEXT: s_movk_i32 s8, 0x41 +; GFX9-NEXT: s_sub_i32 s16, s8, 64 +; GFX9-NEXT: s_sub_i32 s12, 64, s8 +; GFX9-NEXT: s_cmp_lt_u32 s8, 64 +; GFX9-NEXT: s_cselect_b32 s17, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s8, 0 +; GFX9-NEXT: s_cselect_b32 s18, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[12:13], s[0:1], s12 +; GFX9-NEXT: s_lshl_b64 s[14:15], s[2:3], s8 +; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], s8 +; GFX9-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] +; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s16 +; GFX9-NEXT: s_cmp_lg_u32 s17, 0 +; GFX9-NEXT: s_cselect_b64 s[10:11], s[10:11], 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1] +; GFX9-NEXT: s_cmp_lg_u32 s18, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX9-NEXT: s_sub_i32 s14, 63, 64 +; GFX9-NEXT: s_sub_i32 s12, 64, 63 +; GFX9-NEXT: s_cmp_lt_u32 63, 64 ; GFX9-NEXT: s_mov_b32 s9, 0 -; GFX9-NEXT: s_lshl_b64 s[2:3], s[0:1], s2 -; GFX9-NEXT: s_lshr_b32 s8, s7, 31 +; GFX9-NEXT: s_cselect_b32 s15, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 63, 0 +; GFX9-NEXT: s_cselect_b32 s16, 1, 0 ; GFX9-NEXT: s_lshr_b32 s0, s5, 31 ; GFX9-NEXT: s_mov_b32 s1, s9 -; GFX9-NEXT: s_lshl_b64 s[4:5], s[6:7], s4 -; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] -; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX9-NEXT: s_lshl_b64 s[12:13], s[6:7], s12 +; GFX9-NEXT: s_lshr_b32 s8, s7, 31 +; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[12:13] +; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 +; GFX9-NEXT: s_cmp_lg_u32 s15, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7] +; GFX9-NEXT: s_cmp_lg_u32 s16, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1] +; GFX9-NEXT: s_cmp_lg_u32 s15, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], s[8:9], 0 +; GFX9-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1] +; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_fshl_i128_65: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_sub_i32 s2, 0x41, 64 -; GFX10-NEXT: s_sub_i32 s4, 64, 63 -; GFX10-NEXT: s_mov_b32 s9, 0 -; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], s2 -; GFX10-NEXT: s_lshr_b32 s0, s5, 31 -; GFX10-NEXT: s_lshr_b32 s8, s7, 31 -; GFX10-NEXT: s_mov_b32 s1, s9 -; GFX10-NEXT: s_lshl_b64 s[4:5], s[6:7], s4 -; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] -; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] +; GFX10-NEXT: s_movk_i32 s12, 0x41 +; GFX10-NEXT: s_sub_i32 s14, s12, 64 +; GFX10-NEXT: s_sub_i32 s8, 64, s12 +; GFX10-NEXT: s_cmp_lt_u32 s12, 64 +; GFX10-NEXT: s_cselect_b32 s15, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s12, 0 +; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s12 +; GFX10-NEXT: s_lshr_b64 s[8:9], s[0:1], s8 +; GFX10-NEXT: s_lshl_b64 s[12:13], s[0:1], s12 +; GFX10-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] +; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s14 +; GFX10-NEXT: s_cmp_lg_u32 s15, 0 +; GFX10-NEXT: s_cselect_b64 s[10:11], s[12:13], 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX10-NEXT: s_sub_i32 s14, 63, 64 +; GFX10-NEXT: s_sub_i32 s0, 64, 63 +; GFX10-NEXT: s_cmp_lt_u32 63, 64 +; GFX10-NEXT: s_mov_b32 s1, 0 +; GFX10-NEXT: s_cselect_b32 s15, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 63, 0 +; GFX10-NEXT: s_mov_b32 s9, s1 +; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_lshl_b64 s[12:13], s[6:7], s0 +; GFX10-NEXT: s_lshr_b32 s8, s5, 31 +; GFX10-NEXT: s_lshr_b32 s0, s7, 31 +; GFX10-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13] +; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 +; GFX10-NEXT: s_cmp_lg_u32 s15, 0 +; GFX10-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7] +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX10-NEXT: s_cmp_lg_u32 s15, 0 +; GFX10-NEXT: s_cselect_b64 s[6:7], s[0:1], 0 +; GFX10-NEXT: s_or_b64 s[0:1], s[10:11], s[4:5] +; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] ; GFX10-NEXT: ; return to shader part epilog %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65) ret i128 %result @@ -5859,39 +6249,159 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) { ; GFX6-LABEL: v_fshl_i128_65: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: s_sub_i32 s4, 0x41, 64 -; GFX6-NEXT: v_lshl_b64 v[2:3], v[0:1], s4 -; GFX6-NEXT: s_sub_i32 s4, 64, 63 -; GFX6-NEXT: v_lshl_b64 v[0:1], v[6:7], s4 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v7 -; GFX6-NEXT: v_lshrrev_b32_e32 v5, 31, v5 -; GFX6-NEXT: v_or_b32_e32 v0, v5, v0 +; GFX6-NEXT: s_movk_i32 s4, 0x41 +; GFX6-NEXT: s_sub_i32 s6, 64, s4 +; GFX6-NEXT: s_sub_i32 s5, s4, 64 +; GFX6-NEXT: s_cmp_lt_u32 s4, 64 +; GFX6-NEXT: s_cselect_b32 s7, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s4, 0 +; GFX6-NEXT: v_lshr_b64 v[8:9], v[0:1], s6 +; GFX6-NEXT: v_lshl_b64 v[10:11], v[2:3], s4 +; GFX6-NEXT: v_lshl_b64 v[12:13], v[0:1], s4 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s5 +; GFX6-NEXT: s_and_b32 s4, 1, s7 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_or_b32_e32 v8, v8, v10 +; GFX6-NEXT: v_or_b32_e32 v9, v9, v11 +; GFX6-NEXT: s_and_b32 s4, 1, s8 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_sub_i32 s4, 63, 64 +; GFX6-NEXT: s_sub_i32 s5, 64, 63 +; GFX6-NEXT: s_cmp_lt_u32 63, 64 +; GFX6-NEXT: s_cselect_b32 s6, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 63, 0 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc +; GFX6-NEXT: v_lshl_b64 v[0:1], v[6:7], s5 +; GFX6-NEXT: v_lshrrev_b32_e32 v8, 31, v7 +; GFX6-NEXT: v_lshrrev_b32_e32 v9, 31, v5 +; GFX6-NEXT: s_cselect_b32 s7, 1, 0 +; GFX6-NEXT: v_lshr_b64 v[6:7], v[6:7], s4 +; GFX6-NEXT: s_and_b32 s4, 1, s6 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_or_b32_e32 v0, v9, v0 +; GFX6-NEXT: s_and_b32 s4, 1, s7 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_and_b32 s4, 1, s6 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX6-NEXT: v_or_b32_e32 v0, v10, v0 +; GFX6-NEXT: v_or_b32_e32 v1, v11, v1 ; GFX6-NEXT: v_or_b32_e32 v2, v2, v4 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_fshl_i128_65: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: s_sub_i32 s4, 0x41, 64 -; GFX8-NEXT: v_lshlrev_b64 v[2:3], s4, v[0:1] -; GFX8-NEXT: s_sub_i32 s4, 64, 63 -; GFX8-NEXT: v_lshlrev_b64 v[0:1], s4, v[6:7] -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v7 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 31, v5 -; GFX8-NEXT: v_or_b32_e32 v0, v5, v0 +; GFX8-NEXT: s_movk_i32 s4, 0x41 +; GFX8-NEXT: s_sub_i32 s6, 64, s4 +; GFX8-NEXT: s_sub_i32 s5, s4, 64 +; GFX8-NEXT: s_cmp_lt_u32 s4, 64 +; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s4, 0 +; GFX8-NEXT: v_lshrrev_b64 v[8:9], s6, v[0:1] +; GFX8-NEXT: v_lshlrev_b64 v[10:11], s4, v[2:3] +; GFX8-NEXT: v_lshlrev_b64 v[12:13], s4, v[0:1] +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] +; GFX8-NEXT: s_and_b32 s4, 1, s7 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_or_b32_e32 v8, v8, v10 +; GFX8-NEXT: v_or_b32_e32 v9, v9, v11 +; GFX8-NEXT: s_and_b32 s4, 1, s8 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_sub_i32 s4, 63, 64 +; GFX8-NEXT: s_sub_i32 s5, 64, 63 +; GFX8-NEXT: s_cmp_lt_u32 63, 64 +; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 63, 0 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc +; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[6:7] +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 31, v7 +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 31, v5 +; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: v_lshrrev_b64 v[6:7], s4, v[6:7] +; GFX8-NEXT: s_and_b32 s4, 1, s6 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_or_b32_e32 v0, v9, v0 +; GFX8-NEXT: s_and_b32 s4, 1, s7 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_and_b32 s4, 1, s6 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX8-NEXT: v_or_b32_e32 v0, v10, v0 +; GFX8-NEXT: v_or_b32_e32 v1, v11, v1 ; GFX8-NEXT: v_or_b32_e32 v2, v2, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_fshl_i128_65: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_sub_i32 s4, 0x41, 64 -; GFX9-NEXT: v_lshlrev_b64 v[2:3], s4, v[0:1] -; GFX9-NEXT: s_sub_i32 s4, 64, 63 -; GFX9-NEXT: v_lshlrev_b64 v[0:1], s4, v[6:7] -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v7 -; GFX9-NEXT: v_lshrrev_b32_e32 v5, 31, v5 -; GFX9-NEXT: v_or_b32_e32 v0, v5, v0 +; GFX9-NEXT: s_movk_i32 s4, 0x41 +; GFX9-NEXT: s_sub_i32 s6, 64, s4 +; GFX9-NEXT: s_sub_i32 s5, s4, 64 +; GFX9-NEXT: s_cmp_lt_u32 s4, 64 +; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s4, 0 +; GFX9-NEXT: v_lshrrev_b64 v[8:9], s6, v[0:1] +; GFX9-NEXT: v_lshlrev_b64 v[10:11], s4, v[2:3] +; GFX9-NEXT: v_lshlrev_b64 v[12:13], s4, v[0:1] +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] +; GFX9-NEXT: s_and_b32 s4, 1, s7 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_or_b32_e32 v8, v8, v10 +; GFX9-NEXT: v_or_b32_e32 v9, v9, v11 +; GFX9-NEXT: s_and_b32 s4, 1, s8 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_sub_i32 s4, 63, 64 +; GFX9-NEXT: s_sub_i32 s5, 64, 63 +; GFX9-NEXT: s_cmp_lt_u32 63, 64 +; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 63, 0 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc +; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[6:7] +; GFX9-NEXT: v_lshrrev_b32_e32 v8, 31, v7 +; GFX9-NEXT: v_lshrrev_b32_e32 v9, 31, v5 +; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: v_lshrrev_b64 v[6:7], s4, v[6:7] +; GFX9-NEXT: s_and_b32 s4, 1, s6 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_or_b32_e32 v0, v9, v0 +; GFX9-NEXT: s_and_b32 s4, 1, s7 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_and_b32 s4, 1, s6 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX9-NEXT: v_or_b32_e32 v0, v10, v0 +; GFX9-NEXT: v_or_b32_e32 v1, v11, v1 ; GFX9-NEXT: v_or_b32_e32 v2, v2, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -5899,14 +6409,52 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_sub_i32 s4, 0x41, 64 +; GFX10-NEXT: s_movk_i32 s4, 0x41 +; GFX10-NEXT: v_lshrrev_b32_e32 v16, 31, v5 +; GFX10-NEXT: s_sub_i32 s5, 64, s4 +; GFX10-NEXT: v_lshlrev_b64 v[10:11], s4, v[2:3] +; GFX10-NEXT: v_lshrrev_b64 v[8:9], s5, v[0:1] +; GFX10-NEXT: s_sub_i32 s5, s4, 64 +; GFX10-NEXT: s_cmp_lt_u32 s4, 64 +; GFX10-NEXT: v_lshlrev_b64 v[12:13], s4, v[0:1] +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s4, 0 +; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: s_sub_i32 s5, 64, 63 -; GFX10-NEXT: v_lshlrev_b64 v[2:3], s4, v[0:1] -; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[6:7] -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 31, v7 -; GFX10-NEXT: v_or_b32_e32 v0, v4, v0 -; GFX10-NEXT: v_or_b32_e32 v2, v2, v5 +; GFX10-NEXT: v_or_b32_e32 v14, v8, v10 +; GFX10-NEXT: v_or_b32_e32 v15, v9, v11 +; GFX10-NEXT: v_lshlrev_b64 v[8:9], s5, v[6:7] +; GFX10-NEXT: s_and_b32 s6, 1, vcc_lo +; GFX10-NEXT: s_and_b32 s7, 1, s4 +; GFX10-NEXT: s_sub_i32 s4, 63, 64 +; GFX10-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6 +; GFX10-NEXT: v_lshrrev_b64 v[10:11], s4, v[6:7] +; GFX10-NEXT: s_cmp_lt_u32 63, 64 +; GFX10-NEXT: v_or_b32_e32 v6, v16, v8 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 63, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 s6, 0, s7 +; GFX10-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v6, s4 +; GFX10-NEXT: s_and_b32 s5, 1, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v8, v11, v9, s4 +; GFX10-NEXT: s_and_b32 s4, 1, s4 +; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v0, v2, s6 +; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v7 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v1, v15, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v4, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v8, v5, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v0, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s6 +; GFX10-NEXT: v_or_b32_e32 v0, v12, v4 +; GFX10-NEXT: v_or_b32_e32 v1, v13, v5 +; GFX10-NEXT: v_or_b32_e32 v2, v2, v6 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65) ret i128 %result @@ -5935,27 +6483,39 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX6-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1] ; GFX6-NEXT: s_cmp_lg_u32 s29, 0 ; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX6-NEXT: s_sub_i32 s26, 64, 1 +; GFX6-NEXT: s_sub_i32 s28, 1, 64 +; GFX6-NEXT: s_sub_i32 s29, 64, 1 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s17, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s30, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[22:23], s[8:9], 1 +; GFX6-NEXT: s_lshl_b64 s[26:27], s[10:11], s29 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[10:11], 1 -; GFX6-NEXT: s_lshr_b64 s[8:9], s[8:9], 1 -; GFX6-NEXT: s_lshl_b64 s[10:11], s[10:11], s26 -; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] -; GFX6-NEXT: s_sub_i32 s27, s16, 64 +; GFX6-NEXT: s_or_b64 s[22:23], s[22:23], s[26:27] +; GFX6-NEXT: s_lshr_b64 s[10:11], s[10:11], s28 +; GFX6-NEXT: s_cmp_lg_u32 s17, 0 +; GFX6-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11] +; GFX6-NEXT: s_cmp_lg_u32 s30, 0 +; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] +; GFX6-NEXT: s_cmp_lg_u32 s17, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 +; GFX6-NEXT: s_sub_i32 s26, s16, 64 ; GFX6-NEXT: s_sub_i32 s22, 64, s16 ; GFX6-NEXT: s_cmp_lt_u32 s16, 64 -; GFX6-NEXT: s_cselect_b32 s28, 1, 0 +; GFX6-NEXT: s_cselect_b32 s27, 1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s16, 0 -; GFX6-NEXT: s_cselect_b32 s29, 1, 0 +; GFX6-NEXT: s_cselect_b32 s30, 1, 0 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[0:1], s16 ; GFX6-NEXT: s_lshl_b64 s[22:23], s[0:1], s22 ; GFX6-NEXT: s_lshr_b64 s[16:17], s[8:9], s16 ; GFX6-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23] -; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s27 -; GFX6-NEXT: s_cmp_lg_u32 s28, 0 +; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s26 +; GFX6-NEXT: s_cmp_lg_u32 s27, 0 ; GFX6-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1] -; GFX6-NEXT: s_cmp_lg_u32 s29, 0 +; GFX6-NEXT: s_cmp_lg_u32 s30, 0 ; GFX6-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] -; GFX6-NEXT: s_cmp_lg_u32 s28, 0 +; GFX6-NEXT: s_cmp_lg_u32 s27, 0 ; GFX6-NEXT: s_cselect_b64 s[8:9], s[10:11], 0 ; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX6-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] @@ -5977,10 +6537,21 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX6-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5] ; GFX6-NEXT: s_cmp_lg_u32 s21, 0 ; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s11, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s20, 1, 0 ; GFX6-NEXT: s_lshr_b64 s[8:9], s[12:13], 1 -; GFX6-NEXT: s_lshl_b64 s[12:13], s[14:15], s26 +; GFX6-NEXT: s_lshl_b64 s[18:19], s[14:15], s29 ; GFX6-NEXT: s_lshr_b64 s[4:5], s[14:15], 1 -; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13] +; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[18:19] +; GFX6-NEXT: s_lshr_b64 s[14:15], s[14:15], s28 +; GFX6-NEXT: s_cmp_lg_u32 s11, 0 +; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], s[14:15] +; GFX6-NEXT: s_cmp_lg_u32 s20, 0 +; GFX6-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9] +; GFX6-NEXT: s_cmp_lg_u32 s11, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], 0 ; GFX6-NEXT: s_sub_i32 s18, s10, 64 ; GFX6-NEXT: s_sub_i32 s14, 64, s10 ; GFX6-NEXT: s_cmp_lt_u32 s10, 64 @@ -6024,27 +6595,39 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX8-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1] ; GFX8-NEXT: s_cmp_lg_u32 s29, 0 ; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX8-NEXT: s_sub_i32 s26, 64, 1 +; GFX8-NEXT: s_sub_i32 s28, 1, 64 +; GFX8-NEXT: s_sub_i32 s29, 64, 1 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s17, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s30, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[22:23], s[8:9], 1 +; GFX8-NEXT: s_lshl_b64 s[26:27], s[10:11], s29 ; GFX8-NEXT: s_lshr_b64 s[0:1], s[10:11], 1 -; GFX8-NEXT: s_lshr_b64 s[8:9], s[8:9], 1 -; GFX8-NEXT: s_lshl_b64 s[10:11], s[10:11], s26 -; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] -; GFX8-NEXT: s_sub_i32 s27, s16, 64 +; GFX8-NEXT: s_or_b64 s[22:23], s[22:23], s[26:27] +; GFX8-NEXT: s_lshr_b64 s[10:11], s[10:11], s28 +; GFX8-NEXT: s_cmp_lg_u32 s17, 0 +; GFX8-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11] +; GFX8-NEXT: s_cmp_lg_u32 s30, 0 +; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] +; GFX8-NEXT: s_cmp_lg_u32 s17, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 +; GFX8-NEXT: s_sub_i32 s26, s16, 64 ; GFX8-NEXT: s_sub_i32 s22, 64, s16 ; GFX8-NEXT: s_cmp_lt_u32 s16, 64 -; GFX8-NEXT: s_cselect_b32 s28, 1, 0 +; GFX8-NEXT: s_cselect_b32 s27, 1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s16, 0 -; GFX8-NEXT: s_cselect_b32 s29, 1, 0 +; GFX8-NEXT: s_cselect_b32 s30, 1, 0 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[0:1], s16 ; GFX8-NEXT: s_lshl_b64 s[22:23], s[0:1], s22 ; GFX8-NEXT: s_lshr_b64 s[16:17], s[8:9], s16 ; GFX8-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23] -; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s27 -; GFX8-NEXT: s_cmp_lg_u32 s28, 0 +; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s26 +; GFX8-NEXT: s_cmp_lg_u32 s27, 0 ; GFX8-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1] -; GFX8-NEXT: s_cmp_lg_u32 s29, 0 +; GFX8-NEXT: s_cmp_lg_u32 s30, 0 ; GFX8-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] -; GFX8-NEXT: s_cmp_lg_u32 s28, 0 +; GFX8-NEXT: s_cmp_lg_u32 s27, 0 ; GFX8-NEXT: s_cselect_b64 s[8:9], s[10:11], 0 ; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX8-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] @@ -6066,10 +6649,21 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX8-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5] ; GFX8-NEXT: s_cmp_lg_u32 s21, 0 ; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s11, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s20, 1, 0 ; GFX8-NEXT: s_lshr_b64 s[8:9], s[12:13], 1 -; GFX8-NEXT: s_lshl_b64 s[12:13], s[14:15], s26 +; GFX8-NEXT: s_lshl_b64 s[18:19], s[14:15], s29 ; GFX8-NEXT: s_lshr_b64 s[4:5], s[14:15], 1 -; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13] +; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[18:19] +; GFX8-NEXT: s_lshr_b64 s[14:15], s[14:15], s28 +; GFX8-NEXT: s_cmp_lg_u32 s11, 0 +; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[14:15] +; GFX8-NEXT: s_cmp_lg_u32 s20, 0 +; GFX8-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9] +; GFX8-NEXT: s_cmp_lg_u32 s11, 0 +; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], 0 ; GFX8-NEXT: s_sub_i32 s18, s10, 64 ; GFX8-NEXT: s_sub_i32 s14, 64, s10 ; GFX8-NEXT: s_cmp_lt_u32 s10, 64 @@ -6113,27 +6707,39 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX9-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1] ; GFX9-NEXT: s_cmp_lg_u32 s29, 0 ; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX9-NEXT: s_sub_i32 s26, 64, 1 +; GFX9-NEXT: s_sub_i32 s28, 1, 64 +; GFX9-NEXT: s_sub_i32 s29, 64, 1 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s17, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s30, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[22:23], s[8:9], 1 +; GFX9-NEXT: s_lshl_b64 s[26:27], s[10:11], s29 ; GFX9-NEXT: s_lshr_b64 s[0:1], s[10:11], 1 -; GFX9-NEXT: s_lshr_b64 s[8:9], s[8:9], 1 -; GFX9-NEXT: s_lshl_b64 s[10:11], s[10:11], s26 -; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] -; GFX9-NEXT: s_sub_i32 s27, s16, 64 +; GFX9-NEXT: s_or_b64 s[22:23], s[22:23], s[26:27] +; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], s28 +; GFX9-NEXT: s_cmp_lg_u32 s17, 0 +; GFX9-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11] +; GFX9-NEXT: s_cmp_lg_u32 s30, 0 +; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] +; GFX9-NEXT: s_cmp_lg_u32 s17, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 +; GFX9-NEXT: s_sub_i32 s26, s16, 64 ; GFX9-NEXT: s_sub_i32 s22, 64, s16 ; GFX9-NEXT: s_cmp_lt_u32 s16, 64 -; GFX9-NEXT: s_cselect_b32 s28, 1, 0 +; GFX9-NEXT: s_cselect_b32 s27, 1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s16, 0 -; GFX9-NEXT: s_cselect_b32 s29, 1, 0 +; GFX9-NEXT: s_cselect_b32 s30, 1, 0 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[0:1], s16 ; GFX9-NEXT: s_lshl_b64 s[22:23], s[0:1], s22 ; GFX9-NEXT: s_lshr_b64 s[16:17], s[8:9], s16 ; GFX9-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23] -; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s27 -; GFX9-NEXT: s_cmp_lg_u32 s28, 0 +; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s26 +; GFX9-NEXT: s_cmp_lg_u32 s27, 0 ; GFX9-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1] -; GFX9-NEXT: s_cmp_lg_u32 s29, 0 +; GFX9-NEXT: s_cmp_lg_u32 s30, 0 ; GFX9-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] -; GFX9-NEXT: s_cmp_lg_u32 s28, 0 +; GFX9-NEXT: s_cmp_lg_u32 s27, 0 ; GFX9-NEXT: s_cselect_b64 s[8:9], s[10:11], 0 ; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX9-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] @@ -6155,10 +6761,21 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX9-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5] ; GFX9-NEXT: s_cmp_lg_u32 s21, 0 ; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s20, 1, 0 ; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], 1 -; GFX9-NEXT: s_lshl_b64 s[12:13], s[14:15], s26 +; GFX9-NEXT: s_lshl_b64 s[18:19], s[14:15], s29 ; GFX9-NEXT: s_lshr_b64 s[4:5], s[14:15], 1 -; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13] +; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[18:19] +; GFX9-NEXT: s_lshr_b64 s[14:15], s[14:15], s28 +; GFX9-NEXT: s_cmp_lg_u32 s11, 0 +; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], s[14:15] +; GFX9-NEXT: s_cmp_lg_u32 s20, 0 +; GFX9-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9] +; GFX9-NEXT: s_cmp_lg_u32 s11, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], 0 ; GFX9-NEXT: s_sub_i32 s18, s10, 64 ; GFX9-NEXT: s_sub_i32 s14, 64, s10 ; GFX9-NEXT: s_cmp_lt_u32 s10, 64 @@ -6202,27 +6819,39 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX10-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1] ; GFX10-NEXT: s_cmp_lg_u32 s29, 0 ; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX10-NEXT: s_sub_i32 s26, 64, 1 +; GFX10-NEXT: s_sub_i32 s28, 1, 64 +; GFX10-NEXT: s_sub_i32 s29, 64, 1 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: s_cselect_b32 s30, 1, 0 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[8:9], 1 -; GFX10-NEXT: s_lshl_b64 s[8:9], s[10:11], s26 -; GFX10-NEXT: s_lshr_b64 s[10:11], s[10:11], 1 -; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] -; GFX10-NEXT: s_sub_i32 s27, s16, 64 +; GFX10-NEXT: s_lshl_b64 s[24:25], s[10:11], s29 +; GFX10-NEXT: s_lshr_b64 s[26:27], s[10:11], 1 +; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[24:25] +; GFX10-NEXT: s_lshr_b64 s[10:11], s[10:11], s28 +; GFX10-NEXT: s_cmp_lg_u32 s17, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11] +; GFX10-NEXT: s_cmp_lg_u32 s30, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] +; GFX10-NEXT: s_cmp_lg_u32 s17, 0 +; GFX10-NEXT: s_cselect_b64 s[8:9], s[26:27], 0 +; GFX10-NEXT: s_sub_i32 s26, s16, 64 ; GFX10-NEXT: s_sub_i32 s17, 64, s16 ; GFX10-NEXT: s_cmp_lt_u32 s16, 64 -; GFX10-NEXT: s_cselect_b32 s28, 1, 0 +; GFX10-NEXT: s_cselect_b32 s27, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s16, 0 -; GFX10-NEXT: s_cselect_b32 s29, 1, 0 -; GFX10-NEXT: s_lshr_b64 s[8:9], s[0:1], s16 -; GFX10-NEXT: s_lshl_b64 s[24:25], s[10:11], s17 -; GFX10-NEXT: s_lshr_b64 s[16:17], s[10:11], s16 -; GFX10-NEXT: s_or_b64 s[8:9], s[8:9], s[24:25] -; GFX10-NEXT: s_lshr_b64 s[10:11], s[10:11], s27 -; GFX10-NEXT: s_cmp_lg_u32 s28, 0 -; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] -; GFX10-NEXT: s_cmp_lg_u32 s29, 0 +; GFX10-NEXT: s_cselect_b32 s30, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s16 +; GFX10-NEXT: s_lshl_b64 s[24:25], s[8:9], s17 +; GFX10-NEXT: s_lshr_b64 s[16:17], s[8:9], s16 +; GFX10-NEXT: s_or_b64 s[10:11], s[10:11], s[24:25] +; GFX10-NEXT: s_lshr_b64 s[8:9], s[8:9], s26 +; GFX10-NEXT: s_cmp_lg_u32 s27, 0 +; GFX10-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9] +; GFX10-NEXT: s_cmp_lg_u32 s30, 0 ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] -; GFX10-NEXT: s_cmp_lg_u32 s28, 0 +; GFX10-NEXT: s_cmp_lg_u32 s27, 0 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[16:17], 0 ; GFX10-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] @@ -6244,23 +6873,34 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX10-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5] ; GFX10-NEXT: s_cmp_lg_u32 s21, 0 ; GFX10-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: s_cselect_b32 s11, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[12:13], 1 -; GFX10-NEXT: s_lshl_b64 s[12:13], s[14:15], s26 -; GFX10-NEXT: s_lshr_b64 s[14:15], s[14:15], 1 -; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13] +; GFX10-NEXT: s_lshl_b64 s[16:17], s[14:15], s29 +; GFX10-NEXT: s_lshr_b64 s[18:19], s[14:15], 1 +; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[16:17] +; GFX10-NEXT: s_lshr_b64 s[14:15], s[14:15], s28 +; GFX10-NEXT: s_cmp_lg_u32 s11, 0 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[14:15] +; GFX10-NEXT: s_cmp_lg_u32 s20, 0 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[12:13], s[4:5] +; GFX10-NEXT: s_cmp_lg_u32 s11, 0 +; GFX10-NEXT: s_cselect_b64 s[12:13], s[18:19], 0 ; GFX10-NEXT: s_sub_i32 s18, s10, 64 ; GFX10-NEXT: s_sub_i32 s11, 64, s10 ; GFX10-NEXT: s_cmp_lt_u32 s10, 64 ; GFX10-NEXT: s_cselect_b32 s19, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s10, 0 ; GFX10-NEXT: s_cselect_b32 s20, 1, 0 -; GFX10-NEXT: s_lshr_b64 s[12:13], s[4:5], s10 -; GFX10-NEXT: s_lshl_b64 s[16:17], s[14:15], s11 -; GFX10-NEXT: s_lshr_b64 s[10:11], s[14:15], s10 -; GFX10-NEXT: s_or_b64 s[12:13], s[12:13], s[16:17] -; GFX10-NEXT: s_lshr_b64 s[14:15], s[14:15], s18 +; GFX10-NEXT: s_lshr_b64 s[14:15], s[4:5], s10 +; GFX10-NEXT: s_lshl_b64 s[16:17], s[12:13], s11 +; GFX10-NEXT: s_lshr_b64 s[10:11], s[12:13], s10 +; GFX10-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] +; GFX10-NEXT: s_lshr_b64 s[12:13], s[12:13], s18 ; GFX10-NEXT: s_cmp_lg_u32 s19, 0 -; GFX10-NEXT: s_cselect_b64 s[12:13], s[12:13], s[14:15] +; GFX10-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13] ; GFX10-NEXT: s_cmp_lg_u32 s20, 0 ; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[12:13] ; GFX10-NEXT: s_cmp_lg_u32 s19, 0 @@ -6276,24 +6916,40 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX6-LABEL: v_fshl_v2i128: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: s_sub_i32 s6, 64, 1 -; GFX6-NEXT: v_lshl_b64 v[17:18], v[10:11], s6 -; GFX6-NEXT: v_lshr_b64 v[8:9], v[8:9], 1 -; GFX6-NEXT: s_movk_i32 s7, 0x7f -; GFX6-NEXT: v_and_b32_e32 v23, s7, v16 -; GFX6-NEXT: v_or_b32_e32 v8, v8, v17 -; GFX6-NEXT: v_xor_b32_e32 v16, -1, v16 +; GFX6-NEXT: s_movk_i32 s6, 0x7f +; GFX6-NEXT: v_and_b32_e32 v23, s6, v16 ; GFX6-NEXT: v_sub_i32_e32 v17, vcc, 64, v23 -; GFX6-NEXT: v_and_b32_e32 v24, s7, v16 -; GFX6-NEXT: v_or_b32_e32 v9, v9, v18 ; GFX6-NEXT: v_lshr_b64 v[17:18], v[0:1], v17 ; GFX6-NEXT: v_lshl_b64 v[21:22], v[2:3], v23 +; GFX6-NEXT: s_sub_i32 s7, 64, 1 +; GFX6-NEXT: s_sub_i32 s8, 1, 64 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: v_or_b32_e32 v24, v17, v21 +; GFX6-NEXT: v_or_b32_e32 v25, v18, v22 +; GFX6-NEXT: v_lshr_b64 v[17:18], v[8:9], 1 +; GFX6-NEXT: v_lshl_b64 v[21:22], v[10:11], s7 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: v_or_b32_e32 v19, v17, v21 +; GFX6-NEXT: v_or_b32_e32 v21, v18, v22 +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_and_b32 s4, 1, s4 +; GFX6-NEXT: v_lshr_b64 v[17:18], v[10:11], s8 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_and_b32 s4, 1, s5 ; GFX6-NEXT: v_lshr_b64 v[10:11], v[10:11], 1 -; GFX6-NEXT: v_sub_i32_e32 v16, vcc, 64, v24 -; GFX6-NEXT: v_or_b32_e32 v21, v17, v21 -; GFX6-NEXT: v_or_b32_e32 v22, v18, v22 +; GFX6-NEXT: v_xor_b32_e32 v16, -1, v16 +; GFX6-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc +; GFX6-NEXT: v_and_b32_e32 v21, s6, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v8, v17, v8, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e64 v9, v18, v9, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc +; GFX6-NEXT: v_sub_i32_e32 v16, vcc, 64, v21 ; GFX6-NEXT: v_lshl_b64 v[16:17], v[10:11], v16 -; GFX6-NEXT: v_lshr_b64 v[18:19], v[8:9], v24 +; GFX6-NEXT: v_lshr_b64 v[18:19], v[8:9], v21 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v23 ; GFX6-NEXT: v_or_b32_e32 v18, v18, v16 ; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, 64, v23 @@ -6301,30 +6957,30 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX6-NEXT: v_lshl_b64 v[16:17], v[0:1], v16 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v23 ; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23 -; GFX6-NEXT: v_cndmask_b32_e32 v25, 0, v0, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v21, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v16, v17, v22, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v22, 0, v0, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v24, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v16, v17, v25, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v17, v0, v2, s[4:5] ; GFX6-NEXT: v_cndmask_b32_e64 v16, v16, v3, s[4:5] -; GFX6-NEXT: v_subrev_i32_e64 v0, s[4:5], 64, v24 +; GFX6-NEXT: v_subrev_i32_e64 v0, s[4:5], 64, v21 ; GFX6-NEXT: v_lshr_b64 v[2:3], v[10:11], v0 -; GFX6-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v24 +; GFX6-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v21 ; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v18, s[4:5] ; GFX6-NEXT: v_cndmask_b32_e32 v18, 0, v1, vcc -; GFX6-NEXT: v_lshr_b64 v[0:1], v[10:11], v24 -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[10:11], v21 +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v21 ; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v19, s[4:5] ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, v0, s[4:5] ; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, v1, s[4:5] -; GFX6-NEXT: v_or_b32_e32 v0, v25, v2 +; GFX6-NEXT: v_or_b32_e32 v0, v22, v2 ; GFX6-NEXT: v_or_b32_e32 v1, v18, v3 ; GFX6-NEXT: v_or_b32_e32 v2, v17, v8 ; GFX6-NEXT: v_or_b32_e32 v3, v16, v9 -; GFX6-NEXT: v_and_b32_e32 v16, s7, v20 +; GFX6-NEXT: v_and_b32_e32 v16, s6, v20 ; GFX6-NEXT: v_xor_b32_e32 v8, -1, v20 -; GFX6-NEXT: v_and_b32_e32 v17, s7, v8 +; GFX6-NEXT: v_and_b32_e32 v17, s6, v8 ; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v16 ; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], v8 ; GFX6-NEXT: v_lshl_b64 v[10:11], v[6:7], v16 @@ -6339,29 +6995,46 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 ; GFX6-NEXT: v_cndmask_b32_e32 v16, v4, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v20, v5, v7, vcc ; GFX6-NEXT: v_lshr_b64 v[4:5], v[12:13], 1 -; GFX6-NEXT: v_lshl_b64 v[6:7], v[14:15], s6 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[14:15], s7 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_and_b32 s6, 1, s4 +; GFX6-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX6-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX6-NEXT: v_lshr_b64 v[4:5], v[14:15], s8 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 +; GFX6-NEXT: s_and_b32 s5, 1, s5 ; GFX6-NEXT: v_lshr_b64 v[8:9], v[14:15], 1 +; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX6-NEXT: s_and_b32 s4, 1, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 64, v17 -; GFX6-NEXT: v_or_b32_e32 v4, v4, v6 -; GFX6-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX6-NEXT: v_lshr_b64 v[6:7], v[4:5], v17 -; GFX6-NEXT: v_lshl_b64 v[10:11], v[8:9], v10 +; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], v17 +; GFX6-NEXT: v_lshl_b64 v[10:11], v[6:7], v10 ; GFX6-NEXT: v_subrev_i32_e32 v12, vcc, 64, v17 -; GFX6-NEXT: v_or_b32_e32 v10, v6, v10 -; GFX6-NEXT: v_or_b32_e32 v11, v7, v11 -; GFX6-NEXT: v_lshr_b64 v[6:7], v[8:9], v17 -; GFX6-NEXT: v_lshr_b64 v[8:9], v[8:9], v12 +; GFX6-NEXT: v_or_b32_e32 v10, v8, v10 +; GFX6-NEXT: v_or_b32_e32 v11, v9, v11 +; GFX6-NEXT: v_lshr_b64 v[8:9], v[6:7], v17 +; GFX6-NEXT: v_lshr_b64 v[6:7], v[6:7], v12 ; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17 -; GFX6-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc ; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v17 -; GFX6-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc -; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX6-NEXT: v_or_b32_e32 v4, v18, v4 ; GFX6-NEXT: v_or_b32_e32 v5, v19, v5 ; GFX6-NEXT: v_or_b32_e32 v6, v16, v6 @@ -6371,24 +7044,40 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX8-LABEL: v_fshl_v2i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: s_sub_i32 s6, 64, 1 -; GFX8-NEXT: v_lshlrev_b64 v[17:18], s6, v[10:11] -; GFX8-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9] -; GFX8-NEXT: s_movk_i32 s7, 0x7f -; GFX8-NEXT: v_and_b32_e32 v23, s7, v16 -; GFX8-NEXT: v_or_b32_e32 v8, v8, v17 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v16 +; GFX8-NEXT: s_movk_i32 s6, 0x7f +; GFX8-NEXT: v_and_b32_e32 v23, s6, v16 ; GFX8-NEXT: v_sub_u32_e32 v17, vcc, 64, v23 -; GFX8-NEXT: v_and_b32_e32 v24, s7, v16 -; GFX8-NEXT: v_or_b32_e32 v9, v9, v18 ; GFX8-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1] ; GFX8-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3] +; GFX8-NEXT: s_sub_i32 s7, 64, 1 +; GFX8-NEXT: s_sub_i32 s8, 1, 64 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: v_or_b32_e32 v24, v17, v21 +; GFX8-NEXT: v_or_b32_e32 v25, v18, v22 +; GFX8-NEXT: v_lshrrev_b64 v[17:18], 1, v[8:9] +; GFX8-NEXT: v_lshlrev_b64 v[21:22], s7, v[10:11] +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: v_or_b32_e32 v19, v17, v21 +; GFX8-NEXT: v_or_b32_e32 v21, v18, v22 +; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_and_b32 s4, 1, s4 +; GFX8-NEXT: v_lshrrev_b64 v[17:18], s8, v[10:11] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_and_b32 s4, 1, s5 ; GFX8-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11] -; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v24 -; GFX8-NEXT: v_or_b32_e32 v21, v17, v21 -; GFX8-NEXT: v_or_b32_e32 v22, v18, v22 +; GFX8-NEXT: v_xor_b32_e32 v16, -1, v16 +; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc +; GFX8-NEXT: v_and_b32_e32 v21, s6, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v8, v17, v8, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e64 v9, v18, v9, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc +; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v21 ; GFX8-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11] -; GFX8-NEXT: v_lshrrev_b64 v[18:19], v24, v[8:9] +; GFX8-NEXT: v_lshrrev_b64 v[18:19], v21, v[8:9] ; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v23 ; GFX8-NEXT: v_or_b32_e32 v18, v18, v16 ; GFX8-NEXT: v_subrev_u32_e32 v16, vcc, 64, v23 @@ -6396,30 +7085,30 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX8-NEXT: v_lshlrev_b64 v[16:17], v16, v[0:1] ; GFX8-NEXT: v_lshlrev_b64 v[0:1], v23, v[0:1] ; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v25, 0, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v21, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v16, v17, v22, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v22, 0, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v24, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v16, v17, v25, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v17, v0, v2, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, v3, s[4:5] -; GFX8-NEXT: v_subrev_u32_e64 v0, s[4:5], 64, v24 +; GFX8-NEXT: v_subrev_u32_e64 v0, s[4:5], 64, v21 ; GFX8-NEXT: v_lshrrev_b64 v[2:3], v0, v[10:11] -; GFX8-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v24 +; GFX8-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v21 ; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v18, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e32 v18, 0, v1, vcc -; GFX8-NEXT: v_lshrrev_b64 v[0:1], v24, v[10:11] -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], v21, v[10:11] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v21 ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v19, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v0, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, v1, s[4:5] -; GFX8-NEXT: v_or_b32_e32 v0, v25, v2 +; GFX8-NEXT: v_or_b32_e32 v0, v22, v2 ; GFX8-NEXT: v_or_b32_e32 v1, v18, v3 ; GFX8-NEXT: v_or_b32_e32 v2, v17, v8 ; GFX8-NEXT: v_or_b32_e32 v3, v16, v9 -; GFX8-NEXT: v_and_b32_e32 v16, s7, v20 +; GFX8-NEXT: v_and_b32_e32 v16, s6, v20 ; GFX8-NEXT: v_xor_b32_e32 v8, -1, v20 -; GFX8-NEXT: v_and_b32_e32 v17, s7, v8 +; GFX8-NEXT: v_and_b32_e32 v17, s6, v8 ; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v16 ; GFX8-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5] ; GFX8-NEXT: v_lshlrev_b64 v[10:11], v16, v[6:7] @@ -6434,29 +7123,46 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 ; GFX8-NEXT: v_cndmask_b32_e32 v16, v4, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v20, v5, v7, vcc ; GFX8-NEXT: v_lshrrev_b64 v[4:5], 1, v[12:13] -; GFX8-NEXT: v_lshlrev_b64 v[6:7], s6, v[14:15] +; GFX8-NEXT: v_lshlrev_b64 v[6:7], s7, v[14:15] +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_and_b32 s6, 1, s4 +; GFX8-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX8-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX8-NEXT: v_lshrrev_b64 v[4:5], s8, v[14:15] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 +; GFX8-NEXT: s_and_b32 s5, 1, s5 ; GFX8-NEXT: v_lshrrev_b64 v[8:9], 1, v[14:15] +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX8-NEXT: s_and_b32 s4, 1, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 64, v17 -; GFX8-NEXT: v_or_b32_e32 v4, v4, v6 -; GFX8-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX8-NEXT: v_lshrrev_b64 v[6:7], v17, v[4:5] -; GFX8-NEXT: v_lshlrev_b64 v[10:11], v10, v[8:9] +; GFX8-NEXT: v_lshrrev_b64 v[8:9], v17, v[4:5] +; GFX8-NEXT: v_lshlrev_b64 v[10:11], v10, v[6:7] ; GFX8-NEXT: v_subrev_u32_e32 v12, vcc, 64, v17 -; GFX8-NEXT: v_or_b32_e32 v10, v6, v10 -; GFX8-NEXT: v_or_b32_e32 v11, v7, v11 -; GFX8-NEXT: v_lshrrev_b64 v[6:7], v17, v[8:9] -; GFX8-NEXT: v_lshrrev_b64 v[8:9], v12, v[8:9] +; GFX8-NEXT: v_or_b32_e32 v10, v8, v10 +; GFX8-NEXT: v_or_b32_e32 v11, v9, v11 +; GFX8-NEXT: v_lshrrev_b64 v[8:9], v17, v[6:7] +; GFX8-NEXT: v_lshrrev_b64 v[6:7], v12, v[6:7] ; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc ; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX8-NEXT: v_or_b32_e32 v4, v18, v4 ; GFX8-NEXT: v_or_b32_e32 v5, v19, v5 ; GFX8-NEXT: v_or_b32_e32 v6, v16, v6 @@ -6466,24 +7172,40 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX9-LABEL: v_fshl_v2i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_sub_i32 s6, 64, 1 -; GFX9-NEXT: v_lshlrev_b64 v[17:18], s6, v[10:11] -; GFX9-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9] -; GFX9-NEXT: s_movk_i32 s7, 0x7f -; GFX9-NEXT: v_and_b32_e32 v23, s7, v16 -; GFX9-NEXT: v_or_b32_e32 v8, v8, v17 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v16 +; GFX9-NEXT: s_movk_i32 s6, 0x7f +; GFX9-NEXT: v_and_b32_e32 v23, s6, v16 ; GFX9-NEXT: v_sub_u32_e32 v17, 64, v23 -; GFX9-NEXT: v_and_b32_e32 v24, s7, v16 -; GFX9-NEXT: v_or_b32_e32 v9, v9, v18 ; GFX9-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3] +; GFX9-NEXT: s_sub_i32 s7, 64, 1 +; GFX9-NEXT: s_sub_i32 s8, 1, 64 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: v_or_b32_e32 v24, v17, v21 +; GFX9-NEXT: v_or_b32_e32 v25, v18, v22 +; GFX9-NEXT: v_lshrrev_b64 v[17:18], 1, v[8:9] +; GFX9-NEXT: v_lshlrev_b64 v[21:22], s7, v[10:11] +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: v_or_b32_e32 v19, v17, v21 +; GFX9-NEXT: v_or_b32_e32 v21, v18, v22 +; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_and_b32 s4, 1, s4 +; GFX9-NEXT: v_lshrrev_b64 v[17:18], s8, v[10:11] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_and_b32 s4, 1, s5 ; GFX9-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11] -; GFX9-NEXT: v_sub_u32_e32 v16, 64, v24 -; GFX9-NEXT: v_or_b32_e32 v21, v17, v21 -; GFX9-NEXT: v_or_b32_e32 v22, v18, v22 +; GFX9-NEXT: v_xor_b32_e32 v16, -1, v16 +; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc +; GFX9-NEXT: v_and_b32_e32 v21, s6, v16 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v8, v17, v8, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e64 v9, v18, v9, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc +; GFX9-NEXT: v_sub_u32_e32 v16, 64, v21 ; GFX9-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11] -; GFX9-NEXT: v_lshrrev_b64 v[18:19], v24, v[8:9] +; GFX9-NEXT: v_lshrrev_b64 v[18:19], v21, v[8:9] ; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23 ; GFX9-NEXT: v_or_b32_e32 v18, v18, v16 ; GFX9-NEXT: v_subrev_u32_e32 v16, 64, v23 @@ -6491,30 +7213,30 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX9-NEXT: v_lshlrev_b64 v[16:17], v16, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[0:1], v23, v[0:1] ; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v23 -; GFX9-NEXT: v_cndmask_b32_e32 v25, 0, v0, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v21, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v22, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v22, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v24, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v25, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v17, v0, v2, s[4:5] -; GFX9-NEXT: v_subrev_u32_e32 v0, 64, v24 +; GFX9-NEXT: v_subrev_u32_e32 v0, 64, v21 ; GFX9-NEXT: v_cndmask_b32_e64 v16, v16, v3, s[4:5] ; GFX9-NEXT: v_lshrrev_b64 v[2:3], v0, v[10:11] -; GFX9-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v24 +; GFX9-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v21 ; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v18, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v1, vcc -; GFX9-NEXT: v_lshrrev_b64 v[0:1], v24, v[10:11] -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], v21, v[10:11] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v21 ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v19, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v0, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, v1, s[4:5] -; GFX9-NEXT: v_or_b32_e32 v0, v25, v2 +; GFX9-NEXT: v_or_b32_e32 v0, v22, v2 ; GFX9-NEXT: v_or_b32_e32 v1, v18, v3 ; GFX9-NEXT: v_or_b32_e32 v2, v17, v8 ; GFX9-NEXT: v_or_b32_e32 v3, v16, v9 -; GFX9-NEXT: v_and_b32_e32 v16, s7, v20 +; GFX9-NEXT: v_and_b32_e32 v16, s6, v20 ; GFX9-NEXT: v_xor_b32_e32 v8, -1, v20 -; GFX9-NEXT: v_and_b32_e32 v17, s7, v8 +; GFX9-NEXT: v_and_b32_e32 v17, s6, v8 ; GFX9-NEXT: v_sub_u32_e32 v8, 64, v16 ; GFX9-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5] ; GFX9-NEXT: v_lshlrev_b64 v[10:11], v16, v[6:7] @@ -6529,29 +7251,46 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX9-NEXT: v_cndmask_b32_e32 v19, 0, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 ; GFX9-NEXT: v_cndmask_b32_e32 v16, v4, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v20, v5, v7, vcc ; GFX9-NEXT: v_lshrrev_b64 v[4:5], 1, v[12:13] -; GFX9-NEXT: v_lshlrev_b64 v[6:7], s6, v[14:15] +; GFX9-NEXT: v_lshlrev_b64 v[6:7], s7, v[14:15] +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_and_b32 s6, 1, s4 +; GFX9-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX9-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX9-NEXT: v_lshrrev_b64 v[4:5], s8, v[14:15] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 +; GFX9-NEXT: s_and_b32 s5, 1, s5 ; GFX9-NEXT: v_lshrrev_b64 v[8:9], 1, v[14:15] +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX9-NEXT: s_and_b32 s4, 1, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX9-NEXT: v_sub_u32_e32 v10, 64, v17 -; GFX9-NEXT: v_or_b32_e32 v4, v4, v6 -; GFX9-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX9-NEXT: v_lshrrev_b64 v[6:7], v17, v[4:5] -; GFX9-NEXT: v_lshlrev_b64 v[10:11], v10, v[8:9] +; GFX9-NEXT: v_lshrrev_b64 v[8:9], v17, v[4:5] +; GFX9-NEXT: v_lshlrev_b64 v[10:11], v10, v[6:7] ; GFX9-NEXT: v_subrev_u32_e32 v12, 64, v17 -; GFX9-NEXT: v_or_b32_e32 v10, v6, v10 -; GFX9-NEXT: v_or_b32_e32 v11, v7, v11 -; GFX9-NEXT: v_lshrrev_b64 v[6:7], v17, v[8:9] -; GFX9-NEXT: v_lshrrev_b64 v[8:9], v12, v[8:9] +; GFX9-NEXT: v_or_b32_e32 v10, v8, v10 +; GFX9-NEXT: v_or_b32_e32 v11, v9, v11 +; GFX9-NEXT: v_lshrrev_b64 v[8:9], v17, v[6:7] +; GFX9-NEXT: v_lshrrev_b64 v[6:7], v12, v[6:7] ; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17 -; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc ; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v17 -; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX9-NEXT: v_or_b32_e32 v4, v18, v4 ; GFX9-NEXT: v_or_b32_e32 v5, v19, v5 ; GFX9-NEXT: v_or_b32_e32 v6, v16, v6 @@ -6562,96 +7301,127 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: v_xor_b32_e32 v17, -1, v16 ; GFX10-NEXT: s_movk_i32 s7, 0x7f -; GFX10-NEXT: v_xor_b32_e32 v18, -1, v16 -; GFX10-NEXT: v_and_b32_e32 v27, s7, v16 ; GFX10-NEXT: s_sub_i32 s8, 64, 1 -; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9] -; GFX10-NEXT: v_lshlrev_b64 v[16:17], s8, v[10:11] -; GFX10-NEXT: v_and_b32_e32 v28, s7, v18 -; GFX10-NEXT: v_sub_nc_u32_e32 v19, 64, v27 -; GFX10-NEXT: v_lshlrev_b64 v[21:22], v27, v[2:3] +; GFX10-NEXT: v_and_b32_e32 v27, s7, v16 +; GFX10-NEXT: v_lshlrev_b64 v[18:19], s8, v[10:11] +; GFX10-NEXT: v_and_b32_e32 v28, s7, v17 +; GFX10-NEXT: v_lshrrev_b64 v[16:17], 1, v[8:9] +; GFX10-NEXT: s_sub_i32 s9, 1, 64 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: v_lshrrev_b64 v[21:22], s9, v[10:11] +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: v_or_b32_e32 v16, v16, v18 +; GFX10-NEXT: v_or_b32_e32 v17, v17, v19 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_and_b32 s5, 1, vcc_lo +; GFX10-NEXT: s_and_b32 s4, 1, s4 +; GFX10-NEXT: v_sub_nc_u32_e32 v23, 64, v27 ; GFX10-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11] -; GFX10-NEXT: v_subrev_nc_u32_e32 v29, 64, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v16, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v17, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s5 +; GFX10-NEXT: v_lshrrev_b64 v[16:17], v23, v[0:1] +; GFX10-NEXT: v_lshlrev_b64 v[18:19], v27, v[2:3] ; GFX10-NEXT: v_sub_nc_u32_e32 v25, 64, v28 -; GFX10-NEXT: v_lshrrev_b64 v[18:19], v19, v[0:1] -; GFX10-NEXT: v_or_b32_e32 v8, v8, v16 -; GFX10-NEXT: v_or_b32_e32 v9, v9, v17 -; GFX10-NEXT: v_lshlrev_b64 v[16:17], v27, v[0:1] +; GFX10-NEXT: v_cndmask_b32_e32 v8, v21, v8, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v9, v22, v9, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v10, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, v11, s4 +; GFX10-NEXT: v_or_b32_e32 v18, v16, v18 +; GFX10-NEXT: v_subrev_nc_u32_e32 v29, 64, v27 +; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 64, v28 +; GFX10-NEXT: v_lshrrev_b64 v[23:24], v28, v[8:9] ; GFX10-NEXT: v_lshlrev_b64 v[25:26], v25, v[10:11] +; GFX10-NEXT: v_lshlrev_b64 v[21:22], v27, v[0:1] +; GFX10-NEXT: v_or_b32_e32 v19, v17, v19 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v29, v[0:1] -; GFX10-NEXT: v_or_b32_e32 v21, v18, v21 -; GFX10-NEXT: v_lshrrev_b64 v[23:24], v28, v[8:9] -; GFX10-NEXT: v_subrev_nc_u32_e32 v18, 64, v28 -; GFX10-NEXT: v_or_b32_e32 v22, v19, v22 +; GFX10-NEXT: v_lshrrev_b64 v[16:17], v16, v[10:11] ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v27 -; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v28 -; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v28 -; GFX10-NEXT: v_lshrrev_b64 v[18:19], v18, v[10:11] ; GFX10-NEXT: v_or_b32_e32 v23, v23, v25 +; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v28 ; GFX10-NEXT: v_or_b32_e32 v24, v24, v26 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v27 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v23, s4 +; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v28 +; GFX10-NEXT: v_cndmask_b32_e32 v18, v0, v18, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v19, v1, v19, vcc_lo ; GFX10-NEXT: v_lshrrev_b64 v[0:1], v28, v[10:11] -; GFX10-NEXT: v_cndmask_b32_e64 v10, v19, v24, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v3, s6 -; GFX10-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v3, v18, v8, s5 -; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v17, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v8, v10, v9, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v0, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v21, v2, s6 -; GFX10-NEXT: v_and_b32_e32 v24, s7, v20 -; GFX10-NEXT: v_or_b32_e32 v0, v16, v3 -; GFX10-NEXT: v_xor_b32_e32 v3, -1, v20 +; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v23, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v10, v17, v24, s4 +; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v27 +; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v22, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v21, 0, v21, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v8, v16, v8, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v9, v10, v9, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v22, v19, v3, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v0, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v23, 0, v1, s4 -; GFX10-NEXT: v_or_b32_e32 v1, v11, v8 -; GFX10-NEXT: v_or_b32_e32 v2, v2, v9 -; GFX10-NEXT: v_lshlrev_b64 v[10:11], s8, v[14:15] +; GFX10-NEXT: v_xor_b32_e32 v16, -1, v20 +; GFX10-NEXT: v_or_b32_e32 v1, v11, v9 +; GFX10-NEXT: v_or_b32_e32 v0, v21, v8 ; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13] -; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v24 -; GFX10-NEXT: v_and_b32_e32 v25, s7, v3 -; GFX10-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15] +; GFX10-NEXT: v_lshlrev_b64 v[10:11], s8, v[14:15] +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: v_and_b32_e32 v25, s7, v16 +; GFX10-NEXT: v_and_b32_e32 v24, s7, v20 +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: v_lshrrev_b64 v[16:17], s9, v[14:15] +; GFX10-NEXT: v_or_b32_e32 v10, v8, v10 +; GFX10-NEXT: v_or_b32_e32 v11, v9, v11 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_and_b32 s5, 1, vcc_lo +; GFX10-NEXT: s_and_b32 s4, 1, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v2, s6 +; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[14:15] +; GFX10-NEXT: v_sub_nc_u32_e32 v18, 64, v24 +; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v10, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s5 +; GFX10-NEXT: v_lshrrev_b64 v[10:11], v18, v[4:5] +; GFX10-NEXT: v_lshlrev_b64 v[14:15], v24, v[6:7] +; GFX10-NEXT: v_sub_nc_u32_e32 v20, 64, v25 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v16, v12, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v8, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v9, s4 +; GFX10-NEXT: v_or_b32_e32 v2, v2, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 64, v24 +; GFX10-NEXT: v_lshlrev_b64 v[16:17], v24, v[4:5] +; GFX10-NEXT: v_or_b32_e32 v14, v10, v14 +; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v25 +; GFX10-NEXT: v_lshrrev_b64 v[18:19], v25, v[12:13] +; GFX10-NEXT: v_lshlrev_b64 v[20:21], v20, v[8:9] ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v24 -; GFX10-NEXT: v_lshrrev_b64 v[12:13], v16, v[4:5] -; GFX10-NEXT: v_lshlrev_b64 v[16:17], v24, v[6:7] -; GFX10-NEXT: v_sub_nc_u32_e32 v20, 64, v25 -; GFX10-NEXT: v_or_b32_e32 v8, v8, v10 -; GFX10-NEXT: v_or_b32_e32 v9, v9, v11 -; GFX10-NEXT: v_lshlrev_b64 v[10:11], v24, v[4:5] ; GFX10-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5] -; GFX10-NEXT: v_or_b32_e32 v16, v12, v16 -; GFX10-NEXT: v_subrev_nc_u32_e32 v12, 64, v25 -; GFX10-NEXT: v_lshrrev_b64 v[18:19], v25, v[8:9] -; GFX10-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15] -; GFX10-NEXT: v_or_b32_e32 v5, v13, v17 +; GFX10-NEXT: v_or_b32_e32 v5, v11, v15 +; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[8:9] ; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v25 -; GFX10-NEXT: v_lshrrev_b64 v[12:13], v12, v[14:15] -; GFX10-NEXT: v_cndmask_b32_e32 v16, v3, v16, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v24 -; GFX10-NEXT: v_or_b32_e32 v17, v18, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v15, 0, v16, vcc_lo +; GFX10-NEXT: v_or_b32_e32 v16, v18, v20 ; GFX10-NEXT: v_or_b32_e32 v18, v19, v21 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v3, v14, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc_lo -; GFX10-NEXT: v_lshrrev_b64 v[3:4], v25, v[14:15] +; GFX10-NEXT: v_lshrrev_b64 v[3:4], v25, v[8:9] +; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v24 +; GFX10-NEXT: v_cndmask_b32_e64 v8, v11, v18, s4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v25 -; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v17, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v18, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v9, 0, v17, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v5, v7, s6 -; GFX10-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, v12, v8, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, v4, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v8, v13, v9, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v3, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v6, v16, v6, s6 -; GFX10-NEXT: v_or_b32_e32 v4, v10, v5 +; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, v4, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v14, v6, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v10, v12, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v3, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v13, s5 ; GFX10-NEXT: v_or_b32_e32 v3, v22, v23 -; GFX10-NEXT: v_or_b32_e32 v5, v11, v8 -; GFX10-NEXT: v_or_b32_e32 v7, v7, v12 -; GFX10-NEXT: v_or_b32_e32 v6, v6, v9 +; GFX10-NEXT: v_or_b32_e32 v7, v7, v11 +; GFX10-NEXT: v_or_b32_e32 v4, v15, v5 +; GFX10-NEXT: v_or_b32_e32 v6, v6, v10 +; GFX10-NEXT: v_or_b32_e32 v5, v9, v8 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) ret <2 x i128> %result diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll index 8315b9a..91655df 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll @@ -4862,11 +4862,22 @@ define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg ; GFX6-NEXT: s_mov_b32 s11, 0 ; GFX6-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX6-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] -; GFX6-NEXT: s_sub_i32 s9, 64, 1 +; GFX6-NEXT: s_sub_i32 s9, 1, 64 +; GFX6-NEXT: s_sub_i32 s13, 64, 1 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s18, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s19, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[14:15], s[0:1], s13 +; GFX6-NEXT: s_lshl_b64 s[16:17], s[2:3], 1 ; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], 1 -; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s9 -; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 -; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX6-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] +; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 +; GFX6-NEXT: s_cmp_lg_u32 s18, 0 +; GFX6-NEXT: s_cselect_b64 s[10:11], s[10:11], 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1] +; GFX6-NEXT: s_cmp_lg_u32 s19, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX6-NEXT: s_sub_i32 s13, s8, 64 ; GFX6-NEXT: s_sub_i32 s9, 64, s8 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64 @@ -4910,11 +4921,22 @@ define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg ; GFX8-NEXT: s_mov_b32 s11, 0 ; GFX8-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX8-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] -; GFX8-NEXT: s_sub_i32 s9, 64, 1 +; GFX8-NEXT: s_sub_i32 s9, 1, 64 +; GFX8-NEXT: s_sub_i32 s13, 64, 1 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[14:15], s[0:1], s13 +; GFX8-NEXT: s_lshl_b64 s[16:17], s[2:3], 1 ; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], 1 -; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s9 -; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 -; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX8-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] +; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 +; GFX8-NEXT: s_cmp_lg_u32 s18, 0 +; GFX8-NEXT: s_cselect_b64 s[10:11], s[10:11], 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1] +; GFX8-NEXT: s_cmp_lg_u32 s19, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX8-NEXT: s_sub_i32 s13, s8, 64 ; GFX8-NEXT: s_sub_i32 s9, 64, s8 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64 @@ -4958,11 +4980,22 @@ define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg ; GFX9-NEXT: s_mov_b32 s11, 0 ; GFX9-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX9-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] -; GFX9-NEXT: s_sub_i32 s9, 64, 1 +; GFX9-NEXT: s_sub_i32 s9, 1, 64 +; GFX9-NEXT: s_sub_i32 s13, 64, 1 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s18, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s19, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[14:15], s[0:1], s13 +; GFX9-NEXT: s_lshl_b64 s[16:17], s[2:3], 1 ; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], 1 -; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s9 -; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 -; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX9-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] +; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 +; GFX9-NEXT: s_cmp_lg_u32 s18, 0 +; GFX9-NEXT: s_cselect_b64 s[10:11], s[10:11], 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1] +; GFX9-NEXT: s_cmp_lg_u32 s19, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX9-NEXT: s_sub_i32 s13, s8, 64 ; GFX9-NEXT: s_sub_i32 s9, 64, s8 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64 @@ -5004,29 +5037,40 @@ define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg ; GFX10: ; %bb.0: ; GFX10-NEXT: s_movk_i32 s10, 0x7f ; GFX10-NEXT: s_mov_b32 s11, 0 -; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX10-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] -; GFX10-NEXT: s_sub_i32 s13, 64, 1 ; GFX10-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] -; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s13 -; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 -; GFX10-NEXT: s_or_b64 s[2:3], s[10:11], s[2:3] +; GFX10-NEXT: s_sub_i32 s9, 1, 64 +; GFX10-NEXT: s_sub_i32 s10, 64, 1 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: s_cselect_b32 s13, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: s_cselect_b32 s18, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s10 +; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 1 +; GFX10-NEXT: s_lshl_b64 s[16:17], s[0:1], 1 +; GFX10-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15] +; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 +; GFX10-NEXT: s_cmp_lg_u32 s13, 0 +; GFX10-NEXT: s_cselect_b64 s[14:15], s[16:17], 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX10-NEXT: s_cmp_lg_u32 s18, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX10-NEXT: s_sub_i32 s13, s8, 64 -; GFX10-NEXT: s_sub_i32 s9, 64, s8 +; GFX10-NEXT: s_sub_i32 s2, 64, s8 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: s_cselect_b32 s17, 1, 0 -; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 -; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], s8 -; GFX10-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 -; GFX10-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15] -; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s13 +; GFX10-NEXT: s_lshl_b64 s[10:11], s[0:1], s8 +; GFX10-NEXT: s_lshr_b64 s[2:3], s[14:15], s2 +; GFX10-NEXT: s_lshl_b64 s[8:9], s[14:15], s8 +; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11] +; GFX10-NEXT: s_lshl_b64 s[10:11], s[14:15], s13 ; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 -; GFX10-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11] ; GFX10-NEXT: s_cmp_lg_u32 s17, 0 -; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX10-NEXT: s_cselect_b64 s[2:3], s[0:1], s[2:3] ; GFX10-NEXT: s_sub_i32 s14, s12, 64 ; GFX10-NEXT: s_sub_i32 s10, 64, s12 ; GFX10-NEXT: s_cmp_lt_u32 s12, 64 @@ -5059,28 +5103,44 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) { ; GFX6-NEXT: v_and_b32_e32 v14, s4, v8 ; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8 ; GFX6-NEXT: v_and_b32_e32 v15, s4, v8 -; GFX6-NEXT: s_sub_i32 s4, 64, 1 -; GFX6-NEXT: v_lshr_b64 v[8:9], v[0:1], s4 -; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 -; GFX6-NEXT: v_or_b32_e32 v2, v8, v2 -; GFX6-NEXT: v_or_b32_e32 v3, v9, v3 -; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v15 +; GFX6-NEXT: s_sub_i32 s5, 64, 1 +; GFX6-NEXT: s_sub_i32 s4, 1, 64 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s6, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: v_lshr_b64 v[8:9], v[0:1], s5 +; GFX6-NEXT: v_lshl_b64 v[10:11], v[2:3], 1 +; GFX6-NEXT: v_lshl_b64 v[12:13], v[0:1], 1 +; GFX6-NEXT: s_cselect_b32 s7, 1, 0 +; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s4 +; GFX6-NEXT: s_and_b32 s4, 1, s6 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_or_b32_e32 v10, v8, v10 +; GFX6-NEXT: v_or_b32_e32 v11, v9, v11 +; GFX6-NEXT: s_and_b32 s4, 1, s7 +; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v12, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v13, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v15 +; GFX6-NEXT: v_lshr_b64 v[2:3], v[8:9], v2 +; GFX6-NEXT: v_lshl_b64 v[10:11], v[0:1], v15 ; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, 64, v15 -; GFX6-NEXT: v_lshr_b64 v[8:9], v[0:1], v8 -; GFX6-NEXT: v_lshl_b64 v[10:11], v[2:3], v15 -; GFX6-NEXT: v_lshl_b64 v[12:13], v[0:1], v15 -; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v16 -; GFX6-NEXT: v_or_b32_e32 v8, v8, v10 +; GFX6-NEXT: v_lshl_b64 v[12:13], v[8:9], v15 +; GFX6-NEXT: v_or_b32_e32 v10, v2, v10 +; GFX6-NEXT: v_or_b32_e32 v11, v3, v11 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[8:9], v16 ; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15 -; GFX6-NEXT: v_or_b32_e32 v9, v9, v11 -; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15 -; GFX6-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v10, v2, v0, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v11, v3, v1, vcc ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v14 ; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], v14 ; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], v2 @@ -5097,10 +5157,10 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) { ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5] ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc -; GFX6-NEXT: v_or_b32_e32 v0, v10, v0 -; GFX6-NEXT: v_or_b32_e32 v1, v11, v1 -; GFX6-NEXT: v_or_b32_e32 v2, v12, v2 -; GFX6-NEXT: v_or_b32_e32 v3, v13, v3 +; GFX6-NEXT: v_or_b32_e32 v0, v12, v0 +; GFX6-NEXT: v_or_b32_e32 v1, v13, v1 +; GFX6-NEXT: v_or_b32_e32 v2, v10, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v11, v3 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_fshr_i128: @@ -5110,28 +5170,44 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) { ; GFX8-NEXT: v_and_b32_e32 v14, s4, v8 ; GFX8-NEXT: v_xor_b32_e32 v8, -1, v8 ; GFX8-NEXT: v_and_b32_e32 v15, s4, v8 -; GFX8-NEXT: s_sub_i32 s4, 64, 1 -; GFX8-NEXT: v_lshrrev_b64 v[8:9], s4, v[0:1] -; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] -; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] -; GFX8-NEXT: v_or_b32_e32 v2, v8, v2 -; GFX8-NEXT: v_or_b32_e32 v3, v9, v3 -; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v15 +; GFX8-NEXT: s_sub_i32 s5, 64, 1 +; GFX8-NEXT: s_sub_i32 s4, 1, 64 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: v_lshrrev_b64 v[8:9], s5, v[0:1] +; GFX8-NEXT: v_lshlrev_b64 v[10:11], 1, v[2:3] +; GFX8-NEXT: v_lshlrev_b64 v[12:13], 1, v[0:1] +; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: v_lshlrev_b64 v[0:1], s4, v[0:1] +; GFX8-NEXT: s_and_b32 s4, 1, s6 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_or_b32_e32 v10, v8, v10 +; GFX8-NEXT: v_or_b32_e32 v11, v9, v11 +; GFX8-NEXT: s_and_b32 s4, 1, s7 +; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v13, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 64, v15 +; GFX8-NEXT: v_lshrrev_b64 v[2:3], v2, v[8:9] +; GFX8-NEXT: v_lshlrev_b64 v[10:11], v15, v[0:1] ; GFX8-NEXT: v_subrev_u32_e32 v16, vcc, 64, v15 -; GFX8-NEXT: v_lshrrev_b64 v[8:9], v8, v[0:1] -; GFX8-NEXT: v_lshlrev_b64 v[10:11], v15, v[2:3] -; GFX8-NEXT: v_lshlrev_b64 v[12:13], v15, v[0:1] -; GFX8-NEXT: v_lshlrev_b64 v[0:1], v16, v[0:1] -; GFX8-NEXT: v_or_b32_e32 v8, v8, v10 +; GFX8-NEXT: v_lshlrev_b64 v[12:13], v15, v[8:9] +; GFX8-NEXT: v_or_b32_e32 v10, v2, v10 +; GFX8-NEXT: v_or_b32_e32 v11, v3, v11 +; GFX8-NEXT: v_lshlrev_b64 v[2:3], v16, v[8:9] ; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15 -; GFX8-NEXT: v_or_b32_e32 v9, v9, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, v3, v1, vcc ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 64, v14 ; GFX8-NEXT: v_lshrrev_b64 v[0:1], v14, v[4:5] ; GFX8-NEXT: v_lshlrev_b64 v[2:3], v2, v[6:7] @@ -5148,10 +5224,10 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) { ; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc -; GFX8-NEXT: v_or_b32_e32 v0, v10, v0 -; GFX8-NEXT: v_or_b32_e32 v1, v11, v1 -; GFX8-NEXT: v_or_b32_e32 v2, v12, v2 -; GFX8-NEXT: v_or_b32_e32 v3, v13, v3 +; GFX8-NEXT: v_or_b32_e32 v0, v12, v0 +; GFX8-NEXT: v_or_b32_e32 v1, v13, v1 +; GFX8-NEXT: v_or_b32_e32 v2, v10, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v11, v3 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_fshr_i128: @@ -5161,29 +5237,45 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) { ; GFX9-NEXT: v_and_b32_e32 v14, s4, v8 ; GFX9-NEXT: v_xor_b32_e32 v8, -1, v8 ; GFX9-NEXT: v_and_b32_e32 v15, s4, v8 -; GFX9-NEXT: s_sub_i32 s4, 64, 1 -; GFX9-NEXT: v_lshrrev_b64 v[8:9], s4, v[0:1] -; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] -; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] -; GFX9-NEXT: v_or_b32_e32 v2, v8, v2 -; GFX9-NEXT: v_or_b32_e32 v3, v9, v3 -; GFX9-NEXT: v_sub_u32_e32 v8, 64, v15 +; GFX9-NEXT: s_sub_i32 s5, 64, 1 +; GFX9-NEXT: s_sub_i32 s4, 1, 64 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: v_lshrrev_b64 v[8:9], s5, v[0:1] +; GFX9-NEXT: v_lshlrev_b64 v[10:11], 1, v[2:3] +; GFX9-NEXT: v_lshlrev_b64 v[12:13], 1, v[0:1] +; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: v_lshlrev_b64 v[0:1], s4, v[0:1] +; GFX9-NEXT: s_and_b32 s4, 1, s6 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_or_b32_e32 v10, v8, v10 +; GFX9-NEXT: v_or_b32_e32 v11, v9, v11 +; GFX9-NEXT: s_and_b32 s4, 1, s7 +; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v12, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v13, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_sub_u32_e32 v2, 64, v15 +; GFX9-NEXT: v_lshrrev_b64 v[2:3], v2, v[8:9] +; GFX9-NEXT: v_lshlrev_b64 v[10:11], v15, v[0:1] ; GFX9-NEXT: v_subrev_u32_e32 v16, 64, v15 -; GFX9-NEXT: v_lshrrev_b64 v[8:9], v8, v[0:1] -; GFX9-NEXT: v_lshlrev_b64 v[10:11], v15, v[2:3] -; GFX9-NEXT: v_lshlrev_b64 v[12:13], v15, v[0:1] -; GFX9-NEXT: v_lshlrev_b64 v[0:1], v16, v[0:1] -; GFX9-NEXT: v_or_b32_e32 v8, v8, v10 +; GFX9-NEXT: v_lshlrev_b64 v[12:13], v15, v[8:9] +; GFX9-NEXT: v_or_b32_e32 v10, v2, v10 +; GFX9-NEXT: v_or_b32_e32 v11, v3, v11 +; GFX9-NEXT: v_lshlrev_b64 v[2:3], v16, v[8:9] ; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15 -; GFX9-NEXT: v_or_b32_e32 v9, v9, v11 -; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15 -; GFX9-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v10, v2, v0, vcc ; GFX9-NEXT: v_sub_u32_e32 v2, 64, v14 -; GFX9-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v1, vcc ; GFX9-NEXT: v_lshrrev_b64 v[0:1], v14, v[4:5] ; GFX9-NEXT: v_lshlrev_b64 v[2:3], v2, v[6:7] ; GFX9-NEXT: v_subrev_u32_e32 v15, 64, v14 @@ -5199,62 +5291,78 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) { ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc -; GFX9-NEXT: v_or_b32_e32 v0, v10, v0 -; GFX9-NEXT: v_or_b32_e32 v1, v11, v1 -; GFX9-NEXT: v_or_b32_e32 v2, v12, v2 -; GFX9-NEXT: v_or_b32_e32 v3, v13, v3 +; GFX9-NEXT: v_or_b32_e32 v0, v12, v0 +; GFX9-NEXT: v_or_b32_e32 v1, v13, v1 +; GFX9-NEXT: v_or_b32_e32 v2, v10, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v11, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_fshr_i128: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_xor_b32_e32 v11, -1, v8 ; GFX10-NEXT: s_sub_i32 s4, 64, 1 -; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] +; GFX10-NEXT: s_sub_i32 s6, 1, 64 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 ; GFX10-NEXT: v_lshrrev_b64 v[9:10], s4, v[0:1] -; GFX10-NEXT: s_movk_i32 s4, 0x7f -; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] -; GFX10-NEXT: v_and_b32_e32 v18, s4, v11 -; GFX10-NEXT: v_and_b32_e32 v19, s4, v8 -; GFX10-NEXT: v_or_b32_e32 v3, v10, v3 -; GFX10-NEXT: v_or_b32_e32 v2, v9, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v18 -; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v19 -; GFX10-NEXT: v_subrev_nc_u32_e32 v20, 64, v18 -; GFX10-NEXT: v_lshrrev_b64 v[14:15], v19, v[4:5] -; GFX10-NEXT: v_lshlrev_b64 v[8:9], v18, v[2:3] -; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[0:1] -; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7] -; GFX10-NEXT: v_lshlrev_b64 v[12:13], v18, v[0:1] -; GFX10-NEXT: v_lshlrev_b64 v[0:1], v20, v[0:1] -; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18 -; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v19 -; GFX10-NEXT: v_or_b32_e32 v10, v10, v8 +; GFX10-NEXT: v_lshlrev_b64 v[11:12], 1, v[2:3] +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: v_lshlrev_b64 v[13:14], 1, v[0:1] +; GFX10-NEXT: s_cselect_b32 s7, 1, 0 +; GFX10-NEXT: s_and_b32 s4, 1, vcc_lo +; GFX10-NEXT: v_lshlrev_b64 v[0:1], s6, v[0:1] +; GFX10-NEXT: v_or_b32_e32 v11, v9, v11 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4 +; GFX10-NEXT: v_or_b32_e32 v10, v10, v12 +; GFX10-NEXT: v_xor_b32_e32 v15, -1, v8 +; GFX10-NEXT: s_movk_i32 s5, 0x7f +; GFX10-NEXT: s_and_b32 s6, 1, s7 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v11, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v10, s4 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s6 +; GFX10-NEXT: v_and_b32_e32 v19, s5, v15 +; GFX10-NEXT: v_cndmask_b32_e32 v9, 0, v13, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v10, 0, v14, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v20, s5, v8 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 +; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v19 ; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v19 -; GFX10-NEXT: v_or_b32_e32 v11, v11, v9 -; GFX10-NEXT: v_or_b32_e32 v14, v14, v16 -; GFX10-NEXT: v_or_b32_e32 v15, v15, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v0, v10, vcc_lo -; GFX10-NEXT: v_lshrrev_b64 v[8:9], v8, v[6:7] -; GFX10-NEXT: v_cndmask_b32_e32 v11, v1, v11, vcc_lo -; GFX10-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7] -; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v18 -; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v14, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v6, v9, v15, s4 -; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, v2, s6 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, v3, s6 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, v5, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v0, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v1, s4 -; GFX10-NEXT: v_or_b32_e32 v0, v12, v4 -; GFX10-NEXT: v_or_b32_e32 v1, v7, v5 -; GFX10-NEXT: v_or_b32_e32 v2, v2, v6 -; GFX10-NEXT: v_or_b32_e32 v3, v3, v8 +; GFX10-NEXT: v_sub_nc_u32_e32 v17, 64, v20 +; GFX10-NEXT: v_lshlrev_b64 v[13:14], v19, v[9:10] +; GFX10-NEXT: v_lshlrev_b64 v[11:12], v19, v[0:1] +; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, v[9:10] +; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, v[9:10] +; GFX10-NEXT: v_lshrrev_b64 v[15:16], v20, v[4:5] +; GFX10-NEXT: v_lshlrev_b64 v[17:18], v17, v[6:7] +; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v19 +; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v20 +; GFX10-NEXT: v_or_b32_e32 v11, v2, v11 +; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v20 +; GFX10-NEXT: v_or_b32_e32 v10, v3, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v12, 0, v13, vcc_lo +; GFX10-NEXT: v_or_b32_e32 v13, v15, v17 +; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo +; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, v[6:7] +; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc_lo +; GFX10-NEXT: v_or_b32_e32 v10, v16, v18 +; GFX10-NEXT: v_lshrrev_b64 v[6:7], v20, v[6:7] +; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v19 +; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v20 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v13, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v10, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v10, 0, v14, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v4, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, v5, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v6, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v7, s4 +; GFX10-NEXT: v_or_b32_e32 v0, v12, v0 +; GFX10-NEXT: v_or_b32_e32 v1, v10, v1 +; GFX10-NEXT: v_or_b32_e32 v2, v8, v2 +; GFX10-NEXT: v_or_b32_e32 v3, v9, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt) ret i128 %result @@ -5263,16 +5371,27 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) { define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) { ; GFX6-LABEL: v_fshr_i128_ssv: ; GFX6: ; %bb.0: +; GFX6-NEXT: s_sub_i32 s14, 1, 64 +; GFX6-NEXT: s_sub_i32 s10, 64, 1 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 ; GFX6-NEXT: s_movk_i32 s8, 0x7f +; GFX6-NEXT: s_cselect_b32 s15, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s16, 1, 0 ; GFX6-NEXT: v_and_b32_e32 v6, s8, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0 -; GFX6-NEXT: s_sub_i32 s10, 64, 1 +; GFX6-NEXT: s_lshr_b64 s[10:11], s[0:1], s10 +; GFX6-NEXT: s_lshl_b64 s[12:13], s[2:3], 1 ; GFX6-NEXT: v_and_b32_e32 v7, s8, v0 ; GFX6-NEXT: s_lshl_b64 s[8:9], s[0:1], 1 -; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s10 -; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 +; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s14 +; GFX6-NEXT: s_cmp_lg_u32 s15, 0 +; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, 64, v7 -; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX6-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX6-NEXT: v_lshr_b64 v[0:1], s[8:9], v0 ; GFX6-NEXT: v_lshl_b64 v[2:3], s[0:1], v7 ; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 64, v7 @@ -5316,16 +5435,27 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, ; ; GFX8-LABEL: v_fshr_i128_ssv: ; GFX8: ; %bb.0: +; GFX8-NEXT: s_sub_i32 s14, 1, 64 +; GFX8-NEXT: s_sub_i32 s10, 64, 1 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 ; GFX8-NEXT: s_movk_i32 s8, 0x7f +; GFX8-NEXT: s_cselect_b32 s15, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s16, 1, 0 ; GFX8-NEXT: v_and_b32_e32 v6, s8, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0 -; GFX8-NEXT: s_sub_i32 s10, 64, 1 +; GFX8-NEXT: s_lshr_b64 s[10:11], s[0:1], s10 +; GFX8-NEXT: s_lshl_b64 s[12:13], s[2:3], 1 ; GFX8-NEXT: v_and_b32_e32 v7, s8, v0 ; GFX8-NEXT: s_lshl_b64 s[8:9], s[0:1], 1 -; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s10 -; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 +; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s14 +; GFX8-NEXT: s_cmp_lg_u32 s15, 0 +; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX8-NEXT: s_cmp_lg_u32 s16, 0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, 64, v7 -; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[8:9] ; GFX8-NEXT: v_lshlrev_b64 v[2:3], v7, s[0:1] ; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, 64, v7 @@ -5369,16 +5499,27 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, ; ; GFX9-LABEL: v_fshr_i128_ssv: ; GFX9: ; %bb.0: +; GFX9-NEXT: s_sub_i32 s14, 1, 64 +; GFX9-NEXT: s_sub_i32 s10, 64, 1 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 ; GFX9-NEXT: s_movk_i32 s8, 0x7f +; GFX9-NEXT: s_cselect_b32 s15, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 ; GFX9-NEXT: v_and_b32_e32 v6, s8, v0 +; GFX9-NEXT: s_cselect_b32 s16, 1, 0 ; GFX9-NEXT: v_xor_b32_e32 v0, -1, v0 -; GFX9-NEXT: s_sub_i32 s10, 64, 1 +; GFX9-NEXT: s_lshr_b64 s[10:11], s[0:1], s10 +; GFX9-NEXT: s_lshl_b64 s[12:13], s[2:3], 1 ; GFX9-NEXT: v_and_b32_e32 v7, s8, v0 ; GFX9-NEXT: s_lshl_b64 s[8:9], s[0:1], 1 -; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s10 -; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 +; GFX9-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s14 +; GFX9-NEXT: s_cmp_lg_u32 s15, 0 +; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX9-NEXT: s_cmp_lg_u32 s16, 0 ; GFX9-NEXT: v_sub_u32_e32 v0, 64, v7 -; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX9-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[8:9] ; GFX9-NEXT: v_lshlrev_b64 v[2:3], v7, s[0:1] ; GFX9-NEXT: v_subrev_u32_e32 v8, 64, v7 @@ -5423,49 +5564,60 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, ; GFX10-LABEL: v_fshr_i128_ssv: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0 -; GFX10-NEXT: s_movk_i32 s10, 0x7f -; GFX10-NEXT: s_sub_i32 s8, 64, 1 -; GFX10-NEXT: v_and_b32_e32 v13, s10, v0 -; GFX10-NEXT: s_lshr_b64 s[8:9], s[0:1], s8 -; GFX10-NEXT: v_and_b32_e32 v12, s10, v1 -; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 -; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 -; GFX10-NEXT: v_sub_nc_u32_e32 v8, 64, v13 -; GFX10-NEXT: s_or_b64 s[8:9], s[8:9], s[2:3] -; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v12 -; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v12 -; GFX10-NEXT: v_lshlrev_b64 v[0:1], v12, s[8:9] -; GFX10-NEXT: v_subrev_nc_u32_e32 v14, 64, v13 -; GFX10-NEXT: v_lshrrev_b64 v[4:5], v13, s[4:5] -; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, s[0:1] +; GFX10-NEXT: s_sub_i32 s14, 1, 64 +; GFX10-NEXT: s_sub_i32 s9, 64, 1 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: s_movk_i32 s8, 0x7f +; GFX10-NEXT: s_cselect_b32 s15, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: v_and_b32_e32 v13, s8, v1 +; GFX10-NEXT: v_and_b32_e32 v12, s8, v0 +; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[8:9], s[0:1], s9 +; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], 1 +; GFX10-NEXT: s_lshl_b64 s[12:13], s[0:1], 1 +; GFX10-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] +; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s14 +; GFX10-NEXT: s_cmp_lg_u32 s15, 0 +; GFX10-NEXT: v_sub_nc_u32_e32 v0, 64, v13 +; GFX10-NEXT: s_cselect_b64 s[10:11], s[12:13], 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: v_sub_nc_u32_e32 v8, 64, v12 +; GFX10-NEXT: s_cselect_b64 s[8:9], s[2:3], s[0:1] +; GFX10-NEXT: v_lshrrev_b64 v[0:1], v0, s[10:11] +; GFX10-NEXT: v_lshlrev_b64 v[2:3], v13, s[8:9] +; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v13 +; GFX10-NEXT: v_lshrrev_b64 v[6:7], v12, s[4:5] ; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, s[6:7] -; GFX10-NEXT: v_lshlrev_b64 v[10:11], v10, s[0:1] -; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v12 -; GFX10-NEXT: v_lshlrev_b64 v[6:7], v12, s[0:1] -; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 64, v13 -; GFX10-NEXT: v_or_b32_e32 v2, v2, v0 -; GFX10-NEXT: v_or_b32_e32 v3, v3, v1 -; GFX10-NEXT: v_lshrrev_b64 v[0:1], v14, s[6:7] -; GFX10-NEXT: v_or_b32_e32 v4, v4, v8 -; GFX10-NEXT: v_or_b32_e32 v5, v5, v9 +; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v13 +; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 64, v12 +; GFX10-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX10-NEXT: v_subrev_nc_u32_e32 v0, 64, v12 +; GFX10-NEXT: v_lshlrev_b64 v[10:11], v10, s[10:11] +; GFX10-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX10-NEXT: v_or_b32_e32 v6, v6, v8 +; GFX10-NEXT: v_or_b32_e32 v7, v7, v9 +; GFX10-NEXT: v_lshrrev_b64 v[0:1], v0, s[6:7] +; GFX10-NEXT: v_lshlrev_b64 v[4:5], v13, s[10:11] ; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v3, vcc_lo -; GFX10-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7] -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 -; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 0, v13 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v5, s0 -; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v7, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo +; GFX10-NEXT: v_lshrrev_b64 v[2:3], v12, s[6:7] +; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 0, v12 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v7, s0 +; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v13 +; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s4, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, s1 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v8, s8, s2 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v8, s8, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v10, s9, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 -; GFX10-NEXT: v_or_b32_e32 v0, v6, v0 -; GFX10-NEXT: v_or_b32_e32 v1, v4, v1 -; GFX10-NEXT: v_or_b32_e32 v2, v5, v2 +; GFX10-NEXT: v_or_b32_e32 v0, v4, v0 +; GFX10-NEXT: v_or_b32_e32 v1, v5, v1 +; GFX10-NEXT: v_or_b32_e32 v2, v6, v2 ; GFX10-NEXT: v_or_b32_e32 v3, v7, v3 ; GFX10-NEXT: ; return to shader part epilog %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt) @@ -5480,11 +5632,22 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX6-NEXT: s_mov_b32 s7, 0 ; GFX6-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX6-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] -; GFX6-NEXT: s_sub_i32 s5, 64, 1 +; GFX6-NEXT: s_sub_i32 s5, 1, 64 +; GFX6-NEXT: s_sub_i32 s9, 64, 1 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s14, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s15, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 +; GFX6-NEXT: s_lshl_b64 s[12:13], s[2:3], 1 ; GFX6-NEXT: s_lshl_b64 s[6:7], s[0:1], 1 -; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s5 -; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 -; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s5 +; GFX6-NEXT: s_cmp_lg_u32 s14, 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX6-NEXT: s_cmp_lg_u32 s15, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX6-NEXT: s_sub_i32 s9, s4, 64 ; GFX6-NEXT: s_sub_i32 s5, 64, s4 ; GFX6-NEXT: s_cmp_lt_u32 s4, 64 @@ -5537,11 +5700,22 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX8-NEXT: s_mov_b32 s7, 0 ; GFX8-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX8-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] -; GFX8-NEXT: s_sub_i32 s5, 64, 1 +; GFX8-NEXT: s_sub_i32 s5, 1, 64 +; GFX8-NEXT: s_sub_i32 s9, 64, 1 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s14, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s15, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 +; GFX8-NEXT: s_lshl_b64 s[12:13], s[2:3], 1 ; GFX8-NEXT: s_lshl_b64 s[6:7], s[0:1], 1 -; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s5 -; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 -; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s5 +; GFX8-NEXT: s_cmp_lg_u32 s14, 0 +; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX8-NEXT: s_cmp_lg_u32 s15, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX8-NEXT: s_sub_i32 s9, s4, 64 ; GFX8-NEXT: s_sub_i32 s5, 64, s4 ; GFX8-NEXT: s_cmp_lt_u32 s4, 64 @@ -5594,11 +5768,22 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX9-NEXT: s_mov_b32 s7, 0 ; GFX9-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX9-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] -; GFX9-NEXT: s_sub_i32 s5, 64, 1 +; GFX9-NEXT: s_sub_i32 s5, 1, 64 +; GFX9-NEXT: s_sub_i32 s9, 64, 1 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s14, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s15, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 +; GFX9-NEXT: s_lshl_b64 s[12:13], s[2:3], 1 ; GFX9-NEXT: s_lshl_b64 s[6:7], s[0:1], 1 -; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s5 -; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 -; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX9-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s5 +; GFX9-NEXT: s_cmp_lg_u32 s14, 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX9-NEXT: s_cmp_lg_u32 s15, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX9-NEXT: s_sub_i32 s9, s4, 64 ; GFX9-NEXT: s_sub_i32 s5, 64, s4 ; GFX9-NEXT: s_cmp_lt_u32 s4, 64 @@ -5649,30 +5834,41 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX10: ; %bb.0: ; GFX10-NEXT: s_movk_i32 s6, 0x7f ; GFX10-NEXT: s_mov_b32 s7, 0 -; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] -; GFX10-NEXT: s_sub_i32 s9, 64, 1 ; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] -; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s9 -; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 -; GFX10-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3] +; GFX10-NEXT: s_sub_i32 s5, 1, 64 +; GFX10-NEXT: s_sub_i32 s6, 64, 1 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1] +; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: s_cselect_b32 s14, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s6 +; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], 1 +; GFX10-NEXT: s_lshl_b64 s[12:13], s[0:1], 1 +; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] +; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s5 +; GFX10-NEXT: s_cmp_lg_u32 s9, 0 +; GFX10-NEXT: s_cselect_b64 s[10:11], s[12:13], 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1] +; GFX10-NEXT: s_cmp_lg_u32 s14, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX10-NEXT: s_sub_i32 s9, s4, 64 -; GFX10-NEXT: s_sub_i32 s5, 64, s4 +; GFX10-NEXT: s_sub_i32 s2, 64, s4 ; GFX10-NEXT: s_cmp_lt_u32 s4, 64 -; GFX10-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1] ; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s4, 0 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0 -; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s5 -; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s4 -; GFX10-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 -; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] -; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 +; GFX10-NEXT: s_lshl_b64 s[6:7], s[0:1], s4 +; GFX10-NEXT: s_lshr_b64 s[2:3], s[10:11], s2 +; GFX10-NEXT: s_lshl_b64 s[4:5], s[10:11], s4 +; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] +; GFX10-NEXT: s_lshl_b64 s[6:7], s[10:11], s9 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], 0 -; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1] +; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] ; GFX10-NEXT: s_cmp_lg_u32 s13, 0 -; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX10-NEXT: s_cselect_b64 s[2:3], s[0:1], s[2:3] ; GFX10-NEXT: s_sub_i32 s0, 64, s8 ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3] ; GFX10-NEXT: s_sub_i32 s0, s8, 64 @@ -5711,37 +5907,53 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX6-NEXT: s_mov_b32 s7, 0 ; GFX6-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX6-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] -; GFX6-NEXT: s_sub_i32 s5, 64, 1 -; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s5 -; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 +; GFX6-NEXT: s_sub_i32 s6, 64, 1 +; GFX6-NEXT: s_sub_i32 s5, 1, 64 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s7, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s6 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], 1 +; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], 1 +; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s5 +; GFX6-NEXT: s_and_b32 s5, 1, s7 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX6-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX6-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX6-NEXT: s_and_b32 s5, 1, s9 +; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX6-NEXT: s_sub_i32 s5, s4, 64 ; GFX6-NEXT: s_sub_i32 s6, 64, s4 -; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GFX6-NEXT: s_cmp_lt_u32 s4, 64 ; GFX6-NEXT: s_cselect_b32 s7, 1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s4, 0 -; GFX6-NEXT: v_or_b32_e32 v2, v4, v2 -; GFX6-NEXT: v_or_b32_e32 v3, v5, v3 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX6-NEXT: s_cselect_b32 s9, 1, 0 -; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s4 -; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], s4 +; GFX6-NEXT: v_lshr_b64 v[2:3], v[4:5], s6 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[0:1], s4 +; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], s4 ; GFX6-NEXT: s_and_b32 s4, 1, s7 -; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s6 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX6-NEXT: s_and_b32 s4, 1, s9 ; GFX6-NEXT: s_sub_i32 s10, s8, 64 ; GFX6-NEXT: s_sub_i32 s9, 64, s8 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64 -; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s5 -; GFX6-NEXT: v_or_b32_e32 v4, v4, v6 -; GFX6-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX6-NEXT: v_or_b32_e32 v6, v2, v6 +; GFX6-NEXT: v_or_b32_e32 v7, v3, v7 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[4:5], s5 ; GFX6-NEXT: s_cselect_b32 s11, 1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0 ; GFX6-NEXT: s_cselect_b32 s12, 1, 0 -; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX6-NEXT: s_lshr_b64 s[4:5], s[2:3], s8 ; GFX6-NEXT: s_lshr_b64 s[6:7], s[0:1], s8 @@ -5753,11 +5965,11 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX6-NEXT: s_cmp_lg_u32 s11, 0 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc ; GFX6-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 -; GFX6-NEXT: v_or_b32_e32 v0, s0, v6 -; GFX6-NEXT: v_or_b32_e32 v1, s1, v7 +; GFX6-NEXT: v_or_b32_e32 v0, s0, v4 +; GFX6-NEXT: v_or_b32_e32 v1, s1, v5 ; GFX6-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX6-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX6-NEXT: ; return to shader part epilog @@ -5768,37 +5980,53 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX8-NEXT: s_mov_b32 s7, 0 ; GFX8-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX8-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] -; GFX8-NEXT: s_sub_i32 s5, 64, 1 -; GFX8-NEXT: v_lshrrev_b64 v[4:5], s5, v[0:1] -; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] +; GFX8-NEXT: s_sub_i32 s6, 64, 1 +; GFX8-NEXT: s_sub_i32 s5, 1, 64 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] +; GFX8-NEXT: v_lshlrev_b64 v[6:7], 1, v[2:3] +; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: v_lshlrev_b64 v[8:9], 1, v[0:1] +; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] +; GFX8-NEXT: s_and_b32 s5, 1, s7 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX8-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX8-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX8-NEXT: s_and_b32 s5, 1, s9 +; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX8-NEXT: s_sub_i32 s5, s4, 64 ; GFX8-NEXT: s_sub_i32 s6, 64, s4 -; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX8-NEXT: s_cmp_lt_u32 s4, 64 ; GFX8-NEXT: s_cselect_b32 s7, 1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s4, 0 -; GFX8-NEXT: v_or_b32_e32 v2, v4, v2 -; GFX8-NEXT: v_or_b32_e32 v3, v5, v3 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 -; GFX8-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] -; GFX8-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1] +; GFX8-NEXT: v_lshrrev_b64 v[2:3], s6, v[4:5] +; GFX8-NEXT: v_lshlrev_b64 v[6:7], s4, v[0:1] +; GFX8-NEXT: v_lshlrev_b64 v[8:9], s4, v[4:5] ; GFX8-NEXT: s_and_b32 s4, 1, s7 -; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX8-NEXT: s_and_b32 s4, 1, s9 ; GFX8-NEXT: s_sub_i32 s10, s8, 64 ; GFX8-NEXT: s_sub_i32 s9, 64, s8 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64 -; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] -; GFX8-NEXT: v_or_b32_e32 v4, v4, v6 -; GFX8-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX8-NEXT: v_or_b32_e32 v6, v2, v6 +; GFX8-NEXT: v_or_b32_e32 v7, v3, v7 +; GFX8-NEXT: v_lshlrev_b64 v[2:3], s5, v[4:5] ; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0 ; GFX8-NEXT: s_cselect_b32 s12, 1, 0 -; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX8-NEXT: s_lshr_b64 s[4:5], s[2:3], s8 ; GFX8-NEXT: s_lshr_b64 s[6:7], s[0:1], s8 @@ -5810,11 +6038,11 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX8-NEXT: s_cmp_lg_u32 s12, 0 ; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc ; GFX8-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 -; GFX8-NEXT: v_or_b32_e32 v0, s0, v6 -; GFX8-NEXT: v_or_b32_e32 v1, s1, v7 +; GFX8-NEXT: v_or_b32_e32 v0, s0, v4 +; GFX8-NEXT: v_or_b32_e32 v1, s1, v5 ; GFX8-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX8-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX8-NEXT: ; return to shader part epilog @@ -5825,37 +6053,53 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX9-NEXT: s_mov_b32 s7, 0 ; GFX9-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX9-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] -; GFX9-NEXT: s_sub_i32 s5, 64, 1 -; GFX9-NEXT: v_lshrrev_b64 v[4:5], s5, v[0:1] -; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] +; GFX9-NEXT: s_sub_i32 s6, 64, 1 +; GFX9-NEXT: s_sub_i32 s5, 1, 64 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] +; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[2:3] +; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[0:1] +; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] +; GFX9-NEXT: s_and_b32 s5, 1, s7 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX9-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX9-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX9-NEXT: s_and_b32 s5, 1, s9 +; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX9-NEXT: s_sub_i32 s5, s4, 64 ; GFX9-NEXT: s_sub_i32 s6, 64, s4 -; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX9-NEXT: s_cmp_lt_u32 s4, 64 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s4, 0 -; GFX9-NEXT: v_or_b32_e32 v2, v4, v2 -; GFX9-NEXT: v_or_b32_e32 v3, v5, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 -; GFX9-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] -; GFX9-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1] +; GFX9-NEXT: v_lshrrev_b64 v[2:3], s6, v[4:5] +; GFX9-NEXT: v_lshlrev_b64 v[6:7], s4, v[0:1] +; GFX9-NEXT: v_lshlrev_b64 v[8:9], s4, v[4:5] ; GFX9-NEXT: s_and_b32 s4, 1, s7 -; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX9-NEXT: s_and_b32 s4, 1, s9 ; GFX9-NEXT: s_sub_i32 s10, s8, 64 ; GFX9-NEXT: s_sub_i32 s9, 64, s8 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64 -; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] -; GFX9-NEXT: v_or_b32_e32 v4, v4, v6 -; GFX9-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX9-NEXT: v_or_b32_e32 v6, v2, v6 +; GFX9-NEXT: v_or_b32_e32 v7, v3, v7 +; GFX9-NEXT: v_lshlrev_b64 v[2:3], s5, v[4:5] ; GFX9-NEXT: s_cselect_b32 s11, 1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0 ; GFX9-NEXT: s_cselect_b32 s12, 1, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX9-NEXT: s_lshr_b64 s[4:5], s[2:3], s8 ; GFX9-NEXT: s_lshr_b64 s[6:7], s[0:1], s8 @@ -5867,67 +6111,83 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX9-NEXT: s_cmp_lg_u32 s12, 0 ; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX9-NEXT: s_cmp_lg_u32 s11, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc ; GFX9-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 -; GFX9-NEXT: v_or_b32_e32 v0, s0, v6 -; GFX9-NEXT: v_or_b32_e32 v1, s1, v7 +; GFX9-NEXT: v_or_b32_e32 v0, s0, v4 +; GFX9-NEXT: v_or_b32_e32 v1, s1, v5 ; GFX9-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX9-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_fshr_i128_vss: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_sub_i32 s6, 64, 1 -; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] -; GFX10-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] ; GFX10-NEXT: s_movk_i32 s6, 0x7f ; GFX10-NEXT: s_mov_b32 s7, 0 -; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] -; GFX10-NEXT: s_andn2_b64 s[8:9], s[6:7], s[4:5] -; GFX10-NEXT: s_and_b64 s[6:7], s[4:5], s[6:7] -; GFX10-NEXT: v_or_b32_e32 v2, v4, v2 -; GFX10-NEXT: v_or_b32_e32 v3, v5, v3 -; GFX10-NEXT: s_sub_i32 s4, 64, s8 -; GFX10-NEXT: s_sub_i32 s5, s8, 64 -; GFX10-NEXT: s_cmp_lt_u32 s8, 64 +; GFX10-NEXT: v_lshlrev_b64 v[6:7], 1, v[2:3] +; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] +; GFX10-NEXT: s_andn2_b64 s[6:7], s[6:7], s[4:5] +; GFX10-NEXT: s_sub_i32 s4, 64, 1 +; GFX10-NEXT: s_sub_i32 s5, 1, 64 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] -; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: v_lshlrev_b64 v[8:9], 1, v[0:1] ; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 -; GFX10-NEXT: s_cmp_eq_u32 s8, 0 -; GFX10-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_and_b32 s4, 1, vcc_lo -; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] -; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 +; GFX10-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 +; GFX10-NEXT: s_and_b32 s5, 1, s7 +; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v5, s4 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s5 +; GFX10-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc_lo +; GFX10-NEXT: s_sub_i32 s5, s6, 64 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 +; GFX10-NEXT: s_sub_i32 s4, 64, s6 +; GFX10-NEXT: s_cmp_lt_u32 s6, 64 +; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[4:5] +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: v_lshlrev_b64 v[6:7], s6, v[0:1] +; GFX10-NEXT: s_cmp_eq_u32 s6, 0 +; GFX10-NEXT: v_lshlrev_b64 v[8:9], s6, v[4:5] +; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: s_and_b32 s4, 1, vcc_lo +; GFX10-NEXT: v_lshlrev_b64 v[4:5], s5, v[4:5] +; GFX10-NEXT: v_or_b32_e32 v2, v2, v6 +; GFX10-NEXT: v_or_b32_e32 v3, v3, v7 ; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4 -; GFX10-NEXT: s_sub_i32 s10, s6, 64 +; GFX10-NEXT: s_sub_i32 s10, s8, 64 ; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v5, s4 -; GFX10-NEXT: s_and_b32 s4, 1, s7 -; GFX10-NEXT: s_sub_i32 s7, 64, s6 -; GFX10-NEXT: s_cmp_lt_u32 s6, 64 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v3, s4 +; GFX10-NEXT: s_and_b32 s4, 1, s6 +; GFX10-NEXT: s_sub_i32 s6, 64, s8 +; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 -; GFX10-NEXT: s_cmp_eq_u32 s6, 0 +; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0 -; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s6 -; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s7 -; GFX10-NEXT: s_lshr_b64 s[6:7], s[2:3], s6 -; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] +; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s8 +; GFX10-NEXT: s_lshl_b64 s[6:7], s[2:3], s6 +; GFX10-NEXT: s_lshr_b64 s[8:9], s[2:3], s8 +; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] ; GFX10-NEXT: s_cmp_lg_u32 s12, 0 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: v_or_b32_e32 v0, s0, v6 -; GFX10-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[8:9], 0 ; GFX10-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 @@ -5940,58 +6200,170 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i define amdgpu_ps i128 @s_fshr_i128_65(i128 inreg %lhs, i128 inreg %rhs) { ; GFX6-LABEL: s_fshr_i128_65: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_sub_i32 s3, 64, 63 -; GFX6-NEXT: s_mov_b32 s4, 0 -; GFX6-NEXT: s_lshl_b32 s5, s0, 31 -; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s3 -; GFX6-NEXT: s_lshl_b32 s3, s2, 31 -; GFX6-NEXT: s_mov_b32 s2, s4 -; GFX6-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3] -; GFX6-NEXT: s_sub_i32 s0, 0x41, 64 -; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], s0 -; GFX6-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1] +; GFX6-NEXT: s_sub_i32 s14, 63, 64 +; GFX6-NEXT: s_sub_i32 s10, 64, 63 +; GFX6-NEXT: s_cmp_lt_u32 63, 64 +; GFX6-NEXT: s_mov_b32 s8, 0 +; GFX6-NEXT: s_cselect_b32 s15, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 63, 0 +; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[10:11], s[0:1], s10 +; GFX6-NEXT: s_lshl_b32 s13, s2, 31 +; GFX6-NEXT: s_mov_b32 s12, s8 +; GFX6-NEXT: s_lshl_b32 s9, s0, 31 +; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s14 +; GFX6-NEXT: s_cmp_lg_u32 s15, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 +; GFX6-NEXT: s_cmp_lg_u32 s16, 0 +; GFX6-NEXT: s_movk_i32 s10, 0x41 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX6-NEXT: s_sub_i32 s14, s10, 64 +; GFX6-NEXT: s_sub_i32 s12, 64, s10 +; GFX6-NEXT: s_cmp_lt_u32 s10, 64 +; GFX6-NEXT: s_cselect_b32 s15, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s10, 0 +; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], s10 +; GFX6-NEXT: s_lshl_b64 s[12:13], s[6:7], s12 +; GFX6-NEXT: s_lshr_b64 s[10:11], s[4:5], s10 +; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 +; GFX6-NEXT: s_cmp_lg_u32 s15, 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], s[10:11], s[6:7] +; GFX6-NEXT: s_cmp_lg_u32 s16, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX6-NEXT: s_cmp_lg_u32 s15, 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], s[0:1], 0 +; GFX6-NEXT: s_or_b64 s[0:1], s[8:9], s[4:5] +; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: s_fshr_i128_65: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_sub_i32 s3, 64, 63 -; GFX8-NEXT: s_mov_b32 s4, 0 -; GFX8-NEXT: s_lshl_b32 s5, s0, 31 -; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s3 -; GFX8-NEXT: s_lshl_b32 s3, s2, 31 -; GFX8-NEXT: s_mov_b32 s2, s4 -; GFX8-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3] -; GFX8-NEXT: s_sub_i32 s0, 0x41, 64 -; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], s0 -; GFX8-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1] +; GFX8-NEXT: s_sub_i32 s14, 63, 64 +; GFX8-NEXT: s_sub_i32 s10, 64, 63 +; GFX8-NEXT: s_cmp_lt_u32 63, 64 +; GFX8-NEXT: s_mov_b32 s8, 0 +; GFX8-NEXT: s_cselect_b32 s15, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 63, 0 +; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[10:11], s[0:1], s10 +; GFX8-NEXT: s_lshl_b32 s13, s2, 31 +; GFX8-NEXT: s_mov_b32 s12, s8 +; GFX8-NEXT: s_lshl_b32 s9, s0, 31 +; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s14 +; GFX8-NEXT: s_cmp_lg_u32 s15, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 +; GFX8-NEXT: s_cmp_lg_u32 s16, 0 +; GFX8-NEXT: s_movk_i32 s10, 0x41 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX8-NEXT: s_sub_i32 s14, s10, 64 +; GFX8-NEXT: s_sub_i32 s12, 64, s10 +; GFX8-NEXT: s_cmp_lt_u32 s10, 64 +; GFX8-NEXT: s_cselect_b32 s15, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s10, 0 +; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], s10 +; GFX8-NEXT: s_lshl_b64 s[12:13], s[6:7], s12 +; GFX8-NEXT: s_lshr_b64 s[10:11], s[4:5], s10 +; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX8-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 +; GFX8-NEXT: s_cmp_lg_u32 s15, 0 +; GFX8-NEXT: s_cselect_b64 s[6:7], s[10:11], s[6:7] +; GFX8-NEXT: s_cmp_lg_u32 s16, 0 +; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX8-NEXT: s_cmp_lg_u32 s15, 0 +; GFX8-NEXT: s_cselect_b64 s[6:7], s[0:1], 0 +; GFX8-NEXT: s_or_b64 s[0:1], s[8:9], s[4:5] +; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_fshr_i128_65: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_sub_i32 s3, 64, 63 -; GFX9-NEXT: s_mov_b32 s4, 0 -; GFX9-NEXT: s_lshl_b32 s5, s0, 31 -; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s3 -; GFX9-NEXT: s_lshl_b32 s3, s2, 31 -; GFX9-NEXT: s_mov_b32 s2, s4 -; GFX9-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3] -; GFX9-NEXT: s_sub_i32 s0, 0x41, 64 -; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], s0 -; GFX9-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1] +; GFX9-NEXT: s_sub_i32 s14, 63, 64 +; GFX9-NEXT: s_sub_i32 s10, 64, 63 +; GFX9-NEXT: s_cmp_lt_u32 63, 64 +; GFX9-NEXT: s_mov_b32 s8, 0 +; GFX9-NEXT: s_cselect_b32 s15, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 63, 0 +; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[10:11], s[0:1], s10 +; GFX9-NEXT: s_lshl_b32 s13, s2, 31 +; GFX9-NEXT: s_mov_b32 s12, s8 +; GFX9-NEXT: s_lshl_b32 s9, s0, 31 +; GFX9-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s14 +; GFX9-NEXT: s_cmp_lg_u32 s15, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 +; GFX9-NEXT: s_cmp_lg_u32 s16, 0 +; GFX9-NEXT: s_movk_i32 s10, 0x41 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX9-NEXT: s_sub_i32 s14, s10, 64 +; GFX9-NEXT: s_sub_i32 s12, 64, s10 +; GFX9-NEXT: s_cmp_lt_u32 s10, 64 +; GFX9-NEXT: s_cselect_b32 s15, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s10, 0 +; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], s10 +; GFX9-NEXT: s_lshl_b64 s[12:13], s[6:7], s12 +; GFX9-NEXT: s_lshr_b64 s[10:11], s[4:5], s10 +; GFX9-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 +; GFX9-NEXT: s_cmp_lg_u32 s15, 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], s[10:11], s[6:7] +; GFX9-NEXT: s_cmp_lg_u32 s16, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX9-NEXT: s_cmp_lg_u32 s15, 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], s[0:1], 0 +; GFX9-NEXT: s_or_b64 s[0:1], s[8:9], s[4:5] +; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_fshr_i128_65: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_sub_i32 s3, 64, 63 -; GFX10-NEXT: s_lshl_b32 s5, s0, 31 -; GFX10-NEXT: s_lshr_b64 s[8:9], s[0:1], s3 -; GFX10-NEXT: s_sub_i32 s0, 0x41, 64 -; GFX10-NEXT: s_mov_b32 s4, 0 -; GFX10-NEXT: s_lshr_b64 s[0:1], s[6:7], s0 -; GFX10-NEXT: s_lshl_b32 s3, s2, 31 -; GFX10-NEXT: s_mov_b32 s2, s4 -; GFX10-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1] -; GFX10-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3] +; GFX10-NEXT: s_sub_i32 s14, 63, 64 +; GFX10-NEXT: s_sub_i32 s9, 64, 63 +; GFX10-NEXT: s_cmp_lt_u32 63, 64 +; GFX10-NEXT: s_mov_b32 s8, 0 +; GFX10-NEXT: s_cselect_b32 s15, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 63, 0 +; GFX10-NEXT: s_mov_b32 s12, s8 +; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 +; GFX10-NEXT: s_lshl_b32 s13, s2, 31 +; GFX10-NEXT: s_lshl_b32 s9, s0, 31 +; GFX10-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s14 +; GFX10-NEXT: s_cmp_lg_u32 s15, 0 +; GFX10-NEXT: s_movk_i32 s12, 0x41 +; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX10-NEXT: s_sub_i32 s14, s12, 64 +; GFX10-NEXT: s_sub_i32 s10, 64, s12 +; GFX10-NEXT: s_cmp_lt_u32 s12, 64 +; GFX10-NEXT: s_cselect_b32 s15, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s12, 0 +; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], s12 +; GFX10-NEXT: s_lshl_b64 s[10:11], s[6:7], s10 +; GFX10-NEXT: s_lshr_b64 s[12:13], s[6:7], s12 +; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11] +; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 +; GFX10-NEXT: s_cmp_lg_u32 s15, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7] +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1] +; GFX10-NEXT: s_cmp_lg_u32 s15, 0 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[12:13], 0 +; GFX10-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] +; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX10-NEXT: ; return to shader part epilog %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 65) ret i128 %result @@ -6001,59 +6373,212 @@ define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) { ; GFX6-LABEL: v_fshr_i128_65: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: s_sub_i32 s4, 64, 63 -; GFX6-NEXT: v_mov_b32_e32 v4, v2 -; GFX6-NEXT: v_lshr_b64 v[2:3], v[0:1], s4 -; GFX6-NEXT: s_sub_i32 s4, 0x41, 64 -; GFX6-NEXT: v_lshlrev_b32_e32 v5, 31, v0 -; GFX6-NEXT: v_lshr_b64 v[0:1], v[6:7], s4 -; GFX6-NEXT: v_lshlrev_b32_e32 v4, 31, v4 -; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 -; GFX6-NEXT: v_or_b32_e32 v1, v5, v1 +; GFX6-NEXT: s_sub_i32 s5, 64, 63 +; GFX6-NEXT: s_sub_i32 s4, 63, 64 +; GFX6-NEXT: s_cmp_lt_u32 63, 64 +; GFX6-NEXT: s_cselect_b32 s6, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 63, 0 +; GFX6-NEXT: v_lshr_b64 v[8:9], v[0:1], s5 +; GFX6-NEXT: v_lshlrev_b32_e32 v10, 31, v0 +; GFX6-NEXT: v_lshlrev_b32_e32 v11, 31, v2 +; GFX6-NEXT: s_cselect_b32 s7, 1, 0 +; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s4 +; GFX6-NEXT: s_and_b32 s4, 1, s6 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_or_b32_e32 v9, v9, v11 +; GFX6-NEXT: s_and_b32 s4, 1, s7 +; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_movk_i32 s4, 0x41 +; GFX6-NEXT: s_sub_i32 s5, s4, 64 +; GFX6-NEXT: s_sub_i32 s6, 64, s4 +; GFX6-NEXT: s_cmp_lt_u32 s4, 64 +; GFX6-NEXT: v_cndmask_b32_e32 v11, v0, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v12, v1, v3, vcc +; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s4 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], s6 +; GFX6-NEXT: s_cselect_b32 s7, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s4, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: v_lshr_b64 v[8:9], v[6:7], s4 +; GFX6-NEXT: s_and_b32 s4, 1, s7 +; GFX6-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[6:7], s5 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_and_b32 s4, 1, s8 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_and_b32 s4, 1, s7 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc +; GFX6-NEXT: v_or_b32_e32 v1, v10, v1 +; GFX6-NEXT: v_or_b32_e32 v2, v11, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v12, v3 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_fshr_i128_65: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: s_sub_i32 s4, 64, 63 -; GFX8-NEXT: v_mov_b32_e32 v4, v2 -; GFX8-NEXT: v_lshrrev_b64 v[2:3], s4, v[0:1] -; GFX8-NEXT: s_sub_i32 s4, 0x41, 64 -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 31, v0 -; GFX8-NEXT: v_lshrrev_b64 v[0:1], s4, v[6:7] -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 31, v4 -; GFX8-NEXT: v_or_b32_e32 v3, v3, v4 -; GFX8-NEXT: v_or_b32_e32 v1, v5, v1 +; GFX8-NEXT: s_sub_i32 s5, 64, 63 +; GFX8-NEXT: s_sub_i32 s4, 63, 64 +; GFX8-NEXT: s_cmp_lt_u32 63, 64 +; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 63, 0 +; GFX8-NEXT: v_lshrrev_b64 v[8:9], s5, v[0:1] +; GFX8-NEXT: v_lshlrev_b32_e32 v10, 31, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v11, 31, v2 +; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: v_lshlrev_b64 v[0:1], s4, v[0:1] +; GFX8-NEXT: s_and_b32 s4, 1, s6 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_or_b32_e32 v9, v9, v11 +; GFX8-NEXT: s_and_b32 s4, 1, s7 +; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_movk_i32 s4, 0x41 +; GFX8-NEXT: s_sub_i32 s5, s4, 64 +; GFX8-NEXT: s_sub_i32 s6, 64, s4 +; GFX8-NEXT: s_cmp_lt_u32 s4, 64 +; GFX8-NEXT: v_cndmask_b32_e32 v11, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v12, v1, v3, vcc +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s4, v[4:5] +; GFX8-NEXT: v_lshlrev_b64 v[2:3], s6, v[6:7] +; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s4, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: v_lshrrev_b64 v[8:9], s4, v[6:7] +; GFX8-NEXT: s_and_b32 s4, 1, s7 +; GFX8-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s5, v[6:7] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_and_b32 s4, 1, s8 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_and_b32 s4, 1, s7 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc +; GFX8-NEXT: v_or_b32_e32 v1, v10, v1 +; GFX8-NEXT: v_or_b32_e32 v2, v11, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v12, v3 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_fshr_i128_65: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_sub_i32 s4, 64, 63 -; GFX9-NEXT: v_mov_b32_e32 v4, v2 -; GFX9-NEXT: v_lshrrev_b64 v[2:3], s4, v[0:1] -; GFX9-NEXT: s_sub_i32 s4, 0x41, 64 -; GFX9-NEXT: v_lshlrev_b32_e32 v5, 31, v0 -; GFX9-NEXT: v_lshrrev_b64 v[0:1], s4, v[6:7] -; GFX9-NEXT: v_lshlrev_b32_e32 v4, 31, v4 -; GFX9-NEXT: v_or_b32_e32 v3, v3, v4 -; GFX9-NEXT: v_or_b32_e32 v1, v5, v1 +; GFX9-NEXT: s_sub_i32 s5, 64, 63 +; GFX9-NEXT: s_sub_i32 s4, 63, 64 +; GFX9-NEXT: s_cmp_lt_u32 63, 64 +; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 63, 0 +; GFX9-NEXT: v_lshrrev_b64 v[8:9], s5, v[0:1] +; GFX9-NEXT: v_lshlrev_b32_e32 v10, 31, v0 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 31, v2 +; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: v_lshlrev_b64 v[0:1], s4, v[0:1] +; GFX9-NEXT: s_and_b32 s4, 1, s6 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_or_b32_e32 v9, v9, v11 +; GFX9-NEXT: s_and_b32 s4, 1, s7 +; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_movk_i32 s4, 0x41 +; GFX9-NEXT: s_sub_i32 s5, s4, 64 +; GFX9-NEXT: s_sub_i32 s6, 64, s4 +; GFX9-NEXT: s_cmp_lt_u32 s4, 64 +; GFX9-NEXT: v_cndmask_b32_e32 v11, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v12, v1, v3, vcc +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s4, v[4:5] +; GFX9-NEXT: v_lshlrev_b64 v[2:3], s6, v[6:7] +; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s4, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: v_lshrrev_b64 v[8:9], s4, v[6:7] +; GFX9-NEXT: s_and_b32 s4, 1, s7 +; GFX9-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s5, v[6:7] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_and_b32 s4, 1, s8 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_and_b32 s4, 1, s7 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc +; GFX9-NEXT: v_or_b32_e32 v1, v10, v1 +; GFX9-NEXT: v_or_b32_e32 v2, v11, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v12, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_fshr_i128_65: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_mov_b32_e32 v8, v2 ; GFX10-NEXT: s_sub_i32 s4, 64, 63 -; GFX10-NEXT: s_sub_i32 s5, 0x41, 64 -; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[0:1] -; GFX10-NEXT: v_lshrrev_b64 v[4:5], s5, v[6:7] -; GFX10-NEXT: v_lshlrev_b32_e32 v9, 31, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 31, v8 -; GFX10-NEXT: v_or_b32_e32 v1, v9, v5 -; GFX10-NEXT: v_or_b32_e32 v3, v3, v0 -; GFX10-NEXT: v_mov_b32_e32 v0, v4 +; GFX10-NEXT: s_sub_i32 s5, 63, 64 +; GFX10-NEXT: s_cmp_lt_u32 63, 64 +; GFX10-NEXT: v_lshlrev_b32_e32 v11, 31, v0 +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 63, 0 +; GFX10-NEXT: v_lshrrev_b64 v[8:9], s4, v[0:1] +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] +; GFX10-NEXT: s_and_b32 s5, 1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 31, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v13, 0, v11, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 +; GFX10-NEXT: s_movk_i32 s6, 0x41 +; GFX10-NEXT: s_and_b32 s4, 1, s4 +; GFX10-NEXT: s_sub_i32 s5, 64, s6 +; GFX10-NEXT: v_or_b32_e32 v12, v9, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v14, v0, v8, vcc_lo +; GFX10-NEXT: v_lshlrev_b64 v[10:11], s5, v[6:7] +; GFX10-NEXT: v_lshrrev_b64 v[8:9], s6, v[4:5] +; GFX10-NEXT: s_sub_i32 s5, s6, 64 +; GFX10-NEXT: s_cmp_lt_u32 s6, 64 +; GFX10-NEXT: v_cndmask_b32_e32 v12, v1, v12, vcc_lo +; GFX10-NEXT: v_lshrrev_b64 v[0:1], s5, v[6:7] +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s6, 0 +; GFX10-NEXT: v_or_b32_e32 v8, v8, v10 +; GFX10-NEXT: v_or_b32_e32 v9, v9, v11 +; GFX10-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10-NEXT: v_lshrrev_b64 v[6:7], s6, v[6:7] +; GFX10-NEXT: s_and_b32 s5, 1, s5 +; GFX10-NEXT: s_and_b32 s6, 1, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, s5 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v14, v2, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v12, v3, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v5, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s5 +; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc_lo +; GFX10-NEXT: v_or_b32_e32 v1, v13, v1 +; GFX10-NEXT: v_or_b32_e32 v2, v2, v4 +; GFX10-NEXT: v_or_b32_e32 v3, v3, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 65) ret i128 %result @@ -6064,35 +6589,46 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX6: ; %bb.0: ; GFX6-NEXT: s_movk_i32 s18, 0x7f ; GFX6-NEXT: s_mov_b32 s19, 0 -; GFX6-NEXT: s_sub_i32 s28, 64, 1 ; GFX6-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX6-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] +; GFX6-NEXT: s_sub_i32 s30, 1, 64 +; GFX6-NEXT: s_sub_i32 s31, 64, 1 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s17, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s23, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[26:27], s[0:1], s31 +; GFX6-NEXT: s_lshl_b64 s[28:29], s[2:3], 1 ; GFX6-NEXT: s_lshl_b64 s[24:25], s[0:1], 1 -; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s28 -; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 -; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX6-NEXT: s_or_b64 s[26:27], s[26:27], s[28:29] +; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s30 +; GFX6-NEXT: s_cmp_lg_u32 s17, 0 +; GFX6-NEXT: s_cselect_b64 s[24:25], s[24:25], 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[26:27], s[0:1] +; GFX6-NEXT: s_cmp_lg_u32 s23, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX6-NEXT: s_sub_i32 s23, s16, 64 ; GFX6-NEXT: s_sub_i32 s17, 64, s16 ; GFX6-NEXT: s_cmp_lt_u32 s16, 64 -; GFX6-NEXT: s_cselect_b32 s29, 1, 0 +; GFX6-NEXT: s_cselect_b32 s28, 1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s16, 0 -; GFX6-NEXT: s_cselect_b32 s30, 1, 0 +; GFX6-NEXT: s_cselect_b32 s29, 1, 0 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[24:25], s16 ; GFX6-NEXT: s_lshr_b64 s[26:27], s[24:25], s17 ; GFX6-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 ; GFX6-NEXT: s_or_b64 s[16:17], s[26:27], s[16:17] ; GFX6-NEXT: s_lshl_b64 s[24:25], s[24:25], s23 -; GFX6-NEXT: s_cmp_lg_u32 s29, 0 +; GFX6-NEXT: s_cmp_lg_u32 s28, 0 ; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX6-NEXT: s_cselect_b64 s[16:17], s[16:17], s[24:25] -; GFX6-NEXT: s_cmp_lg_u32 s30, 0 +; GFX6-NEXT: s_cmp_lg_u32 s29, 0 ; GFX6-NEXT: s_cselect_b64 s[16:17], s[0:1], s[16:17] ; GFX6-NEXT: s_sub_i32 s26, s22, 64 ; GFX6-NEXT: s_sub_i32 s24, 64, s22 ; GFX6-NEXT: s_cmp_lt_u32 s22, 64 ; GFX6-NEXT: s_cselect_b32 s27, 1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s22, 0 -; GFX6-NEXT: s_cselect_b32 s29, 1, 0 +; GFX6-NEXT: s_cselect_b32 s28, 1, 0 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[10:11], s22 ; GFX6-NEXT: s_lshl_b64 s[24:25], s[10:11], s24 ; GFX6-NEXT: s_lshr_b64 s[22:23], s[8:9], s22 @@ -6100,18 +6636,28 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX6-NEXT: s_lshr_b64 s[10:11], s[10:11], s26 ; GFX6-NEXT: s_cmp_lg_u32 s27, 0 ; GFX6-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11] -; GFX6-NEXT: s_cmp_lg_u32 s29, 0 +; GFX6-NEXT: s_cmp_lg_u32 s28, 0 ; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX6-NEXT: s_cmp_lg_u32 s27, 0 ; GFX6-NEXT: s_cselect_b64 s[10:11], s[0:1], 0 ; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[8:9] ; GFX6-NEXT: s_or_b64 s[2:3], s[16:17], s[10:11] -; GFX6-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX6-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] +; GFX6-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s11, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[18:19], s[4:5], s31 +; GFX6-NEXT: s_lshl_b64 s[20:21], s[6:7], 1 ; GFX6-NEXT: s_lshl_b64 s[16:17], s[4:5], 1 -; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], s28 -; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 -; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; GFX6-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] +; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], s30 +; GFX6-NEXT: s_cmp_lg_u32 s9, 0 +; GFX6-NEXT: s_cselect_b64 s[16:17], s[16:17], 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], s[18:19], s[4:5] +; GFX6-NEXT: s_cmp_lg_u32 s11, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] ; GFX6-NEXT: s_sub_i32 s9, s10, 64 ; GFX6-NEXT: s_sub_i32 s11, 64, s10 ; GFX6-NEXT: s_cmp_lt_u32 s10, 64 @@ -6153,35 +6699,46 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX8: ; %bb.0: ; GFX8-NEXT: s_movk_i32 s18, 0x7f ; GFX8-NEXT: s_mov_b32 s19, 0 -; GFX8-NEXT: s_sub_i32 s28, 64, 1 ; GFX8-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX8-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] +; GFX8-NEXT: s_sub_i32 s30, 1, 64 +; GFX8-NEXT: s_sub_i32 s31, 64, 1 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s17, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s23, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[26:27], s[0:1], s31 +; GFX8-NEXT: s_lshl_b64 s[28:29], s[2:3], 1 ; GFX8-NEXT: s_lshl_b64 s[24:25], s[0:1], 1 -; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s28 -; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 -; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX8-NEXT: s_or_b64 s[26:27], s[26:27], s[28:29] +; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s30 +; GFX8-NEXT: s_cmp_lg_u32 s17, 0 +; GFX8-NEXT: s_cselect_b64 s[24:25], s[24:25], 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[26:27], s[0:1] +; GFX8-NEXT: s_cmp_lg_u32 s23, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX8-NEXT: s_sub_i32 s23, s16, 64 ; GFX8-NEXT: s_sub_i32 s17, 64, s16 ; GFX8-NEXT: s_cmp_lt_u32 s16, 64 -; GFX8-NEXT: s_cselect_b32 s29, 1, 0 +; GFX8-NEXT: s_cselect_b32 s28, 1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s16, 0 -; GFX8-NEXT: s_cselect_b32 s30, 1, 0 +; GFX8-NEXT: s_cselect_b32 s29, 1, 0 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[24:25], s16 ; GFX8-NEXT: s_lshr_b64 s[26:27], s[24:25], s17 ; GFX8-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 ; GFX8-NEXT: s_or_b64 s[16:17], s[26:27], s[16:17] ; GFX8-NEXT: s_lshl_b64 s[24:25], s[24:25], s23 -; GFX8-NEXT: s_cmp_lg_u32 s29, 0 +; GFX8-NEXT: s_cmp_lg_u32 s28, 0 ; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX8-NEXT: s_cselect_b64 s[16:17], s[16:17], s[24:25] -; GFX8-NEXT: s_cmp_lg_u32 s30, 0 +; GFX8-NEXT: s_cmp_lg_u32 s29, 0 ; GFX8-NEXT: s_cselect_b64 s[16:17], s[0:1], s[16:17] ; GFX8-NEXT: s_sub_i32 s26, s22, 64 ; GFX8-NEXT: s_sub_i32 s24, 64, s22 ; GFX8-NEXT: s_cmp_lt_u32 s22, 64 ; GFX8-NEXT: s_cselect_b32 s27, 1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s22, 0 -; GFX8-NEXT: s_cselect_b32 s29, 1, 0 +; GFX8-NEXT: s_cselect_b32 s28, 1, 0 ; GFX8-NEXT: s_lshr_b64 s[0:1], s[10:11], s22 ; GFX8-NEXT: s_lshl_b64 s[24:25], s[10:11], s24 ; GFX8-NEXT: s_lshr_b64 s[22:23], s[8:9], s22 @@ -6189,18 +6746,28 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX8-NEXT: s_lshr_b64 s[10:11], s[10:11], s26 ; GFX8-NEXT: s_cmp_lg_u32 s27, 0 ; GFX8-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11] -; GFX8-NEXT: s_cmp_lg_u32 s29, 0 +; GFX8-NEXT: s_cmp_lg_u32 s28, 0 ; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX8-NEXT: s_cmp_lg_u32 s27, 0 ; GFX8-NEXT: s_cselect_b64 s[10:11], s[0:1], 0 ; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[8:9] ; GFX8-NEXT: s_or_b64 s[2:3], s[16:17], s[10:11] -; GFX8-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX8-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] +; GFX8-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s11, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[18:19], s[4:5], s31 +; GFX8-NEXT: s_lshl_b64 s[20:21], s[6:7], 1 ; GFX8-NEXT: s_lshl_b64 s[16:17], s[4:5], 1 -; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], s28 -; GFX8-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 -; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; GFX8-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] +; GFX8-NEXT: s_lshl_b64 s[4:5], s[4:5], s30 +; GFX8-NEXT: s_cmp_lg_u32 s9, 0 +; GFX8-NEXT: s_cselect_b64 s[16:17], s[16:17], 0 +; GFX8-NEXT: s_cselect_b64 s[4:5], s[18:19], s[4:5] +; GFX8-NEXT: s_cmp_lg_u32 s11, 0 +; GFX8-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] ; GFX8-NEXT: s_sub_i32 s9, s10, 64 ; GFX8-NEXT: s_sub_i32 s11, 64, s10 ; GFX8-NEXT: s_cmp_lt_u32 s10, 64 @@ -6242,35 +6809,46 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX9: ; %bb.0: ; GFX9-NEXT: s_movk_i32 s18, 0x7f ; GFX9-NEXT: s_mov_b32 s19, 0 -; GFX9-NEXT: s_sub_i32 s28, 64, 1 ; GFX9-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX9-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] +; GFX9-NEXT: s_sub_i32 s30, 1, 64 +; GFX9-NEXT: s_sub_i32 s31, 64, 1 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s17, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[26:27], s[0:1], s31 +; GFX9-NEXT: s_lshl_b64 s[28:29], s[2:3], 1 ; GFX9-NEXT: s_lshl_b64 s[24:25], s[0:1], 1 -; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s28 -; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 -; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX9-NEXT: s_or_b64 s[26:27], s[26:27], s[28:29] +; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s30 +; GFX9-NEXT: s_cmp_lg_u32 s17, 0 +; GFX9-NEXT: s_cselect_b64 s[24:25], s[24:25], 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[26:27], s[0:1] +; GFX9-NEXT: s_cmp_lg_u32 s23, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX9-NEXT: s_sub_i32 s23, s16, 64 ; GFX9-NEXT: s_sub_i32 s17, 64, s16 ; GFX9-NEXT: s_cmp_lt_u32 s16, 64 -; GFX9-NEXT: s_cselect_b32 s29, 1, 0 +; GFX9-NEXT: s_cselect_b32 s28, 1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s16, 0 -; GFX9-NEXT: s_cselect_b32 s30, 1, 0 +; GFX9-NEXT: s_cselect_b32 s29, 1, 0 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[24:25], s16 ; GFX9-NEXT: s_lshr_b64 s[26:27], s[24:25], s17 ; GFX9-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 ; GFX9-NEXT: s_or_b64 s[16:17], s[26:27], s[16:17] ; GFX9-NEXT: s_lshl_b64 s[24:25], s[24:25], s23 -; GFX9-NEXT: s_cmp_lg_u32 s29, 0 +; GFX9-NEXT: s_cmp_lg_u32 s28, 0 ; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX9-NEXT: s_cselect_b64 s[16:17], s[16:17], s[24:25] -; GFX9-NEXT: s_cmp_lg_u32 s30, 0 +; GFX9-NEXT: s_cmp_lg_u32 s29, 0 ; GFX9-NEXT: s_cselect_b64 s[16:17], s[0:1], s[16:17] ; GFX9-NEXT: s_sub_i32 s26, s22, 64 ; GFX9-NEXT: s_sub_i32 s24, 64, s22 ; GFX9-NEXT: s_cmp_lt_u32 s22, 64 ; GFX9-NEXT: s_cselect_b32 s27, 1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s22, 0 -; GFX9-NEXT: s_cselect_b32 s29, 1, 0 +; GFX9-NEXT: s_cselect_b32 s28, 1, 0 ; GFX9-NEXT: s_lshr_b64 s[0:1], s[10:11], s22 ; GFX9-NEXT: s_lshl_b64 s[24:25], s[10:11], s24 ; GFX9-NEXT: s_lshr_b64 s[22:23], s[8:9], s22 @@ -6278,18 +6856,28 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], s26 ; GFX9-NEXT: s_cmp_lg_u32 s27, 0 ; GFX9-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11] -; GFX9-NEXT: s_cmp_lg_u32 s29, 0 +; GFX9-NEXT: s_cmp_lg_u32 s28, 0 ; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX9-NEXT: s_cmp_lg_u32 s27, 0 ; GFX9-NEXT: s_cselect_b64 s[10:11], s[0:1], 0 ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[8:9] ; GFX9-NEXT: s_or_b64 s[2:3], s[16:17], s[10:11] -; GFX9-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX9-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] +; GFX9-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[18:19], s[4:5], s31 +; GFX9-NEXT: s_lshl_b64 s[20:21], s[6:7], 1 ; GFX9-NEXT: s_lshl_b64 s[16:17], s[4:5], 1 -; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s28 -; GFX9-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 -; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; GFX9-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] +; GFX9-NEXT: s_lshl_b64 s[4:5], s[4:5], s30 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: s_cselect_b64 s[16:17], s[16:17], 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], s[18:19], s[4:5] +; GFX9-NEXT: s_cmp_lg_u32 s11, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] ; GFX9-NEXT: s_sub_i32 s9, s10, 64 ; GFX9-NEXT: s_sub_i32 s11, 64, s10 ; GFX9-NEXT: s_cmp_lt_u32 s10, 64 @@ -6329,37 +6917,48 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; ; GFX10-LABEL: s_fshr_v2i128: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_sub_i32 s28, 64, 1 ; GFX10-NEXT: s_movk_i32 s18, 0x7f ; GFX10-NEXT: s_mov_b32 s19, 0 -; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s28 -; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 +; GFX10-NEXT: s_sub_i32 s30, 1, 64 ; GFX10-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX10-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] -; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 -; GFX10-NEXT: s_or_b64 s[2:3], s[24:25], s[2:3] +; GFX10-NEXT: s_sub_i32 s31, 64, 1 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: s_cselect_b32 s23, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s31 +; GFX10-NEXT: s_lshl_b64 s[26:27], s[2:3], 1 +; GFX10-NEXT: s_lshl_b64 s[28:29], s[0:1], 1 +; GFX10-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27] +; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s30 +; GFX10-NEXT: s_cmp_lg_u32 s17, 0 +; GFX10-NEXT: s_cselect_b64 s[26:27], s[28:29], 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1] +; GFX10-NEXT: s_cmp_lg_u32 s23, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX10-NEXT: s_sub_i32 s23, s16, 64 -; GFX10-NEXT: s_sub_i32 s17, 64, s16 +; GFX10-NEXT: s_sub_i32 s2, 64, s16 ; GFX10-NEXT: s_cmp_lt_u32 s16, 64 -; GFX10-NEXT: s_cselect_b32 s29, 1, 0 +; GFX10-NEXT: s_cselect_b32 s28, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s16, 0 -; GFX10-NEXT: s_cselect_b32 s30, 1, 0 -; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s17 -; GFX10-NEXT: s_lshl_b64 s[26:27], s[2:3], s16 -; GFX10-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 -; GFX10-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27] -; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s23 -; GFX10-NEXT: s_cmp_lg_u32 s29, 0 +; GFX10-NEXT: s_cselect_b32 s29, 1, 0 +; GFX10-NEXT: s_lshl_b64 s[24:25], s[0:1], s16 +; GFX10-NEXT: s_lshr_b64 s[2:3], s[26:27], s2 +; GFX10-NEXT: s_lshl_b64 s[16:17], s[26:27], s16 +; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[24:25] +; GFX10-NEXT: s_lshl_b64 s[24:25], s[26:27], s23 +; GFX10-NEXT: s_cmp_lg_u32 s28, 0 ; GFX10-NEXT: s_cselect_b64 s[16:17], s[16:17], 0 -; GFX10-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1] -; GFX10-NEXT: s_cmp_lg_u32 s30, 0 -; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] +; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[24:25] +; GFX10-NEXT: s_cmp_lg_u32 s29, 0 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[0:1], s[2:3] ; GFX10-NEXT: s_sub_i32 s26, s22, 64 ; GFX10-NEXT: s_sub_i32 s23, 64, s22 ; GFX10-NEXT: s_cmp_lt_u32 s22, 64 ; GFX10-NEXT: s_cselect_b32 s27, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s22, 0 -; GFX10-NEXT: s_cselect_b32 s29, 1, 0 +; GFX10-NEXT: s_cselect_b32 s28, 1, 0 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[8:9], s22 ; GFX10-NEXT: s_lshl_b64 s[24:25], s[10:11], s23 ; GFX10-NEXT: s_lshr_b64 s[22:23], s[10:11], s22 @@ -6367,34 +6966,44 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr ; GFX10-NEXT: s_lshr_b64 s[10:11], s[10:11], s26 ; GFX10-NEXT: s_cmp_lg_u32 s27, 0 ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11] -; GFX10-NEXT: s_cmp_lg_u32 s29, 0 +; GFX10-NEXT: s_cmp_lg_u32 s28, 0 ; GFX10-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] ; GFX10-NEXT: s_cmp_lg_u32 s27, 0 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[22:23], 0 -; GFX10-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX10-NEXT: s_or_b64 s[0:1], s[16:17], s[0:1] -; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s28 -; GFX10-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX10-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] -; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], 1 -; GFX10-NEXT: s_or_b64 s[6:7], s[16:17], s[6:7] +; GFX10-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: s_cselect_b32 s11, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s31 +; GFX10-NEXT: s_lshl_b64 s[18:19], s[6:7], 1 +; GFX10-NEXT: s_lshl_b64 s[20:21], s[4:5], 1 +; GFX10-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] +; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], s30 +; GFX10-NEXT: s_cmp_lg_u32 s9, 0 +; GFX10-NEXT: s_cselect_b64 s[18:19], s[20:21], 0 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5] +; GFX10-NEXT: s_cmp_lg_u32 s11, 0 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] ; GFX10-NEXT: s_sub_i32 s9, s10, 64 -; GFX10-NEXT: s_sub_i32 s11, 64, s10 +; GFX10-NEXT: s_sub_i32 s6, 64, s10 ; GFX10-NEXT: s_cmp_lt_u32 s10, 64 ; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s10, 0 ; GFX10-NEXT: s_cselect_b32 s21, 1, 0 -; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s11 -; GFX10-NEXT: s_lshl_b64 s[18:19], s[6:7], s10 -; GFX10-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 -; GFX10-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] -; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], s9 +; GFX10-NEXT: s_lshl_b64 s[16:17], s[4:5], s10 +; GFX10-NEXT: s_lshr_b64 s[6:7], s[18:19], s6 +; GFX10-NEXT: s_lshl_b64 s[10:11], s[18:19], s10 +; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[16:17] +; GFX10-NEXT: s_lshl_b64 s[16:17], s[18:19], s9 ; GFX10-NEXT: s_cmp_lg_u32 s20, 0 ; GFX10-NEXT: s_cselect_b64 s[10:11], s[10:11], 0 -; GFX10-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5] +; GFX10-NEXT: s_cselect_b64 s[6:7], s[6:7], s[16:17] ; GFX10-NEXT: s_cmp_lg_u32 s21, 0 -; GFX10-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] +; GFX10-NEXT: s_cselect_b64 s[6:7], s[4:5], s[6:7] ; GFX10-NEXT: s_sub_i32 s18, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 @@ -6424,381 +7033,505 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_sub_i32 s6, 64, 1 +; GFX6-NEXT: s_sub_i32 s7, 1, 64 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 ; GFX6-NEXT: v_lshr_b64 v[17:18], v[0:1], s6 -; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GFX6-NEXT: s_movk_i32 s7, 0x7f -; GFX6-NEXT: v_or_b32_e32 v2, v17, v2 -; GFX6-NEXT: v_xor_b32_e32 v17, -1, v16 -; GFX6-NEXT: v_and_b32_e32 v23, s7, v17 -; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 -; GFX6-NEXT: v_or_b32_e32 v3, v18, v3 -; GFX6-NEXT: v_sub_i32_e32 v17, vcc, 64, v23 -; GFX6-NEXT: v_and_b32_e32 v24, s7, v16 -; GFX6-NEXT: v_lshr_b64 v[17:18], v[0:1], v17 -; GFX6-NEXT: v_lshl_b64 v[21:22], v[2:3], v23 -; GFX6-NEXT: v_sub_i32_e32 v16, vcc, 64, v24 -; GFX6-NEXT: v_or_b32_e32 v21, v17, v21 -; GFX6-NEXT: v_or_b32_e32 v22, v18, v22 -; GFX6-NEXT: v_lshl_b64 v[16:17], v[10:11], v16 -; GFX6-NEXT: v_lshr_b64 v[18:19], v[8:9], v24 -; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v23 -; GFX6-NEXT: v_or_b32_e32 v18, v18, v16 -; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, 64, v23 -; GFX6-NEXT: v_or_b32_e32 v19, v19, v17 -; GFX6-NEXT: v_lshl_b64 v[16:17], v[0:1], v16 -; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v23 -; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23 -; GFX6-NEXT: v_cndmask_b32_e32 v25, 0, v0, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v21, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v16, v17, v22, vcc -; GFX6-NEXT: v_cndmask_b32_e64 v17, v0, v2, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v16, v16, v3, s[4:5] -; GFX6-NEXT: v_subrev_i32_e64 v0, s[4:5], 64, v24 -; GFX6-NEXT: v_lshr_b64 v[2:3], v[10:11], v0 -; GFX6-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v24 -; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v18, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e32 v18, 0, v1, vcc -; GFX6-NEXT: v_lshr_b64 v[0:1], v[10:11], v24 -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24 -; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v19, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc -; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, v0, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc -; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, v1, s[4:5] -; GFX6-NEXT: v_or_b32_e32 v0, v25, v2 -; GFX6-NEXT: v_or_b32_e32 v2, v17, v8 +; GFX6-NEXT: v_lshl_b64 v[21:22], v[2:3], 1 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: v_or_b32_e32 v19, v17, v21 +; GFX6-NEXT: v_or_b32_e32 v21, v18, v22 +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: v_lshl_b64 v[17:18], v[0:1], 1 +; GFX6-NEXT: s_and_b32 s4, 1, s4 +; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s7 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_and_b32 s4, 1, s5 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v19, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] +; GFX6-NEXT: s_movk_i32 s8, 0x7f +; GFX6-NEXT: v_xor_b32_e32 v2, -1, v16 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v21, vcc +; GFX6-NEXT: v_and_b32_e32 v19, s8, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v18, 0, v18, vcc +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v19 +; GFX6-NEXT: v_lshr_b64 v[2:3], v[17:18], v2 +; GFX6-NEXT: v_lshl_b64 v[21:22], v[0:1], v19 +; GFX6-NEXT: v_and_b32_e32 v25, s8, v16 +; GFX6-NEXT: v_or_b32_e32 v23, v2, v21 +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v25 +; GFX6-NEXT: v_or_b32_e32 v24, v3, v22 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[10:11], v2 +; GFX6-NEXT: v_lshr_b64 v[21:22], v[8:9], v25 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v19 +; GFX6-NEXT: v_or_b32_e32 v21, v21, v2 +; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 64, v19 +; GFX6-NEXT: v_or_b32_e32 v22, v22, v3 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[17:18], v2 +; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v19 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v23, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v24, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v0, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v1, s[4:5] +; GFX6-NEXT: v_subrev_i32_e64 v0, s[4:5], 64, v25 +; GFX6-NEXT: v_lshl_b64 v[16:17], v[17:18], v19 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[10:11], v0 +; GFX6-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v25 +; GFX6-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v18, v0, v21, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e64 v19, v1, v22, s[4:5] +; GFX6-NEXT: v_lshr_b64 v[0:1], v[10:11], v25 +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v25 +; GFX6-NEXT: v_cndmask_b32_e32 v8, v18, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, v0, s[4:5] +; GFX6-NEXT: v_or_b32_e32 v0, v16, v8 +; GFX6-NEXT: v_cndmask_b32_e64 v11, 0, v1, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v9, v19, v9, vcc ; GFX6-NEXT: v_xor_b32_e32 v8, -1, v20 -; GFX6-NEXT: v_or_b32_e32 v1, v18, v3 -; GFX6-NEXT: v_or_b32_e32 v3, v16, v9 -; GFX6-NEXT: v_and_b32_e32 v17, s7, v8 +; GFX6-NEXT: v_or_b32_e32 v1, v17, v9 +; GFX6-NEXT: v_and_b32_e32 v17, s8, v8 +; GFX6-NEXT: s_cmp_lt_u32 1, 64 +; GFX6-NEXT: v_or_b32_e32 v2, v2, v10 +; GFX6-NEXT: v_or_b32_e32 v3, v3, v11 ; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], s6 -; GFX6-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 -; GFX6-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 -; GFX6-NEXT: v_or_b32_e32 v6, v8, v6 -; GFX6-NEXT: v_or_b32_e32 v7, v9, v7 -; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v17 -; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], v8 -; GFX6-NEXT: v_lshl_b64 v[10:11], v[6:7], v17 -; GFX6-NEXT: v_subrev_i32_e32 v18, vcc, 64, v17 +; GFX6-NEXT: v_lshl_b64 v[10:11], v[6:7], 1 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 1, 0 +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_and_b32 s4, 1, s4 ; GFX6-NEXT: v_or_b32_e32 v10, v8, v10 ; GFX6-NEXT: v_or_b32_e32 v11, v9, v11 -; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v17 -; GFX6-NEXT: v_lshl_b64 v[4:5], v[4:5], v18 -; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17 -; GFX6-NEXT: v_and_b32_e32 v16, s7, v20 +; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], 1 +; GFX6-NEXT: v_lshl_b64 v[4:5], v[4:5], s7 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_and_b32 s4, 1, s5 ; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 64, v17 +; GFX6-NEXT: v_lshr_b64 v[6:7], v[8:9], v6 +; GFX6-NEXT: v_lshl_b64 v[10:11], v[4:5], v17 +; GFX6-NEXT: v_subrev_i32_e32 v18, vcc, 64, v17 +; GFX6-NEXT: v_or_b32_e32 v10, v6, v10 +; GFX6-NEXT: v_or_b32_e32 v11, v7, v11 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[8:9], v17 +; GFX6-NEXT: v_lshl_b64 v[8:9], v[8:9], v18 +; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17 +; GFX6-NEXT: v_and_b32_e32 v16, s8, v20 +; GFX6-NEXT: v_cndmask_b32_e32 v18, 0, v6, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v19, 0, v7, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v17 -; GFX6-NEXT: v_cndmask_b32_e32 v10, v4, v6, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v11, v5, v7, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v8, v6, v4, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v9, v7, v5, vcc ; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 64, v16 ; GFX6-NEXT: v_lshr_b64 v[4:5], v[12:13], v16 ; GFX6-NEXT: v_lshl_b64 v[6:7], v[14:15], v6 -; GFX6-NEXT: v_subrev_i32_e32 v17, vcc, 64, v16 -; GFX6-NEXT: v_or_b32_e32 v18, v4, v6 -; GFX6-NEXT: v_or_b32_e32 v19, v5, v7 -; GFX6-NEXT: v_lshr_b64 v[6:7], v[14:15], v17 +; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, 64, v16 +; GFX6-NEXT: v_or_b32_e32 v11, v4, v6 +; GFX6-NEXT: v_or_b32_e32 v17, v5, v7 +; GFX6-NEXT: v_lshr_b64 v[6:7], v[14:15], v10 ; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16 ; GFX6-NEXT: v_lshr_b64 v[4:5], v[14:15], v16 -; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v18, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc ; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16 -; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v19, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e32 v12, 0, v4, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v13, 0, v5, vcc -; GFX6-NEXT: v_or_b32_e32 v4, v8, v6 -; GFX6-NEXT: v_or_b32_e32 v5, v9, v7 -; GFX6-NEXT: v_or_b32_e32 v6, v10, v12 -; GFX6-NEXT: v_or_b32_e32 v7, v11, v13 +; GFX6-NEXT: v_cndmask_b32_e32 v11, 0, v5, vcc +; GFX6-NEXT: v_or_b32_e32 v4, v18, v6 +; GFX6-NEXT: v_or_b32_e32 v5, v19, v7 +; GFX6-NEXT: v_or_b32_e32 v6, v8, v10 +; GFX6-NEXT: v_or_b32_e32 v7, v9, v11 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_fshr_v2i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_sub_i32 s6, 64, 1 +; GFX8-NEXT: s_sub_i32 s7, 1, 64 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 ; GFX8-NEXT: v_lshrrev_b64 v[17:18], s6, v[0:1] -; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] -; GFX8-NEXT: s_movk_i32 s7, 0x7f -; GFX8-NEXT: v_or_b32_e32 v2, v17, v2 -; GFX8-NEXT: v_xor_b32_e32 v17, -1, v16 -; GFX8-NEXT: v_and_b32_e32 v23, s7, v17 -; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] -; GFX8-NEXT: v_or_b32_e32 v3, v18, v3 -; GFX8-NEXT: v_sub_u32_e32 v17, vcc, 64, v23 -; GFX8-NEXT: v_and_b32_e32 v24, s7, v16 -; GFX8-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1] -; GFX8-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3] -; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v24 -; GFX8-NEXT: v_or_b32_e32 v21, v17, v21 -; GFX8-NEXT: v_or_b32_e32 v22, v18, v22 -; GFX8-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11] -; GFX8-NEXT: v_lshrrev_b64 v[18:19], v24, v[8:9] -; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v23 -; GFX8-NEXT: v_or_b32_e32 v18, v18, v16 -; GFX8-NEXT: v_subrev_u32_e32 v16, vcc, 64, v23 -; GFX8-NEXT: v_or_b32_e32 v19, v19, v17 -; GFX8-NEXT: v_lshlrev_b64 v[16:17], v16, v[0:1] -; GFX8-NEXT: v_lshlrev_b64 v[0:1], v23, v[0:1] -; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v25, 0, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v21, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v16, v17, v22, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v17, v0, v2, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, v3, s[4:5] -; GFX8-NEXT: v_subrev_u32_e64 v0, s[4:5], 64, v24 -; GFX8-NEXT: v_lshrrev_b64 v[2:3], v0, v[10:11] -; GFX8-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v24 -; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v18, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v18, 0, v1, vcc -; GFX8-NEXT: v_lshrrev_b64 v[0:1], v24, v[10:11] -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24 -; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v19, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v0, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, v1, s[4:5] -; GFX8-NEXT: v_or_b32_e32 v0, v25, v2 -; GFX8-NEXT: v_or_b32_e32 v2, v17, v8 +; GFX8-NEXT: v_lshlrev_b64 v[21:22], 1, v[2:3] +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: v_or_b32_e32 v19, v17, v21 +; GFX8-NEXT: v_or_b32_e32 v21, v18, v22 +; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: v_lshlrev_b64 v[17:18], 1, v[0:1] +; GFX8-NEXT: s_and_b32 s4, 1, s4 +; GFX8-NEXT: v_lshlrev_b64 v[0:1], s7, v[0:1] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_and_b32 s4, 1, s5 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v19, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] +; GFX8-NEXT: s_movk_i32 s8, 0x7f +; GFX8-NEXT: v_xor_b32_e32 v2, -1, v16 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v21, vcc +; GFX8-NEXT: v_and_b32_e32 v19, s8, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v18, 0, v18, vcc +; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 64, v19 +; GFX8-NEXT: v_lshrrev_b64 v[2:3], v2, v[17:18] +; GFX8-NEXT: v_lshlrev_b64 v[21:22], v19, v[0:1] +; GFX8-NEXT: v_and_b32_e32 v25, s8, v16 +; GFX8-NEXT: v_or_b32_e32 v23, v2, v21 +; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 64, v25 +; GFX8-NEXT: v_or_b32_e32 v24, v3, v22 +; GFX8-NEXT: v_lshlrev_b64 v[2:3], v2, v[10:11] +; GFX8-NEXT: v_lshrrev_b64 v[21:22], v25, v[8:9] +; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v19 +; GFX8-NEXT: v_or_b32_e32 v21, v21, v2 +; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 64, v19 +; GFX8-NEXT: v_or_b32_e32 v22, v22, v3 +; GFX8-NEXT: v_lshlrev_b64 v[2:3], v2, v[17:18] +; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v19 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v23, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v24, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v0, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v1, s[4:5] +; GFX8-NEXT: v_subrev_u32_e64 v0, s[4:5], 64, v25 +; GFX8-NEXT: v_lshlrev_b64 v[16:17], v19, v[17:18] +; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, v[10:11] +; GFX8-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v25 +; GFX8-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v18, v0, v21, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e64 v19, v1, v22, s[4:5] +; GFX8-NEXT: v_lshrrev_b64 v[0:1], v25, v[10:11] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v25 +; GFX8-NEXT: v_cndmask_b32_e32 v8, v18, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v0, s[4:5] +; GFX8-NEXT: v_or_b32_e32 v0, v16, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, v1, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v9, v19, v9, vcc ; GFX8-NEXT: v_xor_b32_e32 v8, -1, v20 -; GFX8-NEXT: v_or_b32_e32 v1, v18, v3 -; GFX8-NEXT: v_or_b32_e32 v3, v16, v9 -; GFX8-NEXT: v_and_b32_e32 v17, s7, v8 +; GFX8-NEXT: v_or_b32_e32 v1, v17, v9 +; GFX8-NEXT: v_and_b32_e32 v17, s8, v8 +; GFX8-NEXT: s_cmp_lt_u32 1, 64 +; GFX8-NEXT: v_or_b32_e32 v2, v2, v10 +; GFX8-NEXT: v_or_b32_e32 v3, v3, v11 ; GFX8-NEXT: v_lshrrev_b64 v[8:9], s6, v[4:5] -; GFX8-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7] -; GFX8-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5] -; GFX8-NEXT: v_or_b32_e32 v6, v8, v6 -; GFX8-NEXT: v_or_b32_e32 v7, v9, v7 -; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v17 -; GFX8-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5] -; GFX8-NEXT: v_lshlrev_b64 v[10:11], v17, v[6:7] -; GFX8-NEXT: v_subrev_u32_e32 v18, vcc, 64, v17 +; GFX8-NEXT: v_lshlrev_b64 v[10:11], 1, v[6:7] +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 1, 0 +; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_and_b32 s4, 1, s4 ; GFX8-NEXT: v_or_b32_e32 v10, v8, v10 ; GFX8-NEXT: v_or_b32_e32 v11, v9, v11 -; GFX8-NEXT: v_lshlrev_b64 v[8:9], v17, v[4:5] -; GFX8-NEXT: v_lshlrev_b64 v[4:5], v18, v[4:5] -; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17 -; GFX8-NEXT: v_and_b32_e32 v16, s7, v20 +; GFX8-NEXT: v_lshlrev_b64 v[8:9], 1, v[4:5] +; GFX8-NEXT: v_lshlrev_b64 v[4:5], s7, v[4:5] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_and_b32 s4, 1, s5 ; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 64, v17 +; GFX8-NEXT: v_lshrrev_b64 v[6:7], v6, v[8:9] +; GFX8-NEXT: v_lshlrev_b64 v[10:11], v17, v[4:5] +; GFX8-NEXT: v_subrev_u32_e32 v18, vcc, 64, v17 +; GFX8-NEXT: v_or_b32_e32 v10, v6, v10 +; GFX8-NEXT: v_or_b32_e32 v11, v7, v11 +; GFX8-NEXT: v_lshlrev_b64 v[6:7], v17, v[8:9] +; GFX8-NEXT: v_lshlrev_b64 v[8:9], v18, v[8:9] +; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17 +; GFX8-NEXT: v_and_b32_e32 v16, s8, v20 +; GFX8-NEXT: v_cndmask_b32_e32 v18, 0, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v19, 0, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v4, v6, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v11, v5, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v6, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v7, v5, vcc ; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 64, v16 ; GFX8-NEXT: v_lshrrev_b64 v[4:5], v16, v[12:13] ; GFX8-NEXT: v_lshlrev_b64 v[6:7], v6, v[14:15] -; GFX8-NEXT: v_subrev_u32_e32 v17, vcc, 64, v16 -; GFX8-NEXT: v_or_b32_e32 v18, v4, v6 -; GFX8-NEXT: v_or_b32_e32 v19, v5, v7 -; GFX8-NEXT: v_lshrrev_b64 v[6:7], v17, v[14:15] +; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, 64, v16 +; GFX8-NEXT: v_or_b32_e32 v11, v4, v6 +; GFX8-NEXT: v_or_b32_e32 v17, v5, v7 +; GFX8-NEXT: v_lshrrev_b64 v[6:7], v10, v[14:15] ; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16 ; GFX8-NEXT: v_lshrrev_b64 v[4:5], v16, v[14:15] -; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v18, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc ; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v19, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v12, 0, v4, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v13, 0, v5, vcc -; GFX8-NEXT: v_or_b32_e32 v4, v8, v6 -; GFX8-NEXT: v_or_b32_e32 v5, v9, v7 -; GFX8-NEXT: v_or_b32_e32 v6, v10, v12 -; GFX8-NEXT: v_or_b32_e32 v7, v11, v13 +; GFX8-NEXT: v_cndmask_b32_e32 v11, 0, v5, vcc +; GFX8-NEXT: v_or_b32_e32 v4, v18, v6 +; GFX8-NEXT: v_or_b32_e32 v5, v19, v7 +; GFX8-NEXT: v_or_b32_e32 v6, v8, v10 +; GFX8-NEXT: v_or_b32_e32 v7, v9, v11 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_fshr_v2i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_sub_i32 s6, 64, 1 +; GFX9-NEXT: s_sub_i32 s7, 1, 64 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 ; GFX9-NEXT: v_lshrrev_b64 v[17:18], s6, v[0:1] -; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] -; GFX9-NEXT: s_movk_i32 s7, 0x7f -; GFX9-NEXT: v_or_b32_e32 v2, v17, v2 -; GFX9-NEXT: v_xor_b32_e32 v17, -1, v16 -; GFX9-NEXT: v_and_b32_e32 v23, s7, v17 -; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] -; GFX9-NEXT: v_or_b32_e32 v3, v18, v3 -; GFX9-NEXT: v_sub_u32_e32 v17, 64, v23 -; GFX9-NEXT: v_and_b32_e32 v24, s7, v16 -; GFX9-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1] -; GFX9-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3] -; GFX9-NEXT: v_sub_u32_e32 v16, 64, v24 -; GFX9-NEXT: v_or_b32_e32 v21, v17, v21 -; GFX9-NEXT: v_or_b32_e32 v22, v18, v22 -; GFX9-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11] -; GFX9-NEXT: v_lshrrev_b64 v[18:19], v24, v[8:9] -; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23 -; GFX9-NEXT: v_or_b32_e32 v18, v18, v16 -; GFX9-NEXT: v_subrev_u32_e32 v16, 64, v23 -; GFX9-NEXT: v_or_b32_e32 v19, v19, v17 -; GFX9-NEXT: v_lshlrev_b64 v[16:17], v16, v[0:1] -; GFX9-NEXT: v_lshlrev_b64 v[0:1], v23, v[0:1] -; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v23 -; GFX9-NEXT: v_cndmask_b32_e32 v25, 0, v0, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v21, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v22, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v17, v0, v2, s[4:5] -; GFX9-NEXT: v_subrev_u32_e32 v0, 64, v24 -; GFX9-NEXT: v_cndmask_b32_e64 v16, v16, v3, s[4:5] -; GFX9-NEXT: v_lshrrev_b64 v[2:3], v0, v[10:11] -; GFX9-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v24 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v18, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v1, vcc -; GFX9-NEXT: v_lshrrev_b64 v[0:1], v24, v[10:11] -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v19, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v0, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, v1, s[4:5] -; GFX9-NEXT: v_or_b32_e32 v0, v25, v2 -; GFX9-NEXT: v_or_b32_e32 v2, v17, v8 +; GFX9-NEXT: v_lshlrev_b64 v[21:22], 1, v[2:3] +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: v_or_b32_e32 v19, v17, v21 +; GFX9-NEXT: v_or_b32_e32 v21, v18, v22 +; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: v_lshlrev_b64 v[17:18], 1, v[0:1] +; GFX9-NEXT: s_and_b32 s4, 1, s4 +; GFX9-NEXT: v_lshlrev_b64 v[0:1], s7, v[0:1] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_and_b32 s4, 1, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v19, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] +; GFX9-NEXT: s_movk_i32 s8, 0x7f +; GFX9-NEXT: v_xor_b32_e32 v2, -1, v16 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v21, vcc +; GFX9-NEXT: v_and_b32_e32 v19, s8, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v18, vcc +; GFX9-NEXT: v_sub_u32_e32 v2, 64, v19 +; GFX9-NEXT: v_lshrrev_b64 v[2:3], v2, v[17:18] +; GFX9-NEXT: v_lshlrev_b64 v[21:22], v19, v[0:1] +; GFX9-NEXT: v_and_b32_e32 v25, s8, v16 +; GFX9-NEXT: v_or_b32_e32 v23, v2, v21 +; GFX9-NEXT: v_sub_u32_e32 v2, 64, v25 +; GFX9-NEXT: v_or_b32_e32 v24, v3, v22 +; GFX9-NEXT: v_lshlrev_b64 v[2:3], v2, v[10:11] +; GFX9-NEXT: v_lshrrev_b64 v[21:22], v25, v[8:9] +; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v19 +; GFX9-NEXT: v_or_b32_e32 v21, v21, v2 +; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v19 +; GFX9-NEXT: v_or_b32_e32 v22, v22, v3 +; GFX9-NEXT: v_lshlrev_b64 v[2:3], v2, v[17:18] +; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v19 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v23, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v24, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v0, s[4:5] +; GFX9-NEXT: v_subrev_u32_e32 v0, 64, v25 +; GFX9-NEXT: v_lshlrev_b64 v[16:17], v19, v[17:18] +; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v1, s[4:5] +; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, v[10:11] +; GFX9-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v25 +; GFX9-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v18, v0, v21, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e64 v19, v1, v22, s[4:5] +; GFX9-NEXT: v_lshrrev_b64 v[0:1], v25, v[10:11] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v25 +; GFX9-NEXT: v_cndmask_b32_e32 v8, v18, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, v0, s[4:5] +; GFX9-NEXT: v_or_b32_e32 v0, v16, v8 +; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, v1, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v9, v19, v9, vcc ; GFX9-NEXT: v_xor_b32_e32 v8, -1, v20 -; GFX9-NEXT: v_or_b32_e32 v1, v18, v3 -; GFX9-NEXT: v_and_b32_e32 v17, s7, v8 -; GFX9-NEXT: v_or_b32_e32 v3, v16, v9 +; GFX9-NEXT: v_or_b32_e32 v1, v17, v9 +; GFX9-NEXT: v_and_b32_e32 v17, s8, v8 +; GFX9-NEXT: s_cmp_lt_u32 1, 64 +; GFX9-NEXT: v_or_b32_e32 v2, v2, v10 +; GFX9-NEXT: v_or_b32_e32 v3, v3, v11 ; GFX9-NEXT: v_lshrrev_b64 v[8:9], s6, v[4:5] -; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7] -; GFX9-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5] -; GFX9-NEXT: v_or_b32_e32 v6, v8, v6 -; GFX9-NEXT: v_or_b32_e32 v7, v9, v7 -; GFX9-NEXT: v_sub_u32_e32 v8, 64, v17 -; GFX9-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5] -; GFX9-NEXT: v_lshlrev_b64 v[10:11], v17, v[6:7] -; GFX9-NEXT: v_subrev_u32_e32 v18, 64, v17 +; GFX9-NEXT: v_lshlrev_b64 v[10:11], 1, v[6:7] +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 1, 0 +; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_and_b32 s4, 1, s4 ; GFX9-NEXT: v_or_b32_e32 v10, v8, v10 ; GFX9-NEXT: v_or_b32_e32 v11, v9, v11 -; GFX9-NEXT: v_lshlrev_b64 v[8:9], v17, v[4:5] -; GFX9-NEXT: v_lshlrev_b64 v[4:5], v18, v[4:5] -; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17 -; GFX9-NEXT: v_and_b32_e32 v16, s7, v20 +; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[4:5] +; GFX9-NEXT: v_lshlrev_b64 v[4:5], s7, v[4:5] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_and_b32 s4, 1, s5 ; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX9-NEXT: v_sub_u32_e32 v6, 64, v17 +; GFX9-NEXT: v_lshrrev_b64 v[6:7], v6, v[8:9] +; GFX9-NEXT: v_lshlrev_b64 v[10:11], v17, v[4:5] +; GFX9-NEXT: v_subrev_u32_e32 v18, 64, v17 +; GFX9-NEXT: v_or_b32_e32 v10, v6, v10 +; GFX9-NEXT: v_or_b32_e32 v11, v7, v11 +; GFX9-NEXT: v_lshlrev_b64 v[6:7], v17, v[8:9] +; GFX9-NEXT: v_lshlrev_b64 v[8:9], v18, v[8:9] +; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17 +; GFX9-NEXT: v_and_b32_e32 v16, s8, v20 +; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v19, 0, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v17 -; GFX9-NEXT: v_cndmask_b32_e32 v10, v4, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v8, v6, v4, vcc ; GFX9-NEXT: v_sub_u32_e32 v6, 64, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v5, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v9, v7, v5, vcc ; GFX9-NEXT: v_lshrrev_b64 v[4:5], v16, v[12:13] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], v6, v[14:15] -; GFX9-NEXT: v_subrev_u32_e32 v17, 64, v16 -; GFX9-NEXT: v_or_b32_e32 v18, v4, v6 -; GFX9-NEXT: v_or_b32_e32 v19, v5, v7 -; GFX9-NEXT: v_lshrrev_b64 v[6:7], v17, v[14:15] +; GFX9-NEXT: v_subrev_u32_e32 v10, 64, v16 +; GFX9-NEXT: v_or_b32_e32 v11, v4, v6 +; GFX9-NEXT: v_or_b32_e32 v17, v5, v7 +; GFX9-NEXT: v_lshrrev_b64 v[6:7], v10, v[14:15] ; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16 ; GFX9-NEXT: v_lshrrev_b64 v[4:5], v16, v[14:15] -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v18, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc ; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v19, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v12, 0, v4, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v5, vcc -; GFX9-NEXT: v_or_b32_e32 v4, v8, v6 -; GFX9-NEXT: v_or_b32_e32 v5, v9, v7 -; GFX9-NEXT: v_or_b32_e32 v6, v10, v12 -; GFX9-NEXT: v_or_b32_e32 v7, v11, v13 +; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v5, vcc +; GFX9-NEXT: v_or_b32_e32 v4, v18, v6 +; GFX9-NEXT: v_or_b32_e32 v5, v19, v7 +; GFX9-NEXT: v_or_b32_e32 v6, v8, v10 +; GFX9-NEXT: v_or_b32_e32 v7, v9, v11 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_fshr_v2i128: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_xor_b32_e32 v19, -1, v16 ; GFX10-NEXT: s_sub_i32 s5, 64, 1 -; GFX10-NEXT: s_movk_i32 s6, 0x7f +; GFX10-NEXT: s_sub_i32 s6, 1, 64 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 ; GFX10-NEXT: v_lshrrev_b64 v[17:18], s5, v[0:1] -; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] -; GFX10-NEXT: v_and_b32_e32 v25, s6, v19 -; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] -; GFX10-NEXT: v_and_b32_e32 v26, s6, v16 -; GFX10-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7] -; GFX10-NEXT: v_or_b32_e32 v2, v17, v2 -; GFX10-NEXT: v_or_b32_e32 v3, v18, v3 -; GFX10-NEXT: v_sub_nc_u32_e32 v17, 64, v25 +; GFX10-NEXT: v_lshlrev_b64 v[21:22], 1, v[2:3] +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: v_lshlrev_b64 v[23:24], 1, v[0:1] +; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_and_b32 s4, 1, vcc_lo +; GFX10-NEXT: v_lshlrev_b64 v[0:1], s6, v[0:1] +; GFX10-NEXT: v_or_b32_e32 v21, v17, v21 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4 +; GFX10-NEXT: v_or_b32_e32 v18, v18, v22 +; GFX10-NEXT: v_xor_b32_e32 v19, -1, v16 +; GFX10-NEXT: s_movk_i32 s7, 0x7f +; GFX10-NEXT: s_and_b32 s8, 1, s8 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v21, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v18, s4 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s8 +; GFX10-NEXT: v_and_b32_e32 v25, s7, v19 +; GFX10-NEXT: v_cndmask_b32_e32 v17, 0, v23, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v18, 0, v24, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v26, s7, v16 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 +; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v25 ; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 64, v25 ; GFX10-NEXT: v_sub_nc_u32_e32 v19, 64, v26 -; GFX10-NEXT: v_lshlrev_b64 v[23:24], v25, v[0:1] -; GFX10-NEXT: v_lshlrev_b64 v[21:22], v25, v[2:3] -; GFX10-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1] -; GFX10-NEXT: v_lshlrev_b64 v[0:1], v16, v[0:1] +; GFX10-NEXT: v_lshlrev_b64 v[23:24], v25, v[17:18] +; GFX10-NEXT: v_lshlrev_b64 v[21:22], v25, v[0:1] +; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, v[17:18] ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25 ; GFX10-NEXT: v_subrev_nc_u32_e32 v27, 64, v26 ; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v26 -; GFX10-NEXT: v_or_b32_e32 v21, v17, v21 -; GFX10-NEXT: v_or_b32_e32 v22, v18, v22 +; GFX10-NEXT: s_cmp_lt_u32 1, 64 +; GFX10-NEXT: v_or_b32_e32 v21, v2, v21 +; GFX10-NEXT: v_or_b32_e32 v22, v3, v22 +; GFX10-NEXT: v_lshlrev_b64 v[2:3], v16, v[17:18] ; GFX10-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9] ; GFX10-NEXT: v_lshlrev_b64 v[18:19], v19, v[10:11] ; GFX10-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo -; GFX10-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11] ; GFX10-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v21, v2, v21, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v22, v3, v22, vcc_lo +; GFX10-NEXT: v_lshrrev_b64 v[2:3], v27, v[10:11] ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v25 ; GFX10-NEXT: v_or_b32_e32 v16, v16, v18 ; GFX10-NEXT: v_or_b32_e32 v17, v17, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v21, v2, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v3, vcc_lo -; GFX10-NEXT: v_lshrrev_b64 v[2:3], v26, v[10:11] -; GFX10-NEXT: v_cndmask_b32_e64 v10, v0, v16, s4 -; GFX10-NEXT: v_xor_b32_e32 v16, -1, v20 +; GFX10-NEXT: v_xor_b32_e32 v25, -1, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v18, v21, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v16, s4 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v26 -; GFX10-NEXT: v_cndmask_b32_e64 v11, v1, v17, s4 -; GFX10-NEXT: v_lshrrev_b64 v[0:1], s5, v[4:5] -; GFX10-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5] -; GFX10-NEXT: v_and_b32_e32 v25, s6, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v16, v11, v9, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s4 -; GFX10-NEXT: v_or_b32_e32 v6, v0, v6 -; GFX10-NEXT: v_or_b32_e32 v7, v1, v7 -; GFX10-NEXT: v_sub_nc_u32_e32 v9, 64, v25 -; GFX10-NEXT: v_or_b32_e32 v0, v23, v8 -; GFX10-NEXT: v_and_b32_e32 v23, s6, v20 -; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, v3, s4 -; GFX10-NEXT: v_lshlrev_b64 v[10:11], v25, v[6:7] -; GFX10-NEXT: v_lshrrev_b64 v[8:9], v9, v[4:5] -; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 64, v25 +; GFX10-NEXT: v_lshrrev_b64 v[0:1], v26, v[10:11] +; GFX10-NEXT: v_cndmask_b32_e64 v19, v3, v17, s4 +; GFX10-NEXT: v_lshlrev_b64 v[10:11], 1, v[6:7] +; GFX10-NEXT: v_lshlrev_b64 v[16:17], 1, v[4:5] +; GFX10-NEXT: v_cndmask_b32_e32 v21, v2, v8, vcc_lo +; GFX10-NEXT: v_lshrrev_b64 v[2:3], s5, v[4:5] +; GFX10-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 1, 0 +; GFX10-NEXT: v_lshlrev_b64 v[4:5], s6, v[4:5] +; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_and_b32 s6, 1, s5 +; GFX10-NEXT: v_or_b32_e32 v2, v2, v10 +; GFX10-NEXT: v_cmp_ne_u32_e64 s6, 0, s6 +; GFX10-NEXT: v_or_b32_e32 v3, v3, v11 +; GFX10-NEXT: s_and_b32 s8, 1, s8 +; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v16, s5 +; GFX10-NEXT: v_cndmask_b32_e32 v16, v19, v9, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6 +; GFX10-NEXT: v_and_b32_e32 v25, s7, v25 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, v3, s6 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s8 +; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v17, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v19, 0, v0, s4 +; GFX10-NEXT: v_or_b32_e32 v0, v23, v21 +; GFX10-NEXT: v_and_b32_e32 v23, s7, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v2, v6, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo +; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v25 +; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 64, v25 ; GFX10-NEXT: v_sub_nc_u32_e32 v20, 64, v23 +; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, v1, s4 +; GFX10-NEXT: v_lshlrev_b64 v[10:11], v25, v[3:4] +; GFX10-NEXT: v_lshrrev_b64 v[5:6], v2, v[8:9] ; GFX10-NEXT: v_or_b32_e32 v1, v24, v16 -; GFX10-NEXT: v_or_b32_e32 v2, v18, v2 -; GFX10-NEXT: v_lshlrev_b64 v[16:17], v25, v[4:5] -; GFX10-NEXT: v_or_b32_e32 v10, v8, v10 -; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v23 +; GFX10-NEXT: v_or_b32_e32 v2, v18, v19 +; GFX10-NEXT: v_lshlrev_b64 v[16:17], v25, v[8:9] ; GFX10-NEXT: v_lshrrev_b64 v[18:19], v23, v[12:13] ; GFX10-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15] +; GFX10-NEXT: v_or_b32_e32 v10, v5, v10 +; GFX10-NEXT: v_subrev_nc_u32_e32 v5, 64, v23 ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25 -; GFX10-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5] -; GFX10-NEXT: v_or_b32_e32 v5, v9, v11 -; GFX10-NEXT: v_lshrrev_b64 v[8:9], v8, v[14:15] +; GFX10-NEXT: v_lshlrev_b64 v[7:8], v7, v[8:9] +; GFX10-NEXT: v_or_b32_e32 v9, v6, v11 ; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v23 +; GFX10-NEXT: v_lshrrev_b64 v[5:6], v5, v[14:15] ; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v16, vcc_lo ; GFX10-NEXT: v_or_b32_e32 v16, v18, v20 ; GFX10-NEXT: v_or_b32_e32 v18, v19, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v3, v10, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc_lo -; GFX10-NEXT: v_lshrrev_b64 v[3:4], v23, v[14:15] +; GFX10-NEXT: v_cndmask_b32_e32 v10, v7, v10, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc_lo +; GFX10-NEXT: v_lshrrev_b64 v[7:8], v23, v[14:15] ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v25 -; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v16, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v16, s4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v23 -; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v18, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v18, s4 ; GFX10-NEXT: v_cndmask_b32_e32 v14, 0, v17, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v6, s6 -; GFX10-NEXT: v_cndmask_b32_e64 v7, v5, v7, s6 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v8, v12, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v4, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v8, v9, v13, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v3, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v3, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v4, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, v12, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, v13, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v7, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, v8, s4 ; GFX10-NEXT: v_or_b32_e32 v3, v22, v26 -; GFX10-NEXT: v_or_b32_e32 v4, v11, v5 -; GFX10-NEXT: v_or_b32_e32 v7, v7, v10 -; GFX10-NEXT: v_or_b32_e32 v5, v14, v8 -; GFX10-NEXT: v_or_b32_e32 v6, v6, v9 +; GFX10-NEXT: v_or_b32_e32 v4, v11, v4 +; GFX10-NEXT: v_or_b32_e32 v5, v14, v5 +; GFX10-NEXT: v_or_b32_e32 v6, v10, v6 +; GFX10-NEXT: v_or_b32_e32 v7, v9, v7 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) ret <2 x i128> %result diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll index 2c68143..520928cd 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll @@ -4766,62 +4766,81 @@ define amdgpu_ps <2 x i64> @s_saddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) { ; GFX6-LABEL: s_saddsat_i128: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_add_u32 s4, s0, s4 -; GFX6-NEXT: s_cselect_b32 s8, 1, 0 -; GFX6-NEXT: s_and_b32 s8, s8, 1 -; GFX6-NEXT: s_cmp_lg_u32 s8, 0 -; GFX6-NEXT: s_addc_u32 s5, s1, s5 -; GFX6-NEXT: s_cselect_b32 s8, 1, 0 -; GFX6-NEXT: s_and_b32 s8, s8, 1 -; GFX6-NEXT: s_cmp_lg_u32 s8, 0 -; GFX6-NEXT: s_addc_u32 s8, s2, s6 +; GFX6-NEXT: s_add_u32 s8, s0, s4 ; GFX6-NEXT: s_cselect_b32 s9, 1, 0 -; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: s_and_b32 s9, s9, 1 -; GFX6-NEXT: v_mov_b32_e32 v2, s0 ; GFX6-NEXT: s_cmp_lg_u32 s9, 0 -; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3] +; GFX6-NEXT: s_addc_u32 s9, s1, s5 +; GFX6-NEXT: s_cselect_b32 s10, 1, 0 +; GFX6-NEXT: s_and_b32 s10, s10, 1 +; GFX6-NEXT: s_cmp_lg_u32 s10, 0 +; GFX6-NEXT: s_addc_u32 s10, s2, s6 +; GFX6-NEXT: s_cselect_b32 s11, 1, 0 +; GFX6-NEXT: v_mov_b32_e32 v3, s1 +; GFX6-NEXT: s_and_b32 s11, s11, 1 +; GFX6-NEXT: v_mov_b32_e32 v2, s0 +; GFX6-NEXT: s_cmp_lg_u32 s11, 0 +; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3] ; GFX6-NEXT: v_mov_b32_e32 v0, s2 -; GFX6-NEXT: s_addc_u32 s9, s3, s7 +; GFX6-NEXT: s_addc_u32 s11, s3, s7 ; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1] -; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0 +; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1] +; GFX6-NEXT: v_cmp_lt_u64_e64 s[0:1], s[4:5], 0 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] -; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 -; GFX6-NEXT: s_ashr_i32 s3, s9, 31 -; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] -; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX6-NEXT: s_ashr_i64 s[0:1], s[8:9], s0 -; GFX6-NEXT: s_add_u32 s0, s0, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 -; GFX6-NEXT: s_and_b32 s2, s2, 1 -; GFX6-NEXT: s_cmp_lg_u32 s2, 0 -; GFX6-NEXT: s_addc_u32 s1, s1, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 -; GFX6-NEXT: s_and_b32 s2, s2, 1 -; GFX6-NEXT: s_cmp_lg_u32 s2, 0 -; GFX6-NEXT: s_addc_u32 s2, s3, 0 +; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1] +; GFX6-NEXT: s_movk_i32 s2, 0x7f ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX6-NEXT: s_cselect_b32 s6, 1, 0 +; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0 +; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[6:7], 0 +; GFX6-NEXT: s_sub_i32 s6, s2, 64 +; GFX6-NEXT: s_sub_i32 s4, 64, s2 +; GFX6-NEXT: s_cmp_lt_u32 s2, 64 +; GFX6-NEXT: s_cselect_b32 s12, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s2, 0 +; GFX6-NEXT: s_cselect_b32 s13, 1, 0 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX6-NEXT: s_ashr_i64 s[0:1], s[10:11], s2 +; GFX6-NEXT: s_lshr_b64 s[2:3], s[8:9], s2 +; GFX6-NEXT: s_lshl_b64 s[4:5], s[10:11], s4 +; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] +; GFX6-NEXT: s_ashr_i32 s4, s11, 31 +; GFX6-NEXT: s_ashr_i64 s[6:7], s[10:11], s6 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX6-NEXT: s_cmp_lg_u32 s13, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX6-NEXT: s_mov_b32 s5, s4 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] +; GFX6-NEXT: s_add_u32 s2, s2, 0 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: s_and_b32 s4, s4, 1 +; GFX6-NEXT: s_cmp_lg_u32 s4, 0 +; GFX6-NEXT: s_addc_u32 s3, s3, 0 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: s_and_b32 s4, s4, 1 +; GFX6-NEXT: s_cmp_lg_u32 s4, 0 +; GFX6-NEXT: s_addc_u32 s0, s0, 0 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX6-NEXT: s_and_b32 s6, s6, 1 -; GFX6-NEXT: s_cmp_lg_u32 s6, 0 +; GFX6-NEXT: s_and_b32 s4, s4, 1 +; GFX6-NEXT: s_cmp_lg_u32 s4, 0 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX6-NEXT: s_addc_u32 s3, s3, 0x80000000 -; GFX6-NEXT: v_mov_b32_e32 v1, s0 -; GFX6-NEXT: v_mov_b32_e32 v2, s1 -; GFX6-NEXT: v_mov_b32_e32 v3, s4 +; GFX6-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX6-NEXT: v_mov_b32_e32 v1, s2 +; GFX6-NEXT: v_mov_b32_e32 v2, s3 +; GFX6-NEXT: v_mov_b32_e32 v3, s8 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX6-NEXT: v_mov_b32_e32 v4, s5 +; GFX6-NEXT: v_mov_b32_e32 v4, s9 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc -; GFX6-NEXT: v_mov_b32_e32 v2, s2 -; GFX6-NEXT: v_mov_b32_e32 v4, s8 -; GFX6-NEXT: v_mov_b32_e32 v3, s3 -; GFX6-NEXT: v_mov_b32_e32 v5, s9 +; GFX6-NEXT: v_mov_b32_e32 v2, s0 +; GFX6-NEXT: v_mov_b32_e32 v3, s1 +; GFX6-NEXT: v_mov_b32_e32 v4, s10 +; GFX6-NEXT: v_mov_b32_e32 v5, s11 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 @@ -4832,68 +4851,87 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) { ; ; GFX8-LABEL: s_saddsat_i128: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_add_u32 s4, s0, s4 -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 -; GFX8-NEXT: s_and_b32 s8, s8, 1 -; GFX8-NEXT: s_cmp_lg_u32 s8, 0 -; GFX8-NEXT: s_addc_u32 s5, s1, s5 -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 -; GFX8-NEXT: s_and_b32 s8, s8, 1 -; GFX8-NEXT: s_cmp_lg_u32 s8, 0 -; GFX8-NEXT: s_addc_u32 s8, s2, s6 +; GFX8-NEXT: s_add_u32 s8, s0, s4 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_and_b32 s9, s9, 1 -; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 +; GFX8-NEXT: s_addc_u32 s9, s1, s5 +; GFX8-NEXT: s_cselect_b32 s10, 1, 0 +; GFX8-NEXT: s_and_b32 s10, s10, 1 +; GFX8-NEXT: s_cmp_lg_u32 s10, 0 +; GFX8-NEXT: s_addc_u32 s10, s2, s6 +; GFX8-NEXT: s_cselect_b32 s11, 1, 0 +; GFX8-NEXT: s_and_b32 s11, s11, 1 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: s_cmp_lg_u32 s11, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 -; GFX8-NEXT: s_addc_u32 s9, s3, s7 -; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3] +; GFX8-NEXT: s_addc_u32 s11, s3, s7 +; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3] ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 -; GFX8-NEXT: s_cmp_eq_u64 s[8:9], s[2:3] +; GFX8-NEXT: s_cmp_eq_u64 s[10:11], s[2:3] ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1] +; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 ; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: v_cmp_lt_u64_e64 s[0:1], s[4:5], 0 ; GFX8-NEXT: s_cmp_eq_u64 s[6:7], 0 -; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] -; GFX8-NEXT: s_and_b32 s0, 1, s2 -; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] -; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX8-NEXT: s_ashr_i32 s3, s9, 31 -; GFX8-NEXT: s_ashr_i64 s[0:1], s[8:9], s0 -; GFX8-NEXT: s_add_u32 s0, s0, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 -; GFX8-NEXT: s_and_b32 s2, s2, 1 -; GFX8-NEXT: s_cmp_lg_u32 s2, 0 -; GFX8-NEXT: s_addc_u32 s1, s1, 0 +; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0 ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 -; GFX8-NEXT: s_and_b32 s2, s2, 1 -; GFX8-NEXT: s_cmp_lg_u32 s2, 0 -; GFX8-NEXT: s_addc_u32 s2, s3, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX8-NEXT: s_and_b32 s0, 1, s2 +; GFX8-NEXT: s_movk_i32 s2, 0x7f +; GFX8-NEXT: s_sub_i32 s6, s2, 64 +; GFX8-NEXT: s_sub_i32 s4, 64, s2 +; GFX8-NEXT: s_cmp_lt_u32 s2, 64 +; GFX8-NEXT: s_cselect_b32 s12, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s2, 0 +; GFX8-NEXT: s_cselect_b32 s13, 1, 0 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_ashr_i64 s[0:1], s[10:11], s2 +; GFX8-NEXT: s_lshr_b64 s[2:3], s[8:9], s2 +; GFX8-NEXT: s_lshl_b64 s[4:5], s[10:11], s4 +; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] +; GFX8-NEXT: s_ashr_i32 s4, s11, 31 +; GFX8-NEXT: s_ashr_i64 s[6:7], s[10:11], s6 +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX8-NEXT: s_cmp_lg_u32 s13, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX8-NEXT: s_mov_b32 s5, s4 +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] +; GFX8-NEXT: s_add_u32 s2, s2, 0 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_and_b32 s4, s4, 1 +; GFX8-NEXT: s_cmp_lg_u32 s4, 0 +; GFX8-NEXT: s_addc_u32 s3, s3, 0 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_and_b32 s4, s4, 1 +; GFX8-NEXT: s_cmp_lg_u32 s4, 0 +; GFX8-NEXT: s_addc_u32 s0, s0, 0 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX8-NEXT: s_and_b32 s6, s6, 1 -; GFX8-NEXT: s_cmp_lg_u32 s6, 0 +; GFX8-NEXT: s_and_b32 s4, s4, 1 +; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX8-NEXT: s_addc_u32 s3, s3, 0x80000000 -; GFX8-NEXT: v_mov_b32_e32 v1, s0 -; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: v_mov_b32_e32 v3, s4 +; GFX8-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX8-NEXT: v_mov_b32_e32 v1, s2 +; GFX8-NEXT: v_mov_b32_e32 v2, s3 +; GFX8-NEXT: v_mov_b32_e32 v3, s8 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX8-NEXT: v_mov_b32_e32 v4, s5 +; GFX8-NEXT: v_mov_b32_e32 v4, s9 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc -; GFX8-NEXT: v_mov_b32_e32 v2, s2 -; GFX8-NEXT: v_mov_b32_e32 v4, s8 -; GFX8-NEXT: v_mov_b32_e32 v3, s3 -; GFX8-NEXT: v_mov_b32_e32 v5, s9 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v4, s10 +; GFX8-NEXT: v_mov_b32_e32 v5, s11 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 @@ -4904,68 +4942,87 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) { ; ; GFX9-LABEL: s_saddsat_i128: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_add_u32 s4, s0, s4 -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 -; GFX9-NEXT: s_and_b32 s8, s8, 1 -; GFX9-NEXT: s_cmp_lg_u32 s8, 0 -; GFX9-NEXT: s_addc_u32 s5, s1, s5 -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 -; GFX9-NEXT: s_and_b32 s8, s8, 1 -; GFX9-NEXT: s_cmp_lg_u32 s8, 0 -; GFX9-NEXT: s_addc_u32 s8, s2, s6 +; GFX9-NEXT: s_add_u32 s8, s0, s4 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_and_b32 s9, s9, 1 -; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: s_addc_u32 s9, s1, s5 +; GFX9-NEXT: s_cselect_b32 s10, 1, 0 +; GFX9-NEXT: s_and_b32 s10, s10, 1 +; GFX9-NEXT: s_cmp_lg_u32 s10, 0 +; GFX9-NEXT: s_addc_u32 s10, s2, s6 +; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_and_b32 s11, s11, 1 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: s_cmp_lg_u32 s11, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, s0 -; GFX9-NEXT: s_addc_u32 s9, s3, s7 -; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3] +; GFX9-NEXT: s_addc_u32 s11, s3, s7 +; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3] ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: s_cmp_eq_u64 s[8:9], s[2:3] +; GFX9-NEXT: s_cmp_eq_u64 s[10:11], s[2:3] ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1] +; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: v_cmp_lt_u64_e64 s[0:1], s[4:5], 0 ; GFX9-NEXT: s_cmp_eq_u64 s[6:7], 0 -; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] -; GFX9-NEXT: s_and_b32 s0, 1, s2 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] -; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX9-NEXT: s_ashr_i32 s3, s9, 31 -; GFX9-NEXT: s_ashr_i64 s[0:1], s[8:9], s0 -; GFX9-NEXT: s_add_u32 s0, s0, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 -; GFX9-NEXT: s_and_b32 s2, s2, 1 -; GFX9-NEXT: s_cmp_lg_u32 s2, 0 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0 ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 -; GFX9-NEXT: s_and_b32 s2, s2, 1 -; GFX9-NEXT: s_cmp_lg_u32 s2, 0 -; GFX9-NEXT: s_addc_u32 s2, s3, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX9-NEXT: s_and_b32 s0, 1, s2 +; GFX9-NEXT: s_movk_i32 s2, 0x7f +; GFX9-NEXT: s_sub_i32 s6, s2, 64 +; GFX9-NEXT: s_sub_i32 s4, 64, s2 +; GFX9-NEXT: s_cmp_lt_u32 s2, 64 +; GFX9-NEXT: s_cselect_b32 s12, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s2, 0 +; GFX9-NEXT: s_cselect_b32 s13, 1, 0 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_ashr_i64 s[0:1], s[10:11], s2 +; GFX9-NEXT: s_lshr_b64 s[2:3], s[8:9], s2 +; GFX9-NEXT: s_lshl_b64 s[4:5], s[10:11], s4 +; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] +; GFX9-NEXT: s_ashr_i32 s4, s11, 31 +; GFX9-NEXT: s_ashr_i64 s[6:7], s[10:11], s6 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX9-NEXT: s_cmp_lg_u32 s13, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] +; GFX9-NEXT: s_add_u32 s2, s2, 0 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_and_b32 s4, s4, 1 +; GFX9-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-NEXT: s_addc_u32 s3, s3, 0 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_and_b32 s4, s4, 1 +; GFX9-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-NEXT: s_addc_u32 s0, s0, 0 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX9-NEXT: s_and_b32 s6, s6, 1 -; GFX9-NEXT: s_cmp_lg_u32 s6, 0 +; GFX9-NEXT: s_and_b32 s4, s4, 1 +; GFX9-NEXT: s_cmp_lg_u32 s4, 0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX9-NEXT: s_addc_u32 s3, s3, 0x80000000 -; GFX9-NEXT: v_mov_b32_e32 v1, s0 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX9-NEXT: v_mov_b32_e32 v1, s2 +; GFX9-NEXT: v_mov_b32_e32 v2, s3 +; GFX9-NEXT: v_mov_b32_e32 v3, s8 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-NEXT: v_mov_b32_e32 v4, s9 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, s2 -; GFX9-NEXT: v_mov_b32_e32 v4, s8 -; GFX9-NEXT: v_mov_b32_e32 v3, s3 -; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: v_mov_b32_e32 v4, s10 +; GFX9-NEXT: v_mov_b32_e32 v5, s11 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX9-NEXT: v_readfirstlane_b32 s0, v0 @@ -4976,62 +5033,81 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) { ; ; GFX10-LABEL: s_saddsat_i128: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_add_u32 s4, s0, s4 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 -; GFX10-NEXT: s_and_b32 s8, s8, 1 -; GFX10-NEXT: s_cmp_lg_u32 s8, 0 -; GFX10-NEXT: s_addc_u32 s5, s1, s5 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 -; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[4:5], s[0:1] -; GFX10-NEXT: s_and_b32 s8, s8, 1 -; GFX10-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-NEXT: s_cmp_lg_u32 s8, 0 -; GFX10-NEXT: s_addc_u32 s8, s2, s6 +; GFX10-NEXT: s_add_u32 s8, s0, s4 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX10-NEXT: s_movk_i32 s12, 0x7f ; GFX10-NEXT: s_and_b32 s9, s9, 1 -; GFX10-NEXT: v_mov_b32_e32 v3, s8 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 -; GFX10-NEXT: s_addc_u32 s9, s3, s7 -; GFX10-NEXT: s_cmp_eq_u64 s[8:9], s[2:3] -; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[8:9], s[2:3] +; GFX10-NEXT: s_addc_u32 s9, s1, s5 +; GFX10-NEXT: s_cselect_b32 s10, 1, 0 +; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1] +; GFX10-NEXT: s_and_b32 s10, s10, 1 +; GFX10-NEXT: s_cmp_lg_u32 s10, 0 +; GFX10-NEXT: s_addc_u32 s10, s2, s6 +; GFX10-NEXT: s_cselect_b32 s11, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX10-NEXT: s_and_b32 s11, s11, 1 +; GFX10-NEXT: v_mov_b32_e32 v3, s10 +; GFX10-NEXT: s_cmp_lg_u32 s11, 0 +; GFX10-NEXT: s_addc_u32 s11, s3, s7 +; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[2:3] +; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[10:11], s[2:3] ; GFX10-NEXT: s_cselect_b32 s0, 1, 0 -; GFX10-NEXT: v_mov_b32_e32 v4, s9 +; GFX10-NEXT: v_mov_b32_e32 v4, s11 ; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: s_cmp_eq_u64 s[6:7], 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 -; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[6:7], 0 +; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[4:5], 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 ; GFX10-NEXT: s_cselect_b32 s1, 1, 0 -; GFX10-NEXT: s_ashr_i32 s3, s9, 31 +; GFX10-NEXT: s_sub_i32 s13, s12, 64 +; GFX10-NEXT: s_and_b32 s14, 1, s1 +; GFX10-NEXT: s_sub_i32 s15, 64, s12 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo +; GFX10-NEXT: s_cmp_lt_u32 s12, 64 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 -; GFX10-NEXT: s_and_b32 s0, 1, s1 -; GFX10-NEXT: s_sub_i32 s1, 0x7f, 64 -; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0 -; GFX10-NEXT: s_ashr_i64 s[0:1], s[8:9], s1 -; GFX10-NEXT: s_add_u32 s0, s0, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[6:7], 0 +; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s12, 0 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s14 +; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[2:3], s[8:9], s12 +; GFX10-NEXT: s_lshl_b64 s[4:5], s[10:11], s15 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; GFX10-NEXT: s_ashr_i32 s6, s11, 31 +; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] +; GFX10-NEXT: s_ashr_i64 s[0:1], s[10:11], s12 +; GFX10-NEXT: s_ashr_i64 s[4:5], s[10:11], s13 +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: s_mov_b32 s7, s6 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] +; GFX10-NEXT: s_cmp_lg_u32 s17, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo +; GFX10-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: v_mov_b32_e32 v2, s9 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7] +; GFX10-NEXT: s_add_u32 s2, s2, 0 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX10-NEXT: s_and_b32 s2, s2, 1 -; GFX10-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-NEXT: s_cmp_lg_u32 s2, 0 -; GFX10-NEXT: s_addc_u32 s1, s1, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_and_b32 s4, s4, 1 +; GFX10-NEXT: v_mov_b32_e32 v1, s8 +; GFX10-NEXT: s_cmp_lg_u32 s4, 0 +; GFX10-NEXT: s_addc_u32 s3, s3, 0 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_and_b32 s2, s2, 1 -; GFX10-NEXT: s_cmp_lg_u32 s2, 0 -; GFX10-NEXT: s_addc_u32 s2, s3, 0 -; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: s_and_b32 s4, s4, 1 +; GFX10-NEXT: s_cmp_lg_u32 s4, 0 +; GFX10-NEXT: s_addc_u32 s0, s0, 0 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX10-NEXT: s_and_b32 s4, s6, 1 +; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 -; GFX10-NEXT: s_addc_u32 s3, s3, 0x80000000 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, s2, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, s3, vcc_lo +; GFX10-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, s0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, s1, vcc_lo ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2 @@ -5044,142 +5120,240 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) { define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) { ; GFX6-LABEL: saddsat_i128_sv: ; GFX6: ; %bb.0: -; GFX6-NEXT: v_mov_b32_e32 v4, s1 -; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc -; GFX6-NEXT: v_mov_b32_e32 v4, s2 -; GFX6-NEXT: v_mov_b32_e32 v5, s3 -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v2, vcc -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v3, vcc -; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1] -; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[4:5] -; GFX6-NEXT: v_bfrev_b32_e32 v8, 1 -; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[4:5] -; GFX6-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc +; GFX6-NEXT: v_mov_b32_e32 v5, s1 +; GFX6-NEXT: v_add_i32_e32 v4, vcc, s0, v0 +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc +; GFX6-NEXT: v_mov_b32_e32 v6, s2 +; GFX6-NEXT: v_mov_b32_e32 v7, s3 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v6, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc +; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5] +; GFX6-NEXT: s_movk_i32 s0, 0x7f +; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7] +; GFX6-NEXT: s_sub_i32 s1, s0, 64 +; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7] +; GFX6-NEXT: s_sub_i32 s2, 64, s0 +; GFX6-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc +; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[0:1] +; GFX6-NEXT: s_cmp_lt_u32 s0, 64 +; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3] -; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] -; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, 0, vcc -; GFX6-NEXT: v_xor_b32_e32 v6, v2, v6 -; GFX6-NEXT: v_ashr_i64 v[2:3], v[4:5], s0 -; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v5 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v7, vcc -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc -; GFX6-NEXT: v_and_b32_e32 v6, 1, v6 -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], s2 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX6-NEXT: v_xor_b32_e32 v10, v0, v8 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s0 +; GFX6-NEXT: s_cmp_eq_u32 s0, 0 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: v_ashr_i64 v[8:9], v[6:7], s0 +; GFX6-NEXT: s_and_b32 s0, 1, s3 +; GFX6-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX6-NEXT: v_ashr_i64 v[0:1], v[6:7], s1 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: s_and_b32 s0, 1, s4 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v9, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: s_and_b32 s0, 1, s3 +; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc +; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0 +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX6-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc +; GFX6-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: saddsat_i128_sv: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_mov_b32_e32 v4, s1 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 -; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc -; GFX8-NEXT: v_mov_b32_e32 v4, s2 -; GFX8-NEXT: v_mov_b32_e32 v5, s3 -; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v4, v2, vcc -; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v5, v3, vcc -; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1] -; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[4:5] -; GFX8-NEXT: v_bfrev_b32_e32 v8, 1 -; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc +; GFX8-NEXT: v_mov_b32_e32 v5, s1 +; GFX8-NEXT: v_add_u32_e32 v4, vcc, s0, v0 +; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc +; GFX8-NEXT: v_mov_b32_e32 v6, s2 +; GFX8-NEXT: v_mov_b32_e32 v7, s3 +; GFX8-NEXT: v_addc_u32_e32 v6, vcc, v6, v2, vcc +; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc +; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5] +; GFX8-NEXT: s_movk_i32 s0, 0x7f +; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7] +; GFX8-NEXT: s_sub_i32 s1, s0, 64 +; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7] +; GFX8-NEXT: s_sub_i32 s2, 64, s0 +; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc +; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[0:1] +; GFX8-NEXT: s_cmp_lt_u32 s0, 64 +; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3] -; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] -; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, 0, vcc -; GFX8-NEXT: v_xor_b32_e32 v6, v2, v6 -; GFX8-NEXT: v_ashrrev_i64 v[2:3], s0, v[4:5] -; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v5 -; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0, v2 -; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v7, vcc -; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc -; GFX8-NEXT: v_and_b32_e32 v6, 1, v6 -; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX8-NEXT: v_lshlrev_b64 v[2:3], s2, v[6:7] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: v_xor_b32_e32 v10, v0, v8 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX8-NEXT: s_cmp_eq_u32 s0, 0 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] +; GFX8-NEXT: s_and_b32 s0, 1, s3 +; GFX8-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX8-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_and_b32 s0, 1, s4 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v9, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_and_b32 s0, 1, s3 +; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc +; GFX8-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: saddsat_i128_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_mov_b32_e32 v4, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v4, s2 -; GFX9-NEXT: v_mov_b32_e32 v5, s3 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v3, vcc -; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1] -; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[4:5] -; GFX9-NEXT: v_bfrev_b32_e32 v8, 1 -; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc +; GFX9-NEXT: v_mov_b32_e32 v5, s1 +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s0, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v1, vcc +; GFX9-NEXT: v_mov_b32_e32 v6, s2 +; GFX9-NEXT: v_mov_b32_e32 v7, s3 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v3, vcc +; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5] +; GFX9-NEXT: s_movk_i32 s0, 0x7f +; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7] +; GFX9-NEXT: s_sub_i32 s1, s0, 64 +; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7] +; GFX9-NEXT: s_sub_i32 s2, 64, s0 +; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc +; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[0:1] +; GFX9-NEXT: s_cmp_lt_u32 s0, 64 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3] -; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] -; GFX9-NEXT: v_cndmask_b32_e64 v2, v7, 0, vcc -; GFX9-NEXT: v_xor_b32_e32 v6, v2, v6 -; GFX9-NEXT: v_ashrrev_i64 v[2:3], s0, v[4:5] -; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v5 -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v7, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v8, vcc -; GFX9-NEXT: v_and_b32_e32 v6, 1, v6 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX9-NEXT: v_lshlrev_b64 v[2:3], s2, v[6:7] +; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX9-NEXT: v_xor_b32_e32 v10, v0, v8 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX9-NEXT: s_cmp_eq_u32 s0, 0 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] +; GFX9-NEXT: s_and_b32 s0, 1, s3 +; GFX9-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX9-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_and_b32 s0, 1, s4 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v9, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_and_b32 s0, 1, s3 +; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc +; GFX9-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: saddsat_i128_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo -; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1] -; GFX10-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo -; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[4:5] -; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo -; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3] +; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, s0, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo +; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5] +; GFX10-NEXT: s_movk_i32 s0, 0x7f +; GFX10-NEXT: s_sub_i32 s1, 64, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo -; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[4:5] -; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo +; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7] +; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7] +; GFX10-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc_lo +; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, 0, v[0:1] +; GFX10-NEXT: v_lshlrev_b64 v[8:9], s1, v[6:7] +; GFX10-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX10-NEXT: s_sub_i32 s1, s0, 64 +; GFX10-NEXT: s_cmp_lt_u32 s0, 64 +; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo +; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3] +; GFX10-NEXT: v_or_b32_e32 v8, v0, v8 +; GFX10-NEXT: v_or_b32_e32 v9, v1, v9 +; GFX10-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] +; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] -; GFX10-NEXT: v_ashrrev_i32_e32 v7, 31, v5 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo -; GFX10-NEXT: v_xor_b32_e32 v6, v2, v6 -; GFX10-NEXT: v_ashrrev_i64 v[2:3], s0, v[4:5] -; GFX10-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX10-NEXT: v_ashrrev_i64 v[2:3], s1, v[6:7] +; GFX10-NEXT: v_cndmask_b32_e32 v11, v12, v11, vcc_lo +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s0, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo +; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo +; GFX10-NEXT: s_and_b32 s0, 1, s1 +; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 +; GFX10-NEXT: v_ashrrev_i32_e32 v8, 31, v7 +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 +; GFX10-NEXT: v_xor_b32_e32 v9, v11, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, v1, s0 +; GFX10-NEXT: v_and_b32_e32 v8, 1, v9 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo -; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v6 -; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0x80000000, v7, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v6, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v7, s0 +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v8 +; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v2, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v3, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0 ; GFX10-NEXT: ; return to shader part epilog %result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs) %cast = bitcast i128 %result to <4 x float> @@ -5197,29 +5371,54 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) { ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v3, v7, vcc ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1] -; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0 +; GFX6-NEXT: v_cmp_lt_u64_e64 s[0:1], s[0:1], 0 ; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3] -; GFX6-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v7 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3] -; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v7 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] -; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 -; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] -; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX6-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX6-NEXT: v_ashr_i64 v[0:1], v[6:7], s0 -; GFX6-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0 +; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[2:3], 0 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX6-NEXT: s_movk_i32 s0, 0x7f +; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX6-NEXT: s_sub_i32 s2, 64, s0 +; GFX6-NEXT: s_sub_i32 s1, s0, 64 +; GFX6-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX6-NEXT: s_cmp_lt_u32 s0, 64 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s0 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], s2 +; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s0, 0 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: v_ashr_i64 v[8:9], v[6:7], s0 +; GFX6-NEXT: s_and_b32 s0, 1, s3 +; GFX6-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX6-NEXT: v_ashr_i64 v[0:1], v[6:7], s1 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: s_and_b32 s0, 1, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: s_and_b32 s0, 1, s3 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc +; GFX6-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX6-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX6-NEXT: ; return to shader part epilog ; @@ -5233,32 +5432,57 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) { ; GFX8-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v3, v7, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1] -; GFX8-NEXT: s_cmp_eq_u64 s[2:3], 0 +; GFX8-NEXT: v_cmp_lt_u64_e64 s[0:1], s[0:1], 0 ; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3] -; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0 +; GFX8-NEXT: s_cmp_eq_u64 s[2:3], 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3] ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0 +; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s4 -; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] -; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX8-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX8-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] -; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v7 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_movk_i32 s0, 0x7f +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX8-NEXT: s_sub_i32 s2, 64, s0 +; GFX8-NEXT: s_sub_i32 s1, s0, 64 +; GFX8-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX8-NEXT: s_cmp_lt_u32 s0, 64 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX8-NEXT: v_lshlrev_b64 v[2:3], s2, v[6:7] +; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s0, 0 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] +; GFX8-NEXT: s_and_b32 s0, 1, s3 +; GFX8-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX8-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_and_b32 s0, 1, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_and_b32 s0, 1, s3 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_bfrev_b32_e32 v8, 1 -; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc +; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX8-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX8-NEXT: ; return to shader part epilog ; @@ -5272,68 +5496,116 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) { ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v2, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v3, v7, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1] -; GFX9-NEXT: s_cmp_eq_u64 s[2:3], 0 +; GFX9-NEXT: v_cmp_lt_u64_e64 s[0:1], s[0:1], 0 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3] -; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0 +; GFX9-NEXT: s_cmp_eq_u64 s[2:3], 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3] ; GFX9-NEXT: s_cselect_b32 s4, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0 +; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX9-NEXT: s_and_b32 s0, 1, s4 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_movk_i32 s0, 0x7f +; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX9-NEXT: s_sub_i32 s2, 64, s0 +; GFX9-NEXT: s_sub_i32 s1, s0, 64 +; GFX9-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX9-NEXT: s_cmp_lt_u32 s0, 64 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX9-NEXT: v_lshlrev_b64 v[2:3], s2, v[6:7] +; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s0, 0 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] +; GFX9-NEXT: s_and_b32 s0, 1, s3 +; GFX9-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX9-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX9-NEXT: s_and_b32 s0, 1, s4 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] -; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX9-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX9-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] -; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_and_b32 s0, 1, s3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_bfrev_b32_e32 v8, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc -; GFX9-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX9-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: saddsat_i128_vs: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, s0 -; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0 +; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], 0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo -; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[2:3], 0 +; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo ; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1] -; GFX10-NEXT: s_and_b32 s0, 1, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1 -; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0 +; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[2:3], 0 +; GFX10-NEXT: s_and_b32 s1, 1, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3] +; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0 +; GFX10-NEXT: s_movk_i32 s0, 0x7f +; GFX10-NEXT: s_sub_i32 s2, 64, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3] -; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, 0, s0 -; GFX10-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX10-NEXT: v_xor_b32_e32 v2, v1, v0 +; GFX10-NEXT: v_lshlrev_b64 v[2:3], s2, v[6:7] +; GFX10-NEXT: v_cndmask_b32_e32 v10, v1, v0, vcc_lo +; GFX10-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 +; GFX10-NEXT: s_sub_i32 s1, s0, 64 +; GFX10-NEXT: s_cmp_lt_u32 s0, 64 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: v_ashrrev_i64 v[8:9], s1, v[6:7] +; GFX10-NEXT: s_cmp_eq_u32 s0, 0 +; GFX10-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX10-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX10-NEXT: s_cselect_b32 s1, 1, 0 ; GFX10-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] -; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v2 -; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0x80000000, v3, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0 +; GFX10-NEXT: s_and_b32 s0, 1, s1 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo +; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 +; GFX10-NEXT: v_ashrrev_i32_e32 v8, 31, v7 +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 +; GFX10-NEXT: v_xor_b32_e32 v9, v11, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, v1, s0 +; GFX10-NEXT: v_and_b32_e32 v8, 1, v9 +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v8 +; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v2, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v3, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0 ; GFX10-NEXT: ; return to shader part epilog %result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs) %cast = bitcast i128 %result to <4 x float> @@ -5344,183 +5616,321 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) { ; GFX6-LABEL: v_saddsat_v2i128: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v0, v8 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v1, v9, vcc -; GFX6-NEXT: v_addc_u32_e32 v16, vcc, v2, v10, vcc -; GFX6-NEXT: v_addc_u32_e32 v17, vcc, v3, v11, vcc -; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1] -; GFX6-NEXT: s_sub_i32 s4, 0x7f, 64 +; GFX6-NEXT: v_add_i32_e32 v16, vcc, v0, v8 +; GFX6-NEXT: v_addc_u32_e32 v17, vcc, v1, v9, vcc +; GFX6-NEXT: v_addc_u32_e32 v18, vcc, v2, v10, vcc +; GFX6-NEXT: v_addc_u32_e32 v19, vcc, v3, v11, vcc +; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1] +; GFX6-NEXT: s_movk_i32 s6, 0x7f ; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[16:17], v[2:3] -; GFX6-NEXT: v_bfrev_b32_e32 v18, 1 +; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3] +; GFX6-NEXT: s_sub_i32 s7, s6, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[16:17], v[2:3] -; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v17 +; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3] +; GFX6-NEXT: s_sub_i32 s8, 64, s6 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11] +; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[8:9] +; GFX6-NEXT: s_cmp_lt_u32 s6, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11] +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] -; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc -; GFX6-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX6-NEXT: v_ashr_i64 v[0:1], v[16:17], s4 -; GFX6-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX6-NEXT: s_cmp_eq_u32 s6, 0 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX6-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[16:17], s6 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[18:19], s8 +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_and_b32 s4, 1, s4 +; GFX6-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX6-NEXT: v_ashr_i64 v[0:1], v[18:19], s7 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_and_b32 s4, 1, s5 +; GFX6-NEXT: v_ashr_i64 v[8:9], v[18:19], s6 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v19 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5] ; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX6-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v18, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v2, v16, v10, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc +; GFX6-NEXT: v_bfrev_b32_e32 v20, 1 +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v20, vcc +; GFX6-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v4, v12 ; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v5, v13, vcc ; GFX6-NEXT: v_addc_u32_e32 v10, vcc, v6, v14, vcc ; GFX6-NEXT: v_addc_u32_e32 v11, vcc, v7, v15, vcc ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GFX6-NEXT: s_cmp_lt_u32 s6, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] -; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v11 +; GFX6-NEXT: s_cmp_eq_u32 s6, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15] +; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[12:13] +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15] +; GFX6-NEXT: v_ashr_i64 v[12:13], v[10:11], s6 +; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] -; GFX6-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc -; GFX6-NEXT: v_xor_b32_e32 v6, v5, v4 -; GFX6-NEXT: v_ashr_i64 v[4:5], v[10:11], s4 -; GFX6-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX6-NEXT: s_and_b32 s5, 1, s5 +; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX6-NEXT: v_xor_b32_e32 v14, v5, v4 +; GFX6-NEXT: v_lshr_b64 v[4:5], v[8:9], s6 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[10:11], s8 +; GFX6-NEXT: s_and_b32 s6, 1, s4 +; GFX6-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX6-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX6-NEXT: v_ashr_i64 v[4:5], v[10:11], s7 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 +; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX6-NEXT: s_and_b32 s4, 1, s4 +; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v11 +; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0, v4 ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GFX6-NEXT: v_addc_u32_e32 v12, vcc, 0, v7, vcc -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v18, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc +; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v20, vcc +; GFX6-NEXT: v_and_b32_e32 v12, 1, v14 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_saddsat_v2i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_add_u32_e32 v8, vcc, v0, v8 -; GFX8-NEXT: v_addc_u32_e32 v9, vcc, v1, v9, vcc -; GFX8-NEXT: v_addc_u32_e32 v16, vcc, v2, v10, vcc -; GFX8-NEXT: v_addc_u32_e32 v17, vcc, v3, v11, vcc -; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1] -; GFX8-NEXT: s_sub_i32 s4, 0x7f, 64 +; GFX8-NEXT: v_add_u32_e32 v16, vcc, v0, v8 +; GFX8-NEXT: v_addc_u32_e32 v17, vcc, v1, v9, vcc +; GFX8-NEXT: v_addc_u32_e32 v18, vcc, v2, v10, vcc +; GFX8-NEXT: v_addc_u32_e32 v19, vcc, v3, v11, vcc +; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1] +; GFX8-NEXT: s_movk_i32 s6, 0x7f ; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[16:17], v[2:3] -; GFX8-NEXT: v_bfrev_b32_e32 v18, 1 +; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3] +; GFX8-NEXT: s_sub_i32 s7, s6, 64 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[16:17], v[2:3] -; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v17 +; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3] +; GFX8-NEXT: s_sub_i32 s8, 64, s6 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11] +; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[8:9] +; GFX8-NEXT: s_cmp_lt_u32 s6, 64 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11] +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc -; GFX8-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX8-NEXT: v_ashrrev_i64 v[0:1], s4, v[16:17] -; GFX8-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX8-NEXT: s_cmp_eq_u32 s6, 0 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX8-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s6, v[16:17] +; GFX8-NEXT: v_lshlrev_b64 v[2:3], s8, v[18:19] +; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_and_b32 s4, 1, s4 +; GFX8-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX8-NEXT: v_ashrrev_i64 v[0:1], s7, v[18:19] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_and_b32 s4, 1, s5 +; GFX8-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v19 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5] ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc -; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v18, vcc -; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v16, v10, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc +; GFX8-NEXT: v_bfrev_b32_e32 v20, 1 +; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v20, vcc +; GFX8-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v4, v12 ; GFX8-NEXT: v_addc_u32_e32 v9, vcc, v5, v13, vcc ; GFX8-NEXT: v_addc_u32_e32 v10, vcc, v6, v14, vcc ; GFX8-NEXT: v_addc_u32_e32 v11, vcc, v7, v15, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GFX8-NEXT: s_cmp_lt_u32 s6, 64 ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] -; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v11 +; GFX8-NEXT: s_cmp_eq_u32 s6, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15] +; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[12:13] +; GFX8-NEXT: s_cselect_b32 s5, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15] +; GFX8-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11] +; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] -; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc -; GFX8-NEXT: v_xor_b32_e32 v6, v5, v4 -; GFX8-NEXT: v_ashrrev_i64 v[4:5], s4, v[10:11] -; GFX8-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX8-NEXT: s_and_b32 s5, 1, s5 +; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX8-NEXT: v_xor_b32_e32 v14, v5, v4 +; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9] +; GFX8-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11] +; GFX8-NEXT: s_and_b32 s6, 1, s4 +; GFX8-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX8-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX8-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX8-NEXT: s_and_b32 s4, 1, s4 +; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v11 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0, v4 ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GFX8-NEXT: v_addc_u32_e32 v12, vcc, 0, v7, vcc -; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v18, vcc -; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc +; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v20, vcc +; GFX8-NEXT: v_and_b32_e32 v12, 1, v14 +; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_saddsat_v2i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v0, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v1, v9, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, v2, v10, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v17, vcc, v3, v11, vcc -; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1] -; GFX9-NEXT: s_sub_i32 s4, 0x7f, 64 +; GFX9-NEXT: v_add_co_u32_e32 v16, vcc, v0, v8 +; GFX9-NEXT: v_addc_co_u32_e32 v17, vcc, v1, v9, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v18, vcc, v2, v10, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v19, vcc, v3, v11, vcc +; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1] +; GFX9-NEXT: s_movk_i32 s6, 0x7f ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc -; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[16:17], v[2:3] -; GFX9-NEXT: v_bfrev_b32_e32 v18, 1 +; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3] +; GFX9-NEXT: s_sub_i32 s7, s6, 64 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[16:17], v[2:3] -; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v17 +; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3] +; GFX9-NEXT: s_sub_i32 s8, 64, s6 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11] +; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[8:9] +; GFX9-NEXT: s_cmp_lt_u32 s6, 64 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11] +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc -; GFX9-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX9-NEXT: v_ashrrev_i64 v[0:1], s4, v[16:17] -; GFX9-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX9-NEXT: s_cmp_eq_u32 s6, 0 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX9-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s6, v[16:17] +; GFX9-NEXT: v_lshlrev_b64 v[2:3], s8, v[18:19] +; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_and_b32 s4, 1, s4 +; GFX9-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX9-NEXT: v_ashrrev_i64 v[0:1], s7, v[18:19] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_and_b32 s4, 1, s5 +; GFX9-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19] +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v19 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5] ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v3, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v18, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v2, v16, v10, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc +; GFX9-NEXT: v_bfrev_b32_e32 v20, 1 +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v20, vcc +; GFX9-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v4, v12 ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v5, v13, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v6, v14, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v7, v15, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GFX9-NEXT: s_cmp_lt_u32 s6, 64 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] -; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v11 +; GFX9-NEXT: s_cmp_eq_u32 s6, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15] +; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[12:13] +; GFX9-NEXT: s_cselect_b32 s5, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15] +; GFX9-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11] +; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] -; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc -; GFX9-NEXT: v_xor_b32_e32 v6, v5, v4 -; GFX9-NEXT: v_ashrrev_i64 v[4:5], s4, v[10:11] -; GFX9-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX9-NEXT: s_and_b32 s5, 1, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX9-NEXT: v_xor_b32_e32 v14, v5, v4 +; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9] +; GFX9-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11] +; GFX9-NEXT: s_and_b32 s6, 1, s4 +; GFX9-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX9-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX9-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX9-NEXT: s_and_b32 s4, 1, s4 +; GFX9-NEXT: v_ashrrev_i32_e32 v15, 31, v11 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v7, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v18, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v20, vcc +; GFX9-NEXT: v_and_b32_e32 v12, 1, v14 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -5528,61 +5938,105 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v0, v8 -; GFX10-NEXT: s_sub_i32 s6, 0x7f, 64 -; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v9, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v16, vcc_lo, v2, v10, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, v3, v11, vcc_lo -; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[0:1] +; GFX10-NEXT: v_add_co_u32 v16, vcc_lo, v0, v8 +; GFX10-NEXT: s_movk_i32 s5, 0x7f +; GFX10-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo +; GFX10-NEXT: s_sub_i32 s6, 64, s5 +; GFX10-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo +; GFX10-NEXT: s_sub_i32 s7, s5, 64 +; GFX10-NEXT: v_add_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo +; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1] +; GFX10-NEXT: s_cmp_lt_u32 s5, 64 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[16:17], v[2:3] +; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3] ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3] +; GFX10-NEXT: v_lshlrev_b64 v[2:3], s6, v[18:19] +; GFX10-NEXT: v_cndmask_b32_e32 v20, v1, v0, vcc_lo +; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, 0, v[8:9] +; GFX10-NEXT: v_lshrrev_b64 v[0:1], s5, v[16:17] +; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11] -; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo -; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[2:3] -; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo +; GFX10-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX10-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX10-NEXT: v_ashrrev_i64 v[0:1], s5, v[18:19] +; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] -; GFX10-NEXT: v_cndmask_b32_e64 v1, v18, 0, vcc_lo -; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, v4, v12 -; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v5, v13, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, v6, v14, vcc_lo -; GFX10-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, v7, v15, vcc_lo -; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[10:11], v[4:5] -; GFX10-NEXT: v_ashrrev_i64 v[0:1], s6, v[16:17] -; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX10-NEXT: v_cmp_eq_u64_e64 s5, v[12:13], v[6:7] -; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4 -; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[12:13], v[6:7] -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc_lo +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: v_ashrrev_i64 v[8:9], s7, v[18:19] +; GFX10-NEXT: s_cmp_eq_u32 s5, 0 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_and_b32 s8, 1, vcc_lo +; GFX10-NEXT: s_and_b32 s4, 1, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 +; GFX10-NEXT: v_ashrrev_i32_e32 v8, 31, v19 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s8 +; GFX10-NEXT: v_xor_b32_e32 v9, v10, v20 +; GFX10-NEXT: s_cmp_lt_u32 s5, 64 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, v1, s4 +; GFX10-NEXT: v_and_b32_e32 v8, 1, v9 +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e32 v21, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 +; GFX10-NEXT: v_add_co_u32 v8, s4, v4, v12 +; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s4, v5, v13, s4 +; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s4, v6, v14, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e64 v11, s4, v7, v15, s4 +; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[4:5] +; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v20, vcc_lo +; GFX10-NEXT: v_lshrrev_b64 v[3:4], s5, v[8:9] ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4 +; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[10:11], v[6:7] +; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s4 +; GFX10-NEXT: v_cmp_gt_u64_e64 s4, 0, v[12:13] +; GFX10-NEXT: v_lshlrev_b64 v[12:13], s6, v[10:11] +; GFX10-NEXT: v_cndmask_b32_e64 v17, 0, 1, s4 ; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[14:15] +; GFX10-NEXT: v_or_b32_e32 v12, v3, v12 +; GFX10-NEXT: v_or_b32_e32 v13, v4, v13 +; GFX10-NEXT: v_ashrrev_i64 v[3:4], s5, v[10:11] ; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, s4 -; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v4, s5 -; GFX10-NEXT: v_cmp_eq_u64_e64 s5, 0, v[14:15] -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0x80000000, v3, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, v1, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, 0, s5 -; GFX10-NEXT: v_xor_b32_e32 v7, v4, v2 -; GFX10-NEXT: v_ashrrev_i64 v[3:4], s6, v[12:13] -; GFX10-NEXT: v_cndmask_b32_e64 v2, v16, v5, s4 -; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v13 +; GFX10-NEXT: v_cmp_eq_u64_e64 s4, v[10:11], v[6:7] +; GFX10-NEXT: v_cndmask_b32_e64 v7, v16, v5, s4 +; GFX10-NEXT: v_cmp_eq_u64_e64 s4, 0, v[14:15] +; GFX10-NEXT: v_ashrrev_i64 v[5:6], s7, v[10:11] +; GFX10-NEXT: v_cndmask_b32_e64 v14, v18, v17, s4 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s5, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v12, s4 +; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v13, s4 +; GFX10-NEXT: s_and_b32 s5, 1, s6 +; GFX10-NEXT: s_and_b32 s6, 1, s4 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s5 +; GFX10-NEXT: v_xor_b32_e32 v7, v14, v7 +; GFX10-NEXT: v_ashrrev_i32_e32 v12, 31, v11 +; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v8, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v9, s4 ; GFX10-NEXT: v_and_b32_e32 v7, 1, v7 -; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v3, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v17, v6, s4 -; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v3, v12, v3, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v12, v4, s5 +; GFX10-NEXT: v_add_co_u32 v5, s4, v5, 0 +; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s4, 0, v6, s4 ; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v7 -; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v14, vcc_lo, 0x80000000, v5, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, v8, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, v7, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, v9, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, v14, s5 +; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, 0, v3, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v21, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s4, 0x80000000, v4, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v5, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v6, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v7, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v12, s5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs) ret <2 x i128> %result @@ -5591,71 +6045,90 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) { define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) { ; GFX6-LABEL: s_saddsat_v2i128: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_add_u32 s8, s0, s8 -; GFX6-NEXT: s_cselect_b32 s16, 1, 0 -; GFX6-NEXT: s_and_b32 s16, s16, 1 -; GFX6-NEXT: s_cmp_lg_u32 s16, 0 -; GFX6-NEXT: s_addc_u32 s9, s1, s9 -; GFX6-NEXT: s_cselect_b32 s16, 1, 0 -; GFX6-NEXT: s_and_b32 s16, s16, 1 -; GFX6-NEXT: s_cmp_lg_u32 s16, 0 -; GFX6-NEXT: s_addc_u32 s16, s2, s10 +; GFX6-NEXT: s_add_u32 s16, s0, s8 ; GFX6-NEXT: s_cselect_b32 s17, 1, 0 -; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: s_and_b32 s17, s17, 1 -; GFX6-NEXT: v_mov_b32_e32 v2, s0 ; GFX6-NEXT: s_cmp_lg_u32 s17, 0 -; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3] +; GFX6-NEXT: s_addc_u32 s17, s1, s9 +; GFX6-NEXT: s_cselect_b32 s18, 1, 0 +; GFX6-NEXT: s_and_b32 s18, s18, 1 +; GFX6-NEXT: s_cmp_lg_u32 s18, 0 +; GFX6-NEXT: s_addc_u32 s18, s2, s10 +; GFX6-NEXT: s_cselect_b32 s19, 1, 0 +; GFX6-NEXT: v_mov_b32_e32 v3, s1 +; GFX6-NEXT: s_and_b32 s19, s19, 1 +; GFX6-NEXT: v_mov_b32_e32 v2, s0 +; GFX6-NEXT: s_cmp_lg_u32 s19, 0 +; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3] ; GFX6-NEXT: v_mov_b32_e32 v0, s2 -; GFX6-NEXT: s_addc_u32 s17, s3, s11 +; GFX6-NEXT: s_addc_u32 s19, s3, s11 +; GFX6-NEXT: s_movk_i32 s20, 0x7f ; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1] -; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0 +; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1] +; GFX6-NEXT: v_cmp_lt_u64_e64 s[0:1], s[8:9], 0 +; GFX6-NEXT: s_sub_i32 s21, s20, 64 +; GFX6-NEXT: s_sub_i32 s22, 64, s20 +; GFX6-NEXT: s_cmp_lt_u32 s20, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc -; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1] +; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[18:19], v[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] -; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0 -; GFX6-NEXT: s_sub_i32 s10, 0x7f, 64 -; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] -; GFX6-NEXT: s_ashr_i32 s3, s17, 31 -; GFX6-NEXT: s_ashr_i64 s[0:1], s[16:17], s10 -; GFX6-NEXT: s_add_u32 s0, s0, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 -; GFX6-NEXT: s_and_b32 s2, s2, 1 -; GFX6-NEXT: s_cmp_lg_u32 s2, 0 -; GFX6-NEXT: s_addc_u32 s1, s1, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 -; GFX6-NEXT: s_and_b32 s2, s2, 1 -; GFX6-NEXT: s_cmp_lg_u32 s2, 0 -; GFX6-NEXT: s_addc_u32 s2, s3, 0 -; GFX6-NEXT: s_cselect_b32 s18, 1, 0 -; GFX6-NEXT: s_and_b32 s18, s18, 1 -; GFX6-NEXT: s_brev_b32 s11, 1 -; GFX6-NEXT: s_cmp_lg_u32 s18, 0 +; GFX6-NEXT: s_cselect_b32 s23, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s20, 0 +; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0 +; GFX6-NEXT: s_cselect_b32 s24, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[2:3], s[16:17], s20 +; GFX6-NEXT: s_lshl_b64 s[8:9], s[18:19], s22 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX6-NEXT: s_addc_u32 s3, s3, s11 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[10:11], 0 +; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX6-NEXT: s_ashr_i32 s8, s19, 31 +; GFX6-NEXT: s_ashr_i64 s[0:1], s[18:19], s20 +; GFX6-NEXT: s_ashr_i64 s[10:11], s[18:19], s21 +; GFX6-NEXT: s_cmp_lg_u32 s23, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11] +; GFX6-NEXT: s_cmp_lg_u32 s24, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX6-NEXT: s_cmp_lg_u32 s23, 0 +; GFX6-NEXT: s_mov_b32 s9, s8 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] +; GFX6-NEXT: s_add_u32 s2, s2, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_and_b32 s8, s8, 1 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 +; GFX6-NEXT: s_addc_u32 s3, s3, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_and_b32 s8, s8, 1 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 +; GFX6-NEXT: s_addc_u32 s0, s0, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX6-NEXT: s_and_b32 s8, s8, 1 ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, s0 +; GFX6-NEXT: s_brev_b32 s23, 1 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 +; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX6-NEXT: s_addc_u32 s1, s1, s23 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX6-NEXT: v_mov_b32_e32 v0, s0 +; GFX6-NEXT: v_mov_b32_e32 v1, s2 +; GFX6-NEXT: v_mov_b32_e32 v3, s16 ; GFX6-NEXT: s_add_u32 s0, s4, s12 -; GFX6-NEXT: v_mov_b32_e32 v2, s1 +; GFX6-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc +; GFX6-NEXT: v_mov_b32_e32 v1, s1 ; GFX6-NEXT: s_cselect_b32 s1, 1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 -; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: s_addc_u32 s1, s5, s13 -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX6-NEXT: v_mov_b32_e32 v0, s2 ; GFX6-NEXT: s_cselect_b32 s2, 1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 -; GFX6-NEXT: v_mov_b32_e32 v4, s9 -; GFX6-NEXT: v_mov_b32_e32 v3, s8 -; GFX6-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc +; GFX6-NEXT: v_mov_b32_e32 v2, s3 +; GFX6-NEXT: v_mov_b32_e32 v4, s17 ; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc -; GFX6-NEXT: v_mov_b32_e32 v2, s16 -; GFX6-NEXT: v_mov_b32_e32 v1, s3 -; GFX6-NEXT: v_mov_b32_e32 v3, s17 +; GFX6-NEXT: v_mov_b32_e32 v2, s18 +; GFX6-NEXT: v_mov_b32_e32 v3, s19 ; GFX6-NEXT: s_addc_u32 s2, s6, s14 ; GFX6-NEXT: s_cselect_b32 s3, 1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc @@ -5670,41 +6143,58 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX6-NEXT: v_mov_b32_e32 v1, s7 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1] -; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0 +; GFX6-NEXT: v_cmp_lt_u64_e64 s[4:5], s[12:13], 0 +; GFX6-NEXT: s_cmp_lt_u32 s20, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] -; GFX6-NEXT: v_cmp_eq_u64_e64 s[4:5], s[14:15], 0 -; GFX6-NEXT: s_ashr_i32 s7, s3, 31 -; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] -; GFX6-NEXT: s_ashr_i64 s[4:5], s[2:3], s10 -; GFX6-NEXT: s_add_u32 s4, s4, 0 -; GFX6-NEXT: s_cselect_b32 s6, 1, 0 -; GFX6-NEXT: s_and_b32 s6, s6, 1 -; GFX6-NEXT: s_cmp_lg_u32 s6, 0 -; GFX6-NEXT: s_addc_u32 s5, s5, 0 -; GFX6-NEXT: s_cselect_b32 s6, 1, 0 -; GFX6-NEXT: s_and_b32 s6, s6, 1 -; GFX6-NEXT: s_cmp_lg_u32 s6, 0 -; GFX6-NEXT: s_addc_u32 s6, s7, 0 +; GFX6-NEXT: s_cselect_b32 s12, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s20, 0 +; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0 +; GFX6-NEXT: s_cselect_b32 s13, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[6:7], s[0:1], s20 +; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s22 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] +; GFX6-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] +; GFX6-NEXT: s_ashr_i32 s8, s3, 31 +; GFX6-NEXT: s_ashr_i64 s[4:5], s[2:3], s20 +; GFX6-NEXT: s_ashr_i64 s[10:11], s[2:3], s21 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11] +; GFX6-NEXT: s_cmp_lg_u32 s13, 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], s[0:1], s[6:7] +; GFX6-NEXT: s_mov_b32 s9, s8 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] +; GFX6-NEXT: s_add_u32 s6, s6, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_and_b32 s8, s8, 1 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 +; GFX6-NEXT: s_addc_u32 s7, s7, 0 ; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_and_b32 s8, s8, 1 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 +; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[14:15], 0 +; GFX6-NEXT: s_addc_u32 s4, s4, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX6-NEXT: s_and_b32 s8, s8, 1 ; GFX6-NEXT: s_cmp_lg_u32 s8, 0 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: v_mov_b32_e32 v3, s0 ; GFX6-NEXT: v_mov_b32_e32 v8, s1 -; GFX6-NEXT: s_addc_u32 s7, s7, s11 -; GFX6-NEXT: v_mov_b32_e32 v1, s4 +; GFX6-NEXT: s_addc_u32 s5, s5, s23 +; GFX6-NEXT: v_mov_b32_e32 v1, s6 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX6-NEXT: v_mov_b32_e32 v2, s5 +; GFX6-NEXT: v_mov_b32_e32 v2, s7 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc +; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: v_mov_b32_e32 v8, s2 -; GFX6-NEXT: v_mov_b32_e32 v2, s6 +; GFX6-NEXT: v_mov_b32_e32 v3, s5 ; GFX6-NEXT: v_mov_b32_e32 v9, s3 -; GFX6-NEXT: v_mov_b32_e32 v3, s7 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc ; GFX6-NEXT: v_readfirstlane_b32 s0, v5 @@ -5719,79 +6209,98 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; ; GFX8-LABEL: s_saddsat_v2i128: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_add_u32 s8, s0, s8 -; GFX8-NEXT: s_cselect_b32 s16, 1, 0 -; GFX8-NEXT: s_and_b32 s16, s16, 1 -; GFX8-NEXT: s_cmp_lg_u32 s16, 0 -; GFX8-NEXT: s_addc_u32 s9, s1, s9 -; GFX8-NEXT: s_cselect_b32 s16, 1, 0 -; GFX8-NEXT: s_and_b32 s16, s16, 1 -; GFX8-NEXT: s_cmp_lg_u32 s16, 0 -; GFX8-NEXT: s_addc_u32 s16, s2, s10 +; GFX8-NEXT: s_add_u32 s16, s0, s8 ; GFX8-NEXT: s_cselect_b32 s17, 1, 0 ; GFX8-NEXT: s_and_b32 s17, s17, 1 -; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: s_cmp_lg_u32 s17, 0 +; GFX8-NEXT: s_addc_u32 s17, s1, s9 +; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_and_b32 s18, s18, 1 +; GFX8-NEXT: s_cmp_lg_u32 s18, 0 +; GFX8-NEXT: s_addc_u32 s18, s2, s10 +; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_and_b32 s19, s19, 1 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: s_cmp_lg_u32 s19, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 -; GFX8-NEXT: s_addc_u32 s17, s3, s11 -; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3] +; GFX8-NEXT: s_addc_u32 s19, s3, s11 +; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3] ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 -; GFX8-NEXT: s_cmp_eq_u64 s[16:17], s[2:3] +; GFX8-NEXT: s_cmp_eq_u64 s[18:19], s[2:3] ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1] +; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 ; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: v_cmp_lt_u64_e64 s[0:1], s[8:9], 0 ; GFX8-NEXT: s_cmp_eq_u64 s[10:11], 0 -; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] -; GFX8-NEXT: s_and_b32 s0, 1, s2 -; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 -; GFX8-NEXT: s_sub_i32 s10, 0x7f, 64 -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] -; GFX8-NEXT: s_ashr_i32 s3, s17, 31 -; GFX8-NEXT: s_ashr_i64 s[0:1], s[16:17], s10 -; GFX8-NEXT: s_add_u32 s0, s0, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 -; GFX8-NEXT: s_and_b32 s2, s2, 1 -; GFX8-NEXT: s_cmp_lg_u32 s2, 0 -; GFX8-NEXT: s_addc_u32 s1, s1, 0 +; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0 ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 -; GFX8-NEXT: s_and_b32 s2, s2, 1 -; GFX8-NEXT: s_cmp_lg_u32 s2, 0 -; GFX8-NEXT: s_addc_u32 s2, s3, 0 -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 -; GFX8-NEXT: s_and_b32 s18, s18, 1 -; GFX8-NEXT: s_brev_b32 s11, 1 -; GFX8-NEXT: s_cmp_lg_u32 s18, 0 +; GFX8-NEXT: s_movk_i32 s20, 0x7f ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: s_addc_u32 s3, s3, s11 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX8-NEXT: s_and_b32 s0, 1, s2 +; GFX8-NEXT: s_sub_i32 s21, s20, 64 +; GFX8-NEXT: s_sub_i32 s22, 64, s20 +; GFX8-NEXT: s_cmp_lt_u32 s20, 64 +; GFX8-NEXT: s_cselect_b32 s23, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s20, 0 +; GFX8-NEXT: s_cselect_b32 s24, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[2:3], s[16:17], s20 +; GFX8-NEXT: s_lshl_b64 s[8:9], s[18:19], s22 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX8-NEXT: s_ashr_i32 s8, s19, 31 +; GFX8-NEXT: s_ashr_i64 s[0:1], s[18:19], s20 +; GFX8-NEXT: s_ashr_i64 s[10:11], s[18:19], s21 +; GFX8-NEXT: s_cmp_lg_u32 s23, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11] +; GFX8-NEXT: s_cmp_lg_u32 s24, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX8-NEXT: s_cmp_lg_u32 s23, 0 +; GFX8-NEXT: s_mov_b32 s9, s8 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] +; GFX8-NEXT: s_add_u32 s2, s2, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_and_b32 s8, s8, 1 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 +; GFX8-NEXT: s_addc_u32 s3, s3, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_and_b32 s8, s8, 1 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 +; GFX8-NEXT: s_addc_u32 s0, s0, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX8-NEXT: s_and_b32 s8, s8, 1 ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, s0 +; GFX8-NEXT: s_brev_b32 s23, 1 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX8-NEXT: s_addc_u32 s1, s1, s23 +; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s2 +; GFX8-NEXT: v_mov_b32_e32 v3, s16 ; GFX8-NEXT: s_add_u32 s0, s4, s12 -; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: s_addc_u32 s1, s5, s13 -; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 -; GFX8-NEXT: v_mov_b32_e32 v4, s9 -; GFX8-NEXT: v_mov_b32_e32 v3, s8 +; GFX8-NEXT: v_mov_b32_e32 v2, s3 +; GFX8-NEXT: v_mov_b32_e32 v4, s17 ; GFX8-NEXT: s_addc_u32 s2, s6, s14 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc -; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: s_cselect_b32 s3, 1, 0 -; GFX8-NEXT: v_mov_b32_e32 v2, s16 -; GFX8-NEXT: v_mov_b32_e32 v3, s17 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc +; GFX8-NEXT: v_mov_b32_e32 v2, s18 +; GFX8-NEXT: v_mov_b32_e32 v3, s19 ; GFX8-NEXT: s_and_b32 s3, s3, 1 ; GFX8-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc @@ -5809,42 +6318,59 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX8-NEXT: s_and_b32 s4, 1, s6 ; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_cmp_lt_u64_e64 s[4:5], s[12:13], 0 ; GFX8-NEXT: s_cmp_eq_u64 s[14:15], 0 -; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] -; GFX8-NEXT: s_and_b32 s4, 1, s6 -; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] -; GFX8-NEXT: s_ashr_i32 s7, s3, 31 -; GFX8-NEXT: s_ashr_i64 s[4:5], s[2:3], s10 -; GFX8-NEXT: s_add_u32 s4, s4, 0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 -; GFX8-NEXT: s_and_b32 s6, s6, 1 -; GFX8-NEXT: s_cmp_lg_u32 s6, 0 -; GFX8-NEXT: s_addc_u32 s5, s5, 0 +; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0 ; GFX8-NEXT: s_cselect_b32 s6, 1, 0 -; GFX8-NEXT: s_and_b32 s6, s6, 1 -; GFX8-NEXT: s_cmp_lg_u32 s6, 0 -; GFX8-NEXT: s_addc_u32 s6, s7, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] +; GFX8-NEXT: s_and_b32 s4, 1, s6 +; GFX8-NEXT: s_cmp_lt_u32 s20, 64 +; GFX8-NEXT: s_cselect_b32 s12, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s20, 0 +; GFX8-NEXT: s_cselect_b32 s13, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[6:7], s[0:1], s20 +; GFX8-NEXT: s_lshl_b64 s[8:9], s[2:3], s22 +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] +; GFX8-NEXT: s_ashr_i32 s8, s3, 31 +; GFX8-NEXT: s_ashr_i64 s[4:5], s[2:3], s20 +; GFX8-NEXT: s_ashr_i64 s[10:11], s[2:3], s21 +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11] +; GFX8-NEXT: s_cmp_lg_u32 s13, 0 +; GFX8-NEXT: s_cselect_b64 s[6:7], s[0:1], s[6:7] +; GFX8-NEXT: s_mov_b32 s9, s8 +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] +; GFX8-NEXT: s_add_u32 s6, s6, 0 ; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_and_b32 s8, s8, 1 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 +; GFX8-NEXT: s_addc_u32 s7, s7, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_and_b32 s8, s8, 1 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 +; GFX8-NEXT: s_addc_u32 s4, s4, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_and_b32 s8, s8, 1 ; GFX8-NEXT: s_cmp_lg_u32 s8, 0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_mov_b32_e32 v3, s0 ; GFX8-NEXT: v_mov_b32_e32 v8, s1 -; GFX8-NEXT: s_addc_u32 s7, s7, s11 -; GFX8-NEXT: v_mov_b32_e32 v1, s4 +; GFX8-NEXT: s_addc_u32 s5, s5, s23 +; GFX8-NEXT: v_mov_b32_e32 v1, s6 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX8-NEXT: v_mov_b32_e32 v2, s5 +; GFX8-NEXT: v_mov_b32_e32 v2, s7 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc +; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: v_mov_b32_e32 v8, s2 -; GFX8-NEXT: v_mov_b32_e32 v2, s6 +; GFX8-NEXT: v_mov_b32_e32 v3, s5 ; GFX8-NEXT: v_mov_b32_e32 v9, s3 -; GFX8-NEXT: v_mov_b32_e32 v3, s7 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc ; GFX8-NEXT: v_readfirstlane_b32 s0, v5 @@ -5859,79 +6385,98 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; ; GFX9-LABEL: s_saddsat_v2i128: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_add_u32 s8, s0, s8 -; GFX9-NEXT: s_cselect_b32 s16, 1, 0 -; GFX9-NEXT: s_and_b32 s16, s16, 1 -; GFX9-NEXT: s_cmp_lg_u32 s16, 0 -; GFX9-NEXT: s_addc_u32 s9, s1, s9 -; GFX9-NEXT: s_cselect_b32 s16, 1, 0 -; GFX9-NEXT: s_and_b32 s16, s16, 1 -; GFX9-NEXT: s_cmp_lg_u32 s16, 0 -; GFX9-NEXT: s_addc_u32 s16, s2, s10 +; GFX9-NEXT: s_add_u32 s16, s0, s8 ; GFX9-NEXT: s_cselect_b32 s17, 1, 0 ; GFX9-NEXT: s_and_b32 s17, s17, 1 -; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: s_cmp_lg_u32 s17, 0 +; GFX9-NEXT: s_addc_u32 s17, s1, s9 +; GFX9-NEXT: s_cselect_b32 s18, 1, 0 +; GFX9-NEXT: s_and_b32 s18, s18, 1 +; GFX9-NEXT: s_cmp_lg_u32 s18, 0 +; GFX9-NEXT: s_addc_u32 s18, s2, s10 +; GFX9-NEXT: s_cselect_b32 s19, 1, 0 +; GFX9-NEXT: s_and_b32 s19, s19, 1 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: s_cmp_lg_u32 s19, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, s0 -; GFX9-NEXT: s_addc_u32 s17, s3, s11 -; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3] +; GFX9-NEXT: s_addc_u32 s19, s3, s11 +; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3] ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: s_cmp_eq_u64 s[16:17], s[2:3] +; GFX9-NEXT: s_cmp_eq_u64 s[18:19], s[2:3] ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1] +; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: v_cmp_lt_u64_e64 s[0:1], s[8:9], 0 ; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0 -; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] -; GFX9-NEXT: s_and_b32 s0, 1, s2 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 -; GFX9-NEXT: s_sub_i32 s10, 0x7f, 64 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] -; GFX9-NEXT: s_ashr_i32 s3, s17, 31 -; GFX9-NEXT: s_ashr_i64 s[0:1], s[16:17], s10 -; GFX9-NEXT: s_add_u32 s0, s0, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 -; GFX9-NEXT: s_and_b32 s2, s2, 1 -; GFX9-NEXT: s_cmp_lg_u32 s2, 0 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0 ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 -; GFX9-NEXT: s_and_b32 s2, s2, 1 -; GFX9-NEXT: s_cmp_lg_u32 s2, 0 -; GFX9-NEXT: s_addc_u32 s2, s3, 0 -; GFX9-NEXT: s_cselect_b32 s18, 1, 0 -; GFX9-NEXT: s_and_b32 s18, s18, 1 -; GFX9-NEXT: s_brev_b32 s11, 1 -; GFX9-NEXT: s_cmp_lg_u32 s18, 0 +; GFX9-NEXT: s_movk_i32 s20, 0x7f ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: s_addc_u32 s3, s3, s11 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX9-NEXT: s_and_b32 s0, 1, s2 +; GFX9-NEXT: s_sub_i32 s21, s20, 64 +; GFX9-NEXT: s_sub_i32 s22, 64, s20 +; GFX9-NEXT: s_cmp_lt_u32 s20, 64 +; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s20, 0 +; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[2:3], s[16:17], s20 +; GFX9-NEXT: s_lshl_b64 s[8:9], s[18:19], s22 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX9-NEXT: s_ashr_i32 s8, s19, 31 +; GFX9-NEXT: s_ashr_i64 s[0:1], s[18:19], s20 +; GFX9-NEXT: s_ashr_i64 s[10:11], s[18:19], s21 +; GFX9-NEXT: s_cmp_lg_u32 s23, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11] +; GFX9-NEXT: s_cmp_lg_u32 s24, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX9-NEXT: s_cmp_lg_u32 s23, 0 +; GFX9-NEXT: s_mov_b32 s9, s8 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] +; GFX9-NEXT: s_add_u32 s2, s2, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_and_b32 s8, s8, 1 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 +; GFX9-NEXT: s_addc_u32 s3, s3, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_and_b32 s8, s8, 1 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 +; GFX9-NEXT: s_addc_u32 s0, s0, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: s_brev_b32 s23, 1 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX9-NEXT: s_addc_u32 s1, s1, s23 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s2 +; GFX9-NEXT: v_mov_b32_e32 v3, s16 ; GFX9-NEXT: s_add_u32 s0, s4, s12 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: s_cselect_b32 s1, 1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: s_addc_u32 s1, s5, s13 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 -; GFX9-NEXT: v_mov_b32_e32 v4, s9 -; GFX9-NEXT: v_mov_b32_e32 v3, s8 +; GFX9-NEXT: v_mov_b32_e32 v2, s3 +; GFX9-NEXT: v_mov_b32_e32 v4, s17 ; GFX9-NEXT: s_addc_u32 s2, s6, s14 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc -; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: s_cselect_b32 s3, 1, 0 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc +; GFX9-NEXT: v_mov_b32_e32 v2, s18 +; GFX9-NEXT: v_mov_b32_e32 v3, s19 ; GFX9-NEXT: s_and_b32 s3, s3, 1 ; GFX9-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc @@ -5949,42 +6494,59 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX9-NEXT: s_and_b32 s4, 1, s6 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_cmp_lt_u64_e64 s[4:5], s[12:13], 0 ; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0 -; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0 -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] -; GFX9-NEXT: s_and_b32 s4, 1, s6 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] -; GFX9-NEXT: s_ashr_i32 s7, s3, 31 -; GFX9-NEXT: s_ashr_i64 s[4:5], s[2:3], s10 -; GFX9-NEXT: s_add_u32 s4, s4, 0 -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 -; GFX9-NEXT: s_and_b32 s6, s6, 1 -; GFX9-NEXT: s_cmp_lg_u32 s6, 0 -; GFX9-NEXT: s_addc_u32 s5, s5, 0 +; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0 ; GFX9-NEXT: s_cselect_b32 s6, 1, 0 -; GFX9-NEXT: s_and_b32 s6, s6, 1 -; GFX9-NEXT: s_cmp_lg_u32 s6, 0 -; GFX9-NEXT: s_addc_u32 s6, s7, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] +; GFX9-NEXT: s_and_b32 s4, 1, s6 +; GFX9-NEXT: s_cmp_lt_u32 s20, 64 +; GFX9-NEXT: s_cselect_b32 s12, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s20, 0 +; GFX9-NEXT: s_cselect_b32 s13, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[6:7], s[0:1], s20 +; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s22 +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] +; GFX9-NEXT: s_ashr_i32 s8, s3, 31 +; GFX9-NEXT: s_ashr_i64 s[4:5], s[2:3], s20 +; GFX9-NEXT: s_ashr_i64 s[10:11], s[2:3], s21 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11] +; GFX9-NEXT: s_cmp_lg_u32 s13, 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], s[0:1], s[6:7] +; GFX9-NEXT: s_mov_b32 s9, s8 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] +; GFX9-NEXT: s_add_u32 s6, s6, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_and_b32 s8, s8, 1 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 +; GFX9-NEXT: s_addc_u32 s7, s7, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_and_b32 s8, s8, 1 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 +; GFX9-NEXT: s_addc_u32 s4, s4, 0 ; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s8, 0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_mov_b32_e32 v3, s0 ; GFX9-NEXT: v_mov_b32_e32 v8, s1 -; GFX9-NEXT: s_addc_u32 s7, s7, s11 -; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: s_addc_u32 s5, s5, s23 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s7 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc +; GFX9-NEXT: v_mov_b32_e32 v2, s4 ; GFX9-NEXT: v_mov_b32_e32 v8, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s5 ; GFX9-NEXT: v_mov_b32_e32 v9, s3 -; GFX9-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc ; GFX9-NEXT: v_readfirstlane_b32 s0, v5 @@ -5999,122 +6561,158 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; ; GFX10-LABEL: s_saddsat_v2i128: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_add_u32 s8, s0, s8 -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 -; GFX10-NEXT: s_and_b32 s16, s16, 1 -; GFX10-NEXT: s_cmp_lg_u32 s16, 0 -; GFX10-NEXT: s_addc_u32 s9, s1, s9 -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 -; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1] -; GFX10-NEXT: s_and_b32 s16, s16, 1 -; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[10:11], 0 -; GFX10-NEXT: s_cmp_lg_u32 s16, 0 -; GFX10-NEXT: v_mov_b32_e32 v2, s9 -; GFX10-NEXT: s_addc_u32 s16, s2, s10 +; GFX10-NEXT: s_add_u32 s16, s0, s8 ; GFX10-NEXT: s_cselect_b32 s17, 1, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: s_and_b32 s17, s17, 1 ; GFX10-NEXT: s_cmp_lg_u32 s17, 0 -; GFX10-NEXT: s_addc_u32 s17, s3, s11 -; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[16:17], s[2:3] -; GFX10-NEXT: s_cmp_eq_u64 s[16:17], s[2:3] -; GFX10-NEXT: v_mov_b32_e32 v3, s17 +; GFX10-NEXT: s_addc_u32 s17, s1, s9 ; GFX10-NEXT: s_cselect_b32 s18, 1, 0 +; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1] +; GFX10-NEXT: s_and_b32 s18, s18, 1 +; GFX10-NEXT: s_cmp_lg_u32 s18, 0 +; GFX10-NEXT: s_addc_u32 s18, s2, s10 +; GFX10-NEXT: s_cselect_b32 s19, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX10-NEXT: s_and_b32 s19, s19, 1 +; GFX10-NEXT: s_cmp_lg_u32 s19, 0 +; GFX10-NEXT: s_addc_u32 s19, s3, s11 +; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3] +; GFX10-NEXT: s_cmp_eq_u64 s[18:19], s[2:3] +; GFX10-NEXT: v_cmp_lt_u64_e64 s2, s[8:9], 0 +; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 -; GFX10-NEXT: s_and_b32 s0, 1, s18 +; GFX10-NEXT: s_and_b32 s0, 1, s20 ; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0 +; GFX10-NEXT: s_movk_i32 s20, 0x7f +; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2 +; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[10:11], 0 +; GFX10-NEXT: s_and_b32 s1, 1, s1 +; GFX10-NEXT: s_sub_i32 s21, s20, 64 +; GFX10-NEXT: s_sub_i32 s22, 64, s20 +; GFX10-NEXT: s_cmp_lt_u32 s20, 64 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 -; GFX10-NEXT: s_sub_i32 s10, 0x7f, 64 -; GFX10-NEXT: s_and_b32 s0, 1, s0 -; GFX10-NEXT: s_ashr_i32 s3, s17, 31 +; GFX10-NEXT: s_cselect_b32 s23, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s20, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2 +; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[2:3], s[16:17], s20 +; GFX10-NEXT: s_lshl_b64 s[8:9], s[18:19], s22 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 -; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 -; GFX10-NEXT: s_brev_b32 s11, 1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0 -; GFX10-NEXT: s_ashr_i64 s[0:1], s[16:17], s10 -; GFX10-NEXT: s_add_u32 s0, s0, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 +; GFX10-NEXT: s_ashr_i32 s10, s19, 31 +; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX10-NEXT: s_ashr_i64 s[0:1], s[18:19], s20 +; GFX10-NEXT: s_ashr_i64 s[8:9], s[18:19], s21 +; GFX10-NEXT: s_cmp_lg_u32 s23, 0 +; GFX10-NEXT: s_mov_b32 s11, s10 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[8:9] +; GFX10-NEXT: s_cmp_lg_u32 s24, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo +; GFX10-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX10-NEXT: s_cmp_lg_u32 s23, 0 +; GFX10-NEXT: v_mov_b32_e32 v2, s17 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11] +; GFX10-NEXT: s_add_u32 s2, s2, 0 +; GFX10-NEXT: s_cselect_b32 s8, 1, 0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX10-NEXT: s_and_b32 s2, s2, 1 -; GFX10-NEXT: v_mov_b32_e32 v1, s8 -; GFX10-NEXT: s_cmp_lg_u32 s2, 0 -; GFX10-NEXT: s_addc_u32 s1, s1, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_and_b32 s8, s8, 1 +; GFX10-NEXT: v_mov_b32_e32 v1, s16 +; GFX10-NEXT: s_cmp_lg_u32 s8, 0 +; GFX10-NEXT: s_brev_b32 s23, 1 +; GFX10-NEXT: s_addc_u32 s3, s3, 0 +; GFX10-NEXT: s_cselect_b32 s8, 1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_and_b32 s2, s2, 1 -; GFX10-NEXT: s_cmp_lg_u32 s2, 0 -; GFX10-NEXT: s_addc_u32 s2, s3, 0 -; GFX10-NEXT: s_cselect_b32 s18, 1, 0 -; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX10-NEXT: s_and_b32 s18, s18, 1 -; GFX10-NEXT: s_cmp_lg_u32 s18, 0 -; GFX10-NEXT: s_addc_u32 s3, s3, s11 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo -; GFX10-NEXT: s_add_u32 s0, s4, s12 +; GFX10-NEXT: s_and_b32 s8, s8, 1 +; GFX10-NEXT: v_mov_b32_e32 v3, s19 +; GFX10-NEXT: s_cmp_lg_u32 s8, 0 +; GFX10-NEXT: s_addc_u32 s0, s0, 0 ; GFX10-NEXT: s_cselect_b32 s8, 1, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s1, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: s_and_b32 s8, s8, 1 -; GFX10-NEXT: v_mov_b32_e32 v2, s16 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo -; GFX10-NEXT: s_addc_u32 s1, s5, s13 +; GFX10-NEXT: s_addc_u32 s1, s1, s23 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s2, vcc_lo +; GFX10-NEXT: s_add_u32 s2, s4, s12 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s3, vcc_lo +; GFX10-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s1, vcc_lo +; GFX10-NEXT: s_and_b32 s3, s3, 1 +; GFX10-NEXT: v_mov_b32_e32 v2, s18 +; GFX10-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10-NEXT: s_addc_u32 s3, s5, s13 ; GFX10-NEXT: s_cselect_b32 s8, 1, 0 -; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5] +; GFX10-NEXT: v_cmp_lt_u64_e64 s1, s[2:3], s[4:5] ; GFX10-NEXT: s_and_b32 s8, s8, 1 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s0, vcc_lo ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 -; GFX10-NEXT: v_cmp_lt_i64_e64 s3, s[14:15], 0 ; GFX10-NEXT: s_addc_u32 s8, s6, s14 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1 ; GFX10-NEXT: s_and_b32 s9, s9, 1 -; GFX10-NEXT: v_mov_b32_e32 v6, s1 -; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: v_mov_b32_e32 v7, s8 +; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: s_addc_u32 s9, s7, s15 ; GFX10-NEXT: s_cmp_eq_u64 s[8:9], s[6:7] -; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[8:9], s[6:7] -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[8:9], s[6:7] +; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, s9 -; GFX10-NEXT: s_and_b32 s2, 1, s2 +; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0 -; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 -; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 -; GFX10-NEXT: s_ashr_i32 s5, s9, 31 -; GFX10-NEXT: s_and_b32 s4, 1, s2 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 +; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[12:13], 0 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s1 +; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_and_b32 s16, 1, s1 +; GFX10-NEXT: s_cmp_lt_u32 s20, 64 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s3 -; GFX10-NEXT: s_ashr_i64 s[2:3], s[8:9], s10 -; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4 -; GFX10-NEXT: s_add_u32 s2, s2, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 +; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[14:15], 0 +; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s20, 0 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s16 +; GFX10-NEXT: s_cselect_b32 s12, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[4:5], s[2:3], s20 +; GFX10-NEXT: s_lshl_b64 s[6:7], s[8:9], s22 +; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 +; GFX10-NEXT: s_ashr_i32 s10, s9, 31 +; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; GFX10-NEXT: s_ashr_i64 s[0:1], s[8:9], s20 +; GFX10-NEXT: s_ashr_i64 s[6:7], s[8:9], s21 +; GFX10-NEXT: s_cmp_lg_u32 s17, 0 +; GFX10-NEXT: s_mov_b32 s11, s10 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX10-NEXT: s_cmp_lg_u32 s12, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo +; GFX10-NEXT: s_cselect_b64 s[4:5], s[2:3], s[4:5] +; GFX10-NEXT: s_cmp_lg_u32 s17, 0 +; GFX10-NEXT: v_mov_b32_e32 v6, s3 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11] +; GFX10-NEXT: s_add_u32 s4, s4, 0 ; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4 ; GFX10-NEXT: s_and_b32 s6, s6, 1 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0, s4 +; GFX10-NEXT: v_mov_b32_e32 v5, s2 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0 -; GFX10-NEXT: s_addc_u32 s3, s3, 0 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 -; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4 -; GFX10-NEXT: s_and_b32 s4, s4, 1 -; GFX10-NEXT: v_mov_b32_e32 v5, s0 -; GFX10-NEXT: s_cmp_lg_u32 s4, 0 -; GFX10-NEXT: v_readfirstlane_b32 s0, v0 -; GFX10-NEXT: v_and_b32_e32 v4, 1, v4 -; GFX10-NEXT: s_addc_u32 s4, s5, 0 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: s_addc_u32 s5, s5, 0 ; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: v_and_b32_e32 v4, 1, v4 ; GFX10-NEXT: s_and_b32 s6, s6, 1 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-NEXT: s_cmp_lg_u32 s6, 0 +; GFX10-NEXT: s_addc_u32 s0, s0, 0 +; GFX10-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: s_and_b32 s6, s6, 1 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0 -; GFX10-NEXT: s_addc_u32 s1, s5, s11 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s2, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, s3, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s4, vcc_lo +; GFX10-NEXT: s_addc_u32 s1, s1, s23 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, s5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v8, s1, vcc_lo +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1 -; GFX10-NEXT: v_readfirstlane_b32 s2, v2 -; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_readfirstlane_b32 s6, v6 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll index db0329c..fe15a5f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll @@ -1073,7 +1073,6 @@ define i64 @v_sdiv_i64_pow2k_denom(i64 %num) { ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3 -; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4 ; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2 @@ -1165,20 +1164,21 @@ define i64 @v_sdiv_i64_pow2k_denom(i64 %num) { ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 ; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v5, vcc ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v5 +; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v6 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6 -; CHECK-NEXT: v_mov_b32_e32 v7, s7 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v2 -; CHECK-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5] +; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5] ; CHECK-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc +; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 -; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; CHECK-NEXT: v_mov_b32_e32 v8, s4 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc ; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v6 @@ -1524,14 +1524,14 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7 -; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000 +; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 -; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 +; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 @@ -1562,7 +1562,7 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v14, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v9, v7, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v10, v13 -; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 +; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 @@ -1587,7 +1587,7 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 -; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 +; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 @@ -1609,26 +1609,26 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v10, s7, v8 ; CGP-NEXT: v_mul_hi_u32 v12, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s7, v7 -; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v11 ; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v1, v9, vcc ; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v9 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v10 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0 ; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10 -; CGP-NEXT: v_mov_b32_e32 v11, s8 ; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v7 -; CGP-NEXT: v_cndmask_b32_e64 v9, v11, v9, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[4:5] ; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v0 -; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; CGP-NEXT: v_mov_b32_e32 v12, s4 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc ; CGP-NEXT: v_add_i32_e32 v1, vcc, 1, v10 @@ -1737,26 +1737,26 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v8, s7, v5 ; CGP-NEXT: v_mul_hi_u32 v10, s7, v4 ; CGP-NEXT: v_mul_lo_u32 v9, s7, v4 -; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v9 ; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v7, vcc ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v7 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2 ; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s7, v2 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 -; CGP-NEXT: v_mov_b32_e32 v9, s6 ; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4 -; CGP-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5] ; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v2 -; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; CGP-NEXT: v_mov_b32_e32 v10, s4 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc ; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v8 @@ -1796,7 +1796,6 @@ define i64 @v_sdiv_i64_oddk_denom(i64 %num) { ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3 -; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4 ; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2 @@ -1888,20 +1887,21 @@ define i64 @v_sdiv_i64_oddk_denom(i64 %num) { ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 ; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v5, vcc ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v5 +; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v6 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6 -; CHECK-NEXT: v_mov_b32_e32 v7, s7 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v2 -; CHECK-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5] +; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5] ; CHECK-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc +; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 -; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; CHECK-NEXT: v_mov_b32_e32 v8, s4 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc ; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v6 @@ -2247,14 +2247,14 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7 -; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000 +; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 -; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 +; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 @@ -2285,7 +2285,7 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v14, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v9, v7, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v10, v13 -; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 +; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 @@ -2310,7 +2310,7 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 -; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 +; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 @@ -2332,26 +2332,26 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v10, s7, v8 ; CGP-NEXT: v_mul_hi_u32 v12, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s7, v7 -; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v11 ; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v1, v9, vcc ; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v9 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v10 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0 ; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10 -; CGP-NEXT: v_mov_b32_e32 v11, s8 ; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v7 -; CGP-NEXT: v_cndmask_b32_e64 v9, v11, v9, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[4:5] ; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v0 -; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; CGP-NEXT: v_mov_b32_e32 v12, s4 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc ; CGP-NEXT: v_add_i32_e32 v1, vcc, 1, v10 @@ -2460,26 +2460,26 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v8, s7, v5 ; CGP-NEXT: v_mul_hi_u32 v10, s7, v4 ; CGP-NEXT: v_mul_lo_u32 v9, s7, v4 -; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v9 ; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v7, vcc ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v7 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2 ; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s7, v2 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 -; CGP-NEXT: v_mov_b32_e32 v9, s6 ; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4 -; CGP-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5] ; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v2 -; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; CGP-NEXT: v_mov_b32_e32 v10, s4 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc ; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v8 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll index 840653d..152c5bc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll @@ -1053,7 +1053,6 @@ define i64 @v_srem_i64_pow2k_denom(i64 %num) { ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3 -; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4 ; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2 @@ -1141,24 +1140,25 @@ define i64 @v_srem_i64_pow2k_denom(i64 %num) { ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, s6, v2 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; CHECK-NEXT: v_mov_b32_e32 v5, s7 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 ; CHECK-NEXT: v_subb_u32_e64 v4, s[4:5], v1, v2, vcc ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2 -; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 +; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v4 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5] +; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5] +; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5] ; CHECK-NEXT: v_subrev_i32_e32 v5, vcc, s6, v0 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v5 +; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; CHECK-NEXT: v_mov_b32_e32 v7, s4 +; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CHECK-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc ; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s6, v5 ; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 @@ -1500,14 +1500,14 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7 -; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000 +; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 -; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 +; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 @@ -1538,7 +1538,7 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v14, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v9, v7, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v10, v13 -; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 +; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 @@ -1563,7 +1563,7 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 -; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 +; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 @@ -1585,26 +1585,26 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v8, s7, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s7, v7 ; CGP-NEXT: v_mul_hi_u32 v7, s7, v7 -; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; CGP-NEXT: v_mov_b32_e32 v9, s8 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v10 ; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc ; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7 -; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CGP-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5] ; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v0 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v9 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc -; CGP-NEXT: v_mov_b32_e32 v11, s4 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v9 +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc +; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc ; CGP-NEXT: v_subrev_i32_e32 v11, vcc, s7, v9 ; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v1, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 @@ -1711,26 +1711,26 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v5, s7, v5 ; CGP-NEXT: v_mul_lo_u32 v8, s7, v4 ; CGP-NEXT: v_mul_hi_u32 v4, s7, v4 -; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; CGP-NEXT: v_mov_b32_e32 v7, s6 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8 ; CGP-NEXT: v_subb_u32_e64 v5, s[4:5], v3, v4, vcc ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4 -; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2 +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5] ; CGP-NEXT: v_subrev_i32_e32 v7, vcc, s7, v2 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v7 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; CGP-NEXT: v_mov_b32_e32 v9, s4 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v7 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; CGP-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc +; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc ; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v7 ; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 @@ -1768,7 +1768,6 @@ define i64 @v_srem_i64_oddk_denom(i64 %num) { ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3 -; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4 ; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2 @@ -1856,24 +1855,25 @@ define i64 @v_srem_i64_oddk_denom(i64 %num) { ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, s6, v2 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; CHECK-NEXT: v_mov_b32_e32 v5, s7 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 ; CHECK-NEXT: v_subb_u32_e64 v4, s[4:5], v1, v2, vcc ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2 -; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 +; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v4 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5] +; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5] +; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5] ; CHECK-NEXT: v_subrev_i32_e32 v5, vcc, s6, v0 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v5 +; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; CHECK-NEXT: v_mov_b32_e32 v7, s4 +; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CHECK-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc ; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s6, v5 ; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 @@ -2215,14 +2215,14 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7 -; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000 +; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 -; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 +; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 @@ -2253,7 +2253,7 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v14, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v9, v7, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v10, v13 -; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 +; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 @@ -2278,7 +2278,7 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 -; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 +; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 @@ -2300,26 +2300,26 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v8, s7, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s7, v7 ; CGP-NEXT: v_mul_hi_u32 v7, s7, v7 -; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; CGP-NEXT: v_mov_b32_e32 v9, s8 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v10 ; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc ; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7 -; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CGP-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5] ; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v0 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v9 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc -; CGP-NEXT: v_mov_b32_e32 v11, s4 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v9 +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc +; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc ; CGP-NEXT: v_subrev_i32_e32 v11, vcc, s7, v9 ; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v1, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 @@ -2426,26 +2426,26 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_mul_lo_u32 v5, s7, v5 ; CGP-NEXT: v_mul_lo_u32 v8, s7, v4 ; CGP-NEXT: v_mul_hi_u32 v4, s7, v4 -; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; CGP-NEXT: v_mov_b32_e32 v7, s6 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8 ; CGP-NEXT: v_subb_u32_e64 v5, s[4:5], v3, v4, vcc ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4 -; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2 +; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5] ; CGP-NEXT: v_subrev_i32_e32 v7, vcc, s7, v2 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v7 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; CGP-NEXT: v_mov_b32_e32 v9, s4 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v7 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; CGP-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc +; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc ; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v7 ; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll index 26ed8af..34d01f4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll @@ -4775,40 +4775,57 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) { ; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 0 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1] +; GFX6-NEXT: s_movk_i32 s2, 0x7f +; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0 -; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] -; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX6-NEXT: s_ashr_i32 s3, s11, 31 -; GFX6-NEXT: s_ashr_i64 s[0:1], s[10:11], s0 -; GFX6-NEXT: s_add_u32 s0, s0, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 -; GFX6-NEXT: s_and_b32 s2, s2, 1 -; GFX6-NEXT: s_cmp_lg_u32 s2, 0 -; GFX6-NEXT: s_addc_u32 s1, s1, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 -; GFX6-NEXT: s_and_b32 s2, s2, 1 -; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[6:7], 0 -; GFX6-NEXT: s_addc_u32 s2, s3, 0 +; GFX6-NEXT: s_sub_i32 s6, s2, 64 +; GFX6-NEXT: s_sub_i32 s4, 64, s2 +; GFX6-NEXT: s_cmp_lt_u32 s2, 64 +; GFX6-NEXT: s_cselect_b32 s12, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s2, 0 +; GFX6-NEXT: s_cselect_b32 s13, 1, 0 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX6-NEXT: s_ashr_i64 s[0:1], s[10:11], s2 +; GFX6-NEXT: s_lshr_b64 s[2:3], s[8:9], s2 +; GFX6-NEXT: s_lshl_b64 s[4:5], s[10:11], s4 +; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] +; GFX6-NEXT: s_ashr_i32 s4, s11, 31 +; GFX6-NEXT: s_ashr_i64 s[6:7], s[10:11], s6 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX6-NEXT: s_cmp_lg_u32 s13, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX6-NEXT: s_mov_b32 s5, s4 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] +; GFX6-NEXT: s_add_u32 s2, s2, 0 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: s_and_b32 s4, s4, 1 +; GFX6-NEXT: s_cmp_lg_u32 s4, 0 +; GFX6-NEXT: s_addc_u32 s3, s3, 0 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: s_and_b32 s4, s4, 1 +; GFX6-NEXT: s_cmp_lg_u32 s4, 0 +; GFX6-NEXT: s_addc_u32 s0, s0, 0 ; GFX6-NEXT: s_cselect_b32 s4, 1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX6-NEXT: s_and_b32 s4, s4, 1 ; GFX6-NEXT: s_cmp_lg_u32 s4, 0 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX6-NEXT: s_addc_u32 s3, s3, 0x80000000 -; GFX6-NEXT: v_mov_b32_e32 v1, s0 -; GFX6-NEXT: v_mov_b32_e32 v2, s1 +; GFX6-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX6-NEXT: v_mov_b32_e32 v1, s2 +; GFX6-NEXT: v_mov_b32_e32 v2, s3 ; GFX6-NEXT: v_mov_b32_e32 v3, s8 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX6-NEXT: v_mov_b32_e32 v4, s9 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc -; GFX6-NEXT: v_mov_b32_e32 v2, s2 +; GFX6-NEXT: v_mov_b32_e32 v2, s0 +; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: v_mov_b32_e32 v4, s10 -; GFX6-NEXT: v_mov_b32_e32 v3, s3 ; GFX6-NEXT: v_mov_b32_e32 v5, s11 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc @@ -4853,36 +4870,53 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) { ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 +; GFX8-NEXT: s_movk_i32 s2, 0x7f +; GFX8-NEXT: s_sub_i32 s6, s2, 64 +; GFX8-NEXT: s_sub_i32 s4, 64, s2 +; GFX8-NEXT: s_cmp_lt_u32 s2, 64 +; GFX8-NEXT: s_cselect_b32 s12, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s2, 0 +; GFX8-NEXT: s_cselect_b32 s13, 1, 0 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX8-NEXT: s_ashr_i32 s3, s11, 31 -; GFX8-NEXT: s_ashr_i64 s[0:1], s[10:11], s0 -; GFX8-NEXT: s_add_u32 s0, s0, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 -; GFX8-NEXT: s_and_b32 s2, s2, 1 -; GFX8-NEXT: s_cmp_lg_u32 s2, 0 -; GFX8-NEXT: s_addc_u32 s1, s1, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 -; GFX8-NEXT: s_and_b32 s2, s2, 1 -; GFX8-NEXT: s_cmp_lg_u32 s2, 0 -; GFX8-NEXT: s_addc_u32 s2, s3, 0 +; GFX8-NEXT: s_ashr_i64 s[0:1], s[10:11], s2 +; GFX8-NEXT: s_lshr_b64 s[2:3], s[8:9], s2 +; GFX8-NEXT: s_lshl_b64 s[4:5], s[10:11], s4 +; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] +; GFX8-NEXT: s_ashr_i32 s4, s11, 31 +; GFX8-NEXT: s_ashr_i64 s[6:7], s[10:11], s6 +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX8-NEXT: s_cmp_lg_u32 s13, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX8-NEXT: s_mov_b32 s5, s4 +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] +; GFX8-NEXT: s_add_u32 s2, s2, 0 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_and_b32 s4, s4, 1 +; GFX8-NEXT: s_cmp_lg_u32 s4, 0 +; GFX8-NEXT: s_addc_u32 s3, s3, 0 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_and_b32 s4, s4, 1 +; GFX8-NEXT: s_cmp_lg_u32 s4, 0 +; GFX8-NEXT: s_addc_u32 s0, s0, 0 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_and_b32 s4, s4, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX8-NEXT: s_addc_u32 s3, s3, 0x80000000 -; GFX8-NEXT: v_mov_b32_e32 v1, s0 -; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX8-NEXT: v_mov_b32_e32 v1, s2 +; GFX8-NEXT: v_mov_b32_e32 v2, s3 ; GFX8-NEXT: v_mov_b32_e32 v3, s8 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_mov_b32_e32 v4, s9 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc -; GFX8-NEXT: v_mov_b32_e32 v2, s2 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v4, s10 -; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: v_mov_b32_e32 v5, s11 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc @@ -4927,36 +4961,53 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) { ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 +; GFX9-NEXT: s_movk_i32 s2, 0x7f +; GFX9-NEXT: s_sub_i32 s6, s2, 64 +; GFX9-NEXT: s_sub_i32 s4, 64, s2 +; GFX9-NEXT: s_cmp_lt_u32 s2, 64 +; GFX9-NEXT: s_cselect_b32 s12, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s2, 0 +; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX9-NEXT: s_ashr_i32 s3, s11, 31 -; GFX9-NEXT: s_ashr_i64 s[0:1], s[10:11], s0 -; GFX9-NEXT: s_add_u32 s0, s0, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 -; GFX9-NEXT: s_and_b32 s2, s2, 1 -; GFX9-NEXT: s_cmp_lg_u32 s2, 0 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 -; GFX9-NEXT: s_and_b32 s2, s2, 1 -; GFX9-NEXT: s_cmp_lg_u32 s2, 0 -; GFX9-NEXT: s_addc_u32 s2, s3, 0 +; GFX9-NEXT: s_ashr_i64 s[0:1], s[10:11], s2 +; GFX9-NEXT: s_lshr_b64 s[2:3], s[8:9], s2 +; GFX9-NEXT: s_lshl_b64 s[4:5], s[10:11], s4 +; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] +; GFX9-NEXT: s_ashr_i32 s4, s11, 31 +; GFX9-NEXT: s_ashr_i64 s[6:7], s[10:11], s6 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX9-NEXT: s_cmp_lg_u32 s13, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] +; GFX9-NEXT: s_add_u32 s2, s2, 0 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_and_b32 s4, s4, 1 +; GFX9-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-NEXT: s_addc_u32 s3, s3, 0 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_and_b32 s4, s4, 1 +; GFX9-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-NEXT: s_addc_u32 s0, s0, 0 ; GFX9-NEXT: s_cselect_b32 s4, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_and_b32 s4, s4, 1 ; GFX9-NEXT: s_cmp_lg_u32 s4, 0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX9-NEXT: s_addc_u32 s3, s3, 0x80000000 -; GFX9-NEXT: v_mov_b32_e32 v1, s0 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX9-NEXT: v_mov_b32_e32 v1, s2 +; GFX9-NEXT: v_mov_b32_e32 v2, s3 ; GFX9-NEXT: v_mov_b32_e32 v3, s8 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_mov_b32_e32 v4, s9 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v4, s10 -; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v5, s11 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc @@ -4970,6 +5021,7 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_sub_u32 s8, s0, s4 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_movk_i32 s12, 0x7f ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: s_subb_u32 s9, s1, s5 @@ -4994,38 +5046,54 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) { ; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[4:5], 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 ; GFX10-NEXT: s_cselect_b32 s1, 1, 0 -; GFX10-NEXT: s_ashr_i32 s3, s11, 31 -; GFX10-NEXT: s_and_b32 s2, 1, s1 +; GFX10-NEXT: s_sub_i32 s13, s12, 64 +; GFX10-NEXT: s_and_b32 s14, 1, s1 +; GFX10-NEXT: s_sub_i32 s15, 64, s12 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo +; GFX10-NEXT: s_cmp_lt_u32 s12, 64 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[6:7], 0 -; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 +; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s12, 0 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s14 +; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[2:3], s[8:9], s12 +; GFX10-NEXT: s_lshl_b64 s[4:5], s[10:11], s15 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 -; GFX10-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX10-NEXT: s_ashr_i64 s[0:1], s[10:11], s0 -; GFX10-NEXT: s_add_u32 s0, s0, 0 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_ashr_i32 s6, s11, 31 +; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] +; GFX10-NEXT: s_ashr_i64 s[0:1], s[10:11], s12 +; GFX10-NEXT: s_ashr_i64 s[4:5], s[10:11], s13 +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 +; GFX10-NEXT: s_mov_b32 s7, s6 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] +; GFX10-NEXT: s_cmp_lg_u32 s17, 0 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo -; GFX10-NEXT: s_and_b32 s4, s4, 1 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, s9 -; GFX10-NEXT: s_cmp_lg_u32 s4, 0 -; GFX10-NEXT: s_addc_u32 s1, s1, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7] +; GFX10-NEXT: s_add_u32 s2, s2, 0 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX10-NEXT: s_and_b32 s2, s2, 1 +; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, s8 -; GFX10-NEXT: s_cmp_lg_u32 s2, 0 -; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_addc_u32 s2, s3, 0 +; GFX10-NEXT: s_cmp_lg_u32 s4, 0 +; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: s_and_b32 s4, s4, 1 +; GFX10-NEXT: s_cmp_lg_u32 s4, 0 +; GFX10-NEXT: s_addc_u32 s0, s0, 0 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 -; GFX10-NEXT: s_addc_u32 s3, s3, 0x80000000 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, s2, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, s3, vcc_lo +; GFX10-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, s0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, s1, vcc_lo ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2 @@ -5046,31 +5114,54 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) { ; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v6, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc ; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5] -; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64 +; GFX6-NEXT: s_movk_i32 s0, 0x7f ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7] +; GFX6-NEXT: s_sub_i32 s1, s0, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7] +; GFX6-NEXT: s_sub_i32 s2, 64, s0 ; GFX6-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1] +; GFX6-NEXT: s_cmp_lt_u32 s0, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3] +; GFX6-NEXT: s_cselect_b32 s3, 1, 0 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] -; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v7 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], s2 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GFX6-NEXT: v_xor_b32_e32 v2, v0, v8 -; GFX6-NEXT: v_ashr_i64 v[0:1], v[6:7], s0 -; GFX6-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX6-NEXT: v_xor_b32_e32 v10, v0, v8 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s0 +; GFX6-NEXT: s_cmp_eq_u32 s0, 0 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: v_ashr_i64 v[8:9], v[6:7], s0 +; GFX6-NEXT: s_and_b32 s0, 1, s3 +; GFX6-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX6-NEXT: v_ashr_i64 v[0:1], v[6:7], s1 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: s_and_b32 s0, 1, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: s_and_b32 s0, 1, s3 +; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc +; GFX6-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc -; GFX6-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX6-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX6-NEXT: ; return to shader part epilog ; @@ -5084,31 +5175,54 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) { ; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v2, vcc ; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc ; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5] -; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64 +; GFX8-NEXT: s_movk_i32 s0, 0x7f ; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7] +; GFX8-NEXT: s_sub_i32 s1, s0, 64 ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7] +; GFX8-NEXT: s_sub_i32 s2, 64, s0 ; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1] +; GFX8-NEXT: s_cmp_lt_u32 s0, 64 ; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3] +; GFX8-NEXT: s_cselect_b32 s3, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] -; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v7 +; GFX8-NEXT: v_lshlrev_b64 v[2:3], s2, v[6:7] ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GFX8-NEXT: v_xor_b32_e32 v2, v0, v8 -; GFX8-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] -; GFX8-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX8-NEXT: v_xor_b32_e32 v10, v0, v8 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX8-NEXT: s_cmp_eq_u32 s0, 0 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] +; GFX8-NEXT: s_and_b32 s0, 1, s3 +; GFX8-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX8-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_and_b32 s0, 1, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_and_b32 s0, 1, s3 +; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc +; GFX8-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX8-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX8-NEXT: ; return to shader part epilog ; @@ -5122,31 +5236,54 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) { ; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v7, v3, vcc ; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5] -; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64 +; GFX9-NEXT: s_movk_i32 s0, 0x7f ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7] +; GFX9-NEXT: s_sub_i32 s1, s0, 64 ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7] +; GFX9-NEXT: s_sub_i32 s2, 64, s0 ; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1] +; GFX9-NEXT: s_cmp_lt_u32 s0, 64 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3] +; GFX9-NEXT: s_cselect_b32 s3, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] -; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v7 +; GFX9-NEXT: v_lshlrev_b64 v[2:3], s2, v[6:7] ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GFX9-NEXT: v_xor_b32_e32 v2, v0, v8 -; GFX9-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] -; GFX9-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX9-NEXT: v_xor_b32_e32 v10, v0, v8 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX9-NEXT: s_cmp_eq_u32 s0, 0 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] +; GFX9-NEXT: s_and_b32 s0, 1, s3 +; GFX9-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX9-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_and_b32 s0, 1, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_and_b32 s0, 1, s3 +; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v3, vcc +; GFX9-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc -; GFX9-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX9-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX9-NEXT: ; return to shader part epilog ; @@ -5157,31 +5294,52 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) { ; GFX10-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo ; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5] -; GFX10-NEXT: s_sub_i32 s0, 0x7f, 64 +; GFX10-NEXT: s_movk_i32 s0, 0x7f +; GFX10-NEXT: s_sub_i32 s1, 64, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7] ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7] +; GFX10-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc_lo ; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1] -; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX10-NEXT: v_lshlrev_b64 v[8:9], s1, v[6:7] +; GFX10-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX10-NEXT: s_sub_i32 s1, s0, 64 +; GFX10-NEXT: s_cmp_lt_u32 s0, 64 +; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3] -; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo -; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7] -; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo -; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] -; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo -; GFX10-NEXT: v_xor_b32_e32 v2, v0, v8 +; GFX10-NEXT: v_or_b32_e32 v8, v0, v8 +; GFX10-NEXT: v_or_b32_e32 v9, v1, v9 ; GFX10-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] -; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v2 -; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0x80000000, v3, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] +; GFX10-NEXT: v_ashrrev_i64 v[2:3], s1, v[6:7] +; GFX10-NEXT: v_cndmask_b32_e32 v11, v12, v11, vcc_lo +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s0, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo +; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo +; GFX10-NEXT: s_and_b32 s0, 1, s1 +; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 +; GFX10-NEXT: v_ashrrev_i32_e32 v8, 31, v7 +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 +; GFX10-NEXT: v_xor_b32_e32 v9, v11, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, v1, s0 +; GFX10-NEXT: v_and_b32_e32 v8, 1, v9 +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v8 +; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v2, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v3, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0 ; GFX10-NEXT: ; return to shader part epilog %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs) %cast = bitcast i128 %result to <4 x float> @@ -5202,28 +5360,51 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) { ; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[0:1], 0 ; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3] -; GFX6-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v7 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3] -; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v7 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0 ; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[2:3], 0 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX6-NEXT: s_movk_i32 s0, 0x7f ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX6-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX6-NEXT: v_ashr_i64 v[0:1], v[6:7], s0 -; GFX6-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX6-NEXT: s_sub_i32 s2, 64, s0 +; GFX6-NEXT: s_sub_i32 s1, s0, 64 +; GFX6-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX6-NEXT: s_cmp_lt_u32 s0, 64 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s0 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], s2 +; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s0, 0 +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: v_ashr_i64 v[8:9], v[6:7], s0 +; GFX6-NEXT: s_and_b32 s0, 1, s3 +; GFX6-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX6-NEXT: v_ashr_i64 v[0:1], v[6:7], s1 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: s_and_b32 s0, 1, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: s_and_b32 s0, 1, s3 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc +; GFX6-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX6-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX6-NEXT: ; return to shader part epilog ; @@ -5247,24 +5428,47 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) { ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0 -; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v7 +; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v7 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s4 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_movk_i32 s0, 0x7f ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX8-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX8-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] -; GFX8-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX8-NEXT: s_sub_i32 s2, 64, s0 +; GFX8-NEXT: s_sub_i32 s1, s0, 64 +; GFX8-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX8-NEXT: s_cmp_lt_u32 s0, 64 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX8-NEXT: v_lshlrev_b64 v[2:3], s2, v[6:7] +; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s0, 0 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] +; GFX8-NEXT: s_and_b32 s0, 1, s3 +; GFX8-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX8-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_and_b32 s0, 1, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: s_and_b32 s0, 1, s3 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc +; GFX8-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc -; GFX8-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX8-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX8-NEXT: ; return to shader part epilog ; @@ -5288,24 +5492,47 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) { ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0 -; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v7 +; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v7 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s4 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_movk_i32 s0, 0x7f ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX9-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX9-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] -; GFX9-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX9-NEXT: s_sub_i32 s2, 64, s0 +; GFX9-NEXT: s_sub_i32 s1, s0, 64 +; GFX9-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX9-NEXT: s_cmp_lt_u32 s0, 64 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX9-NEXT: v_lshlrev_b64 v[2:3], s2, v[6:7] +; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s0, 0 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] +; GFX9-NEXT: s_and_b32 s0, 1, s3 +; GFX9-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX9-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_and_b32 s0, 1, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: s_and_b32 s0, 1, s3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v3, vcc +; GFX9-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc -; GFX9-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX9-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX9-NEXT: ; return to shader part epilog ; @@ -5321,29 +5548,50 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) { ; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1] ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0 ; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[2:3], 0 +; GFX10-NEXT: s_and_b32 s1, 1, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3] ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0 -; GFX10-NEXT: s_and_b32 s0, 1, s4 +; GFX10-NEXT: s_movk_i32 s0, 0x7f +; GFX10-NEXT: s_sub_i32 s2, 64, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3] -; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo -; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 -; GFX10-NEXT: s_sub_i32 s0, 0x7f, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo -; GFX10-NEXT: v_xor_b32_e32 v2, v1, v0 +; GFX10-NEXT: v_lshlrev_b64 v[2:3], s2, v[6:7] +; GFX10-NEXT: v_cndmask_b32_e32 v10, v1, v0, vcc_lo +; GFX10-NEXT: v_lshrrev_b64 v[0:1], s0, v[4:5] +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 +; GFX10-NEXT: s_sub_i32 s1, s0, 64 +; GFX10-NEXT: s_cmp_lt_u32 s0, 64 +; GFX10-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: v_ashrrev_i64 v[8:9], s1, v[6:7] +; GFX10-NEXT: s_cmp_eq_u32 s0, 0 +; GFX10-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX10-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX10-NEXT: s_cselect_b32 s1, 1, 0 ; GFX10-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] -; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v2 -; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0x80000000, v3, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0 +; GFX10-NEXT: s_and_b32 s0, 1, s1 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo +; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 +; GFX10-NEXT: v_ashrrev_i32_e32 v8, 31, v7 +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 +; GFX10-NEXT: v_xor_b32_e32 v9, v11, v10 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, v1, s0 +; GFX10-NEXT: v_and_b32_e32 v8, 1, v9 +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v8 +; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v2, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v3, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0 ; GFX10-NEXT: ; return to shader part epilog %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs) %cast = bitcast i128 %result to <4 x float> @@ -5359,60 +5607,102 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) { ; GFX6-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc ; GFX6-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1] -; GFX6-NEXT: s_sub_i32 s4, 0x7f, 64 +; GFX6-NEXT: s_movk_i32 s6, 0x7f ; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3] -; GFX6-NEXT: v_bfrev_b32_e32 v20, 1 +; GFX6-NEXT: s_sub_i32 s7, s6, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3] -; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v19 +; GFX6-NEXT: s_sub_i32 s8, 64, s6 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9] +; GFX6-NEXT: s_cmp_lt_u32 s6, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11] +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] +; GFX6-NEXT: s_cmp_eq_u32 s6, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX6-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX6-NEXT: v_ashr_i64 v[0:1], v[18:19], s4 -; GFX6-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX6-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[16:17], s6 +; GFX6-NEXT: v_lshl_b64 v[2:3], v[18:19], s8 +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_and_b32 s4, 1, s4 +; GFX6-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX6-NEXT: v_ashr_i64 v[0:1], v[18:19], s7 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: s_and_b32 s4, 1, s5 +; GFX6-NEXT: v_ashr_i64 v[8:9], v[18:19], s6 +; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v19 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5] ; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc +; GFX6-NEXT: v_bfrev_b32_e32 v20, 1 +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v20, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX6-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v4, v12 ; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc ; GFX6-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc ; GFX6-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GFX6-NEXT: s_cmp_lt_u32 s6, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] +; GFX6-NEXT: s_cselect_b32 s4, 1, 0 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] -; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v11 +; GFX6-NEXT: s_cmp_eq_u32 s6, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13] +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15] +; GFX6-NEXT: v_ashr_i64 v[12:13], v[10:11], s6 ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] +; GFX6-NEXT: s_and_b32 s5, 1, s5 ; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX6-NEXT: v_xor_b32_e32 v6, v5, v4 -; GFX6-NEXT: v_ashr_i64 v[4:5], v[10:11], s4 -; GFX6-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX6-NEXT: v_xor_b32_e32 v14, v5, v4 +; GFX6-NEXT: v_lshr_b64 v[4:5], v[8:9], s6 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[10:11], s8 +; GFX6-NEXT: s_and_b32 s6, 1, s4 +; GFX6-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX6-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX6-NEXT: v_ashr_i64 v[4:5], v[10:11], s7 +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 +; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX6-NEXT: s_and_b32 s4, 1, s4 +; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v11 +; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc +; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0, v4 ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GFX6-NEXT: v_addc_u32_e32 v12, vcc, 0, v7, vcc +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v20, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX6-NEXT: v_and_b32_e32 v12, 1, v14 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -5424,60 +5714,102 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) { ; GFX8-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc ; GFX8-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1] -; GFX8-NEXT: s_sub_i32 s4, 0x7f, 64 +; GFX8-NEXT: s_movk_i32 s6, 0x7f ; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3] -; GFX8-NEXT: v_bfrev_b32_e32 v20, 1 +; GFX8-NEXT: s_sub_i32 s7, s6, 64 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3] -; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v19 +; GFX8-NEXT: s_sub_i32 s8, 64, s6 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9] +; GFX8-NEXT: s_cmp_lt_u32 s6, 64 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11] +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] +; GFX8-NEXT: s_cmp_eq_u32 s6, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX8-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX8-NEXT: v_ashrrev_i64 v[0:1], s4, v[18:19] -; GFX8-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX8-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s6, v[16:17] +; GFX8-NEXT: v_lshlrev_b64 v[2:3], s8, v[18:19] +; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_and_b32 s4, 1, s4 +; GFX8-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX8-NEXT: v_ashrrev_i64 v[0:1], s7, v[18:19] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: s_and_b32 s4, 1, s5 +; GFX8-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v19 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5] ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc +; GFX8-NEXT: v_bfrev_b32_e32 v20, 1 +; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v20, vcc -; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX8-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v4, v12 ; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc ; GFX8-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc ; GFX8-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GFX8-NEXT: s_cmp_lt_u32 s6, 64 ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] -; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v11 +; GFX8-NEXT: s_cmp_eq_u32 s6, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13] +; GFX8-NEXT: s_cselect_b32 s5, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15] +; GFX8-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11] ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] +; GFX8-NEXT: s_and_b32 s5, 1, s5 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_xor_b32_e32 v6, v5, v4 -; GFX8-NEXT: v_ashrrev_i64 v[4:5], s4, v[10:11] -; GFX8-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX8-NEXT: v_xor_b32_e32 v14, v5, v4 +; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9] +; GFX8-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11] +; GFX8-NEXT: s_and_b32 s6, 1, s4 +; GFX8-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX8-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX8-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11] +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX8-NEXT: s_and_b32 s4, 1, s4 +; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v11 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc +; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0, v4 ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GFX8-NEXT: v_addc_u32_e32 v12, vcc, 0, v7, vcc +; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v20, vcc -; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX8-NEXT: v_and_b32_e32 v12, 1, v14 +; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -5489,60 +5821,102 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) { ; GFX9-NEXT: v_subb_co_u32_e32 v18, vcc, v2, v10, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v19, vcc, v3, v11, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1] -; GFX9-NEXT: s_sub_i32 s4, 0x7f, 64 +; GFX9-NEXT: s_movk_i32 s6, 0x7f ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3] -; GFX9-NEXT: v_bfrev_b32_e32 v20, 1 +; GFX9-NEXT: s_sub_i32 s7, s6, 64 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3] -; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v19 +; GFX9-NEXT: s_sub_i32 s8, 64, s6 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9] +; GFX9-NEXT: s_cmp_lt_u32 s6, 64 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11] +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] +; GFX9-NEXT: s_cmp_eq_u32 s6, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX9-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX9-NEXT: v_ashrrev_i64 v[0:1], s4, v[18:19] -; GFX9-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX9-NEXT: v_xor_b32_e32 v10, v1, v0 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s6, v[16:17] +; GFX9-NEXT: v_lshlrev_b64 v[2:3], s8, v[18:19] +; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_and_b32 s4, 1, s4 +; GFX9-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX9-NEXT: v_ashrrev_i64 v[0:1], s7, v[18:19] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: s_and_b32 s4, 1, s5 +; GFX9-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19] +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v19 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5] ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v3, vcc +; GFX9-NEXT: v_bfrev_b32_e32 v20, 1 +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v20, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX9-NEXT: v_and_b32_e32 v8, 1, v10 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v4, v12 ; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v5, v13, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v6, v14, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v15, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GFX9-NEXT: s_cmp_lt_u32 s6, 64 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] -; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v11 +; GFX9-NEXT: s_cmp_eq_u32 s6, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13] +; GFX9-NEXT: s_cselect_b32 s5, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15] +; GFX9-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11] ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] +; GFX9-NEXT: s_and_b32 s5, 1, s5 ; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX9-NEXT: v_xor_b32_e32 v6, v5, v4 -; GFX9-NEXT: v_ashrrev_i64 v[4:5], s4, v[10:11] -; GFX9-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX9-NEXT: v_xor_b32_e32 v14, v5, v4 +; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9] +; GFX9-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11] +; GFX9-NEXT: s_and_b32 s6, 1, s4 +; GFX9-NEXT: v_or_b32_e32 v6, v4, v6 +; GFX9-NEXT: v_or_b32_e32 v7, v5, v7 +; GFX9-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11] +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX9-NEXT: s_and_b32 s4, 1, s4 +; GFX9-NEXT: v_ashrrev_i32_e32 v15, 31, v11 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc +; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v7, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v20, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX9-NEXT: v_and_b32_e32 v12, 1, v14 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -5551,64 +5925,104 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v8 -; GFX10-NEXT: s_sub_i32 s6, 0x7f, 64 +; GFX10-NEXT: s_movk_i32 s5, 0x7f ; GFX10-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo +; GFX10-NEXT: s_sub_i32 s6, 64, s5 ; GFX10-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo +; GFX10-NEXT: s_sub_i32 s7, s5, 64 ; GFX10-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo ; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1] +; GFX10-NEXT: s_cmp_lt_u32 s5, 64 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3] ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3] +; GFX10-NEXT: v_lshlrev_b64 v[2:3], s6, v[18:19] +; GFX10-NEXT: v_cndmask_b32_e32 v20, v1, v0, vcc_lo ; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9] +; GFX10-NEXT: v_lshrrev_b64 v[0:1], s5, v[16:17] ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11] +; GFX10-NEXT: v_or_b32_e32 v2, v0, v2 +; GFX10-NEXT: v_or_b32_e32 v3, v1, v3 +; GFX10-NEXT: v_ashrrev_i64 v[0:1], s5, v[18:19] ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo -; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3] -; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] -; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo -; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v12 -; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo -; GFX10-NEXT: v_sub_co_ci_u32_e32 v10, vcc_lo, v6, v14, vcc_lo -; GFX10-NEXT: v_xor_b32_e32 v2, v1, v0 -; GFX10-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v7, v15, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc_lo +; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: v_ashrrev_i64 v[8:9], s7, v[18:19] +; GFX10-NEXT: s_cmp_eq_u32 s5, 0 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_and_b32 s8, 1, vcc_lo +; GFX10-NEXT: s_and_b32 s4, 1, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 +; GFX10-NEXT: v_ashrrev_i32_e32 v8, 31, v19 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s8 +; GFX10-NEXT: v_xor_b32_e32 v9, v10, v20 +; GFX10-NEXT: s_cmp_lt_u32 s5, 64 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, v1, s4 +; GFX10-NEXT: v_and_b32_e32 v8, 1, v9 +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e32 v21, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 +; GFX10-NEXT: v_sub_co_u32 v8, s4, v4, v12 +; GFX10-NEXT: v_sub_co_ci_u32_e64 v9, s4, v5, v13, s4 +; GFX10-NEXT: v_sub_co_ci_u32_e64 v10, s4, v6, v14, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc_lo +; GFX10-NEXT: v_sub_co_ci_u32_e64 v11, s4, v7, v15, s4 ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[4:5] -; GFX10-NEXT: v_ashrrev_i64 v[0:1], s6, v[18:19] -; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX10-NEXT: v_cmp_eq_u64_e64 s5, v[10:11], v[6:7] -; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4 -; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[10:11], v[6:7] -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v20, vcc_lo +; GFX10-NEXT: v_lshrrev_b64 v[3:4], s5, v[8:9] ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4 +; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[10:11], v[6:7] +; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s4 ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, 0, v[12:13] -; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s4 +; GFX10-NEXT: v_lshlrev_b64 v[12:13], s6, v[10:11] +; GFX10-NEXT: v_cndmask_b32_e64 v17, 0, 1, s4 ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[14:15] -; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s4 -; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v4, s5 -; GFX10-NEXT: v_cmp_eq_u64_e64 s5, 0, v[14:15] -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0x80000000, v3, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, v0, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, v1, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v13, v12, s5 -; GFX10-NEXT: v_xor_b32_e32 v7, v4, v2 -; GFX10-NEXT: v_ashrrev_i64 v[3:4], s6, v[10:11] -; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v5, s4 -; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v11 +; GFX10-NEXT: v_or_b32_e32 v12, v3, v12 +; GFX10-NEXT: v_or_b32_e32 v13, v4, v13 +; GFX10-NEXT: v_ashrrev_i64 v[3:4], s5, v[10:11] +; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, s4 +; GFX10-NEXT: v_cmp_eq_u64_e64 s4, v[10:11], v[6:7] +; GFX10-NEXT: v_cndmask_b32_e64 v7, v16, v5, s4 +; GFX10-NEXT: v_cmp_eq_u64_e64 s4, 0, v[14:15] +; GFX10-NEXT: v_ashrrev_i64 v[5:6], s7, v[10:11] +; GFX10-NEXT: v_cndmask_b32_e64 v14, v18, v17, s4 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s5, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v12, s4 +; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v13, s4 +; GFX10-NEXT: s_and_b32 s5, 1, s6 +; GFX10-NEXT: s_and_b32 s6, 1, s4 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s5 +; GFX10-NEXT: v_xor_b32_e32 v7, v14, v7 +; GFX10-NEXT: v_ashrrev_i32_e32 v12, 31, v11 +; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v8, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v9, s4 ; GFX10-NEXT: v_and_b32_e32 v7, 1, v7 -; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, v3, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v19, v6, s4 -; GFX10-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v3, v12, v3, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v12, v4, s5 +; GFX10-NEXT: v_add_co_u32 v5, s4, v5, 0 +; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s4, 0, v6, s4 ; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v7 -; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo -; GFX10-NEXT: v_add_co_ci_u32_e32 v14, vcc_lo, 0x80000000, v5, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v12, s5 +; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, 0, v3, s4 +; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v21, vcc_lo +; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s4, 0x80000000, v4, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v5, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v6, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v7, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v13, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v14, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v12, s5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs) ret <2 x i128> %result @@ -5634,55 +6048,72 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3] ; GFX6-NEXT: v_mov_b32_e32 v0, s2 ; GFX6-NEXT: s_subb_u32 s19, s3, s11 +; GFX6-NEXT: s_movk_i32 s20, 0x7f ; GFX6-NEXT: v_mov_b32_e32 v1, s3 -; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1] -; GFX6-NEXT: s_sub_i32 s8, 0x7f, 64 +; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0 +; GFX6-NEXT: s_sub_i32 s21, s20, 64 +; GFX6-NEXT: s_sub_i32 s22, 64, s20 +; GFX6-NEXT: s_cmp_lt_u32 s20, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[18:19], v[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; GFX6-NEXT: s_cselect_b32 s23, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s20, 0 ; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0 +; GFX6-NEXT: s_cselect_b32 s24, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[2:3], s[16:17], s20 +; GFX6-NEXT: s_lshl_b64 s[8:9], s[18:19], s22 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] -; GFX6-NEXT: s_ashr_i32 s3, s19, 31 -; GFX6-NEXT: s_ashr_i64 s[0:1], s[18:19], s8 -; GFX6-NEXT: s_add_u32 s0, s0, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 -; GFX6-NEXT: s_and_b32 s2, s2, 1 -; GFX6-NEXT: s_cmp_lg_u32 s2, 0 -; GFX6-NEXT: s_addc_u32 s1, s1, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 -; GFX6-NEXT: s_and_b32 s2, s2, 1 -; GFX6-NEXT: s_cmp_lg_u32 s2, 0 -; GFX6-NEXT: s_addc_u32 s2, s3, 0 ; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[10:11], 0 -; GFX6-NEXT: s_cselect_b32 s10, 1, 0 -; GFX6-NEXT: s_and_b32 s10, s10, 1 -; GFX6-NEXT: s_brev_b32 s9, 1 -; GFX6-NEXT: s_cmp_lg_u32 s10, 0 +; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX6-NEXT: s_ashr_i32 s8, s19, 31 +; GFX6-NEXT: s_ashr_i64 s[0:1], s[18:19], s20 +; GFX6-NEXT: s_ashr_i64 s[10:11], s[18:19], s21 +; GFX6-NEXT: s_cmp_lg_u32 s23, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11] +; GFX6-NEXT: s_cmp_lg_u32 s24, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX6-NEXT: s_cmp_lg_u32 s23, 0 +; GFX6-NEXT: s_mov_b32 s9, s8 +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] +; GFX6-NEXT: s_add_u32 s2, s2, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_and_b32 s8, s8, 1 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 +; GFX6-NEXT: s_addc_u32 s3, s3, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_and_b32 s8, s8, 1 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 +; GFX6-NEXT: s_addc_u32 s0, s0, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX6-NEXT: s_addc_u32 s3, s3, s9 +; GFX6-NEXT: s_and_b32 s8, s8, 1 ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, s0 +; GFX6-NEXT: s_brev_b32 s23, 1 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 +; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX6-NEXT: s_addc_u32 s1, s1, s23 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX6-NEXT: v_mov_b32_e32 v0, s0 +; GFX6-NEXT: v_mov_b32_e32 v1, s2 +; GFX6-NEXT: v_mov_b32_e32 v3, s16 ; GFX6-NEXT: s_sub_u32 s0, s4, s12 -; GFX6-NEXT: v_mov_b32_e32 v2, s1 +; GFX6-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc +; GFX6-NEXT: v_mov_b32_e32 v1, s1 ; GFX6-NEXT: s_cselect_b32 s1, 1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 -; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: s_subb_u32 s1, s5, s13 -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX6-NEXT: v_mov_b32_e32 v0, s2 ; GFX6-NEXT: s_cselect_b32 s2, 1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 +; GFX6-NEXT: v_mov_b32_e32 v2, s3 ; GFX6-NEXT: v_mov_b32_e32 v4, s17 -; GFX6-NEXT: v_mov_b32_e32 v3, s16 -; GFX6-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; GFX6-NEXT: v_mov_b32_e32 v2, s18 -; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v3, s19 ; GFX6-NEXT: s_subb_u32 s2, s6, s14 ; GFX6-NEXT: s_cselect_b32 s3, 1, 0 @@ -5699,24 +6130,39 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1] ; GFX6-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 0 +; GFX6-NEXT: s_cmp_lt_u32 s20, 64 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] +; GFX6-NEXT: s_cselect_b32 s12, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s20, 0 ; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0 +; GFX6-NEXT: s_cselect_b32 s13, 1, 0 +; GFX6-NEXT: s_lshr_b64 s[6:7], s[0:1], s20 +; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s22 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] -; GFX6-NEXT: s_ashr_i32 s7, s3, 31 -; GFX6-NEXT: s_ashr_i64 s[4:5], s[2:3], s8 -; GFX6-NEXT: s_add_u32 s4, s4, 0 -; GFX6-NEXT: s_cselect_b32 s6, 1, 0 -; GFX6-NEXT: s_and_b32 s6, s6, 1 -; GFX6-NEXT: s_cmp_lg_u32 s6, 0 -; GFX6-NEXT: s_addc_u32 s5, s5, 0 -; GFX6-NEXT: s_cselect_b32 s6, 1, 0 -; GFX6-NEXT: s_and_b32 s6, s6, 1 -; GFX6-NEXT: s_cmp_lg_u32 s6, 0 +; GFX6-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] +; GFX6-NEXT: s_ashr_i32 s8, s3, 31 +; GFX6-NEXT: s_ashr_i64 s[4:5], s[2:3], s20 +; GFX6-NEXT: s_ashr_i64 s[10:11], s[2:3], s21 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11] +; GFX6-NEXT: s_cmp_lg_u32 s13, 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], s[0:1], s[6:7] +; GFX6-NEXT: s_mov_b32 s9, s8 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] +; GFX6-NEXT: s_add_u32 s6, s6, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_and_b32 s8, s8, 1 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 +; GFX6-NEXT: s_addc_u32 s7, s7, 0 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_and_b32 s8, s8, 1 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 ; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[14:15], 0 -; GFX6-NEXT: s_addc_u32 s6, s7, 0 +; GFX6-NEXT: s_addc_u32 s4, s4, 0 ; GFX6-NEXT: s_cselect_b32 s8, 1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 @@ -5725,16 +6171,16 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: v_mov_b32_e32 v3, s0 ; GFX6-NEXT: v_mov_b32_e32 v8, s1 -; GFX6-NEXT: s_addc_u32 s7, s7, s9 -; GFX6-NEXT: v_mov_b32_e32 v1, s4 +; GFX6-NEXT: s_addc_u32 s5, s5, s23 +; GFX6-NEXT: v_mov_b32_e32 v1, s6 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX6-NEXT: v_mov_b32_e32 v2, s5 +; GFX6-NEXT: v_mov_b32_e32 v2, s7 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc +; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: v_mov_b32_e32 v8, s2 -; GFX6-NEXT: v_mov_b32_e32 v2, s6 +; GFX6-NEXT: v_mov_b32_e32 v3, s5 ; GFX6-NEXT: v_mov_b32_e32 v9, s3 -; GFX6-NEXT: v_mov_b32_e32 v3, s7 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc ; GFX6-NEXT: v_readfirstlane_b32 s0, v5 @@ -5779,49 +6225,66 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0 ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_movk_i32 s20, 0x7f ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 -; GFX8-NEXT: s_sub_i32 s8, 0x7f, 64 +; GFX8-NEXT: s_sub_i32 s21, s20, 64 +; GFX8-NEXT: s_sub_i32 s22, 64, s20 +; GFX8-NEXT: s_cmp_lt_u32 s20, 64 +; GFX8-NEXT: s_cselect_b32 s23, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s20, 0 +; GFX8-NEXT: s_cselect_b32 s24, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[2:3], s[16:17], s20 +; GFX8-NEXT: s_lshl_b64 s[8:9], s[18:19], s22 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_ashr_i32 s3, s19, 31 -; GFX8-NEXT: s_ashr_i64 s[0:1], s[18:19], s8 -; GFX8-NEXT: s_add_u32 s0, s0, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 -; GFX8-NEXT: s_and_b32 s2, s2, 1 -; GFX8-NEXT: s_cmp_lg_u32 s2, 0 -; GFX8-NEXT: s_addc_u32 s1, s1, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 -; GFX8-NEXT: s_and_b32 s2, s2, 1 -; GFX8-NEXT: s_cmp_lg_u32 s2, 0 -; GFX8-NEXT: s_addc_u32 s2, s3, 0 -; GFX8-NEXT: s_cselect_b32 s10, 1, 0 -; GFX8-NEXT: s_and_b32 s10, s10, 1 -; GFX8-NEXT: s_brev_b32 s9, 1 -; GFX8-NEXT: s_cmp_lg_u32 s10, 0 +; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX8-NEXT: s_ashr_i32 s8, s19, 31 +; GFX8-NEXT: s_ashr_i64 s[0:1], s[18:19], s20 +; GFX8-NEXT: s_ashr_i64 s[10:11], s[18:19], s21 +; GFX8-NEXT: s_cmp_lg_u32 s23, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11] +; GFX8-NEXT: s_cmp_lg_u32 s24, 0 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX8-NEXT: s_cmp_lg_u32 s23, 0 +; GFX8-NEXT: s_mov_b32 s9, s8 +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] +; GFX8-NEXT: s_add_u32 s2, s2, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_and_b32 s8, s8, 1 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 +; GFX8-NEXT: s_addc_u32 s3, s3, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_and_b32 s8, s8, 1 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 +; GFX8-NEXT: s_addc_u32 s0, s0, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX8-NEXT: s_addc_u32 s3, s3, s9 +; GFX8-NEXT: s_and_b32 s8, s8, 1 ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, s0 +; GFX8-NEXT: s_brev_b32 s23, 1 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX8-NEXT: s_addc_u32 s1, s1, s23 +; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s2 +; GFX8-NEXT: v_mov_b32_e32 v3, s16 ; GFX8-NEXT: s_sub_u32 s0, s4, s12 -; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: s_subb_u32 s1, s5, s13 -; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 +; GFX8-NEXT: v_mov_b32_e32 v2, s3 ; GFX8-NEXT: v_mov_b32_e32 v4, s17 -; GFX8-NEXT: v_mov_b32_e32 v3, s16 ; GFX8-NEXT: s_subb_u32 s2, s6, s14 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc -; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; GFX8-NEXT: v_mov_b32_e32 v2, s18 ; GFX8-NEXT: v_mov_b32_e32 v3, s19 ; GFX8-NEXT: s_and_b32 s3, s3, 1 @@ -5849,18 +6312,33 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] ; GFX8-NEXT: s_and_b32 s4, 1, s6 +; GFX8-NEXT: s_cmp_lt_u32 s20, 64 +; GFX8-NEXT: s_cselect_b32 s12, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s20, 0 +; GFX8-NEXT: s_cselect_b32 s13, 1, 0 +; GFX8-NEXT: s_lshr_b64 s[6:7], s[0:1], s20 +; GFX8-NEXT: s_lshl_b64 s[8:9], s[2:3], s22 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 -; GFX8-NEXT: s_ashr_i32 s7, s3, 31 -; GFX8-NEXT: s_ashr_i64 s[4:5], s[2:3], s8 -; GFX8-NEXT: s_add_u32 s4, s4, 0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 -; GFX8-NEXT: s_and_b32 s6, s6, 1 -; GFX8-NEXT: s_cmp_lg_u32 s6, 0 -; GFX8-NEXT: s_addc_u32 s5, s5, 0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 -; GFX8-NEXT: s_and_b32 s6, s6, 1 -; GFX8-NEXT: s_cmp_lg_u32 s6, 0 -; GFX8-NEXT: s_addc_u32 s6, s7, 0 +; GFX8-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] +; GFX8-NEXT: s_ashr_i32 s8, s3, 31 +; GFX8-NEXT: s_ashr_i64 s[4:5], s[2:3], s20 +; GFX8-NEXT: s_ashr_i64 s[10:11], s[2:3], s21 +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11] +; GFX8-NEXT: s_cmp_lg_u32 s13, 0 +; GFX8-NEXT: s_cselect_b64 s[6:7], s[0:1], s[6:7] +; GFX8-NEXT: s_mov_b32 s9, s8 +; GFX8-NEXT: s_cmp_lg_u32 s12, 0 +; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] +; GFX8-NEXT: s_add_u32 s6, s6, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_and_b32 s8, s8, 1 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 +; GFX8-NEXT: s_addc_u32 s7, s7, 0 +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_and_b32 s8, s8, 1 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 +; GFX8-NEXT: s_addc_u32 s4, s4, 0 ; GFX8-NEXT: s_cselect_b32 s8, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 @@ -5869,16 +6347,16 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_mov_b32_e32 v3, s0 ; GFX8-NEXT: v_mov_b32_e32 v8, s1 -; GFX8-NEXT: s_addc_u32 s7, s7, s9 -; GFX8-NEXT: v_mov_b32_e32 v1, s4 +; GFX8-NEXT: s_addc_u32 s5, s5, s23 +; GFX8-NEXT: v_mov_b32_e32 v1, s6 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX8-NEXT: v_mov_b32_e32 v2, s5 +; GFX8-NEXT: v_mov_b32_e32 v2, s7 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc +; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: v_mov_b32_e32 v8, s2 -; GFX8-NEXT: v_mov_b32_e32 v2, s6 +; GFX8-NEXT: v_mov_b32_e32 v3, s5 ; GFX8-NEXT: v_mov_b32_e32 v9, s3 -; GFX8-NEXT: v_mov_b32_e32 v3, s7 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc ; GFX8-NEXT: v_readfirstlane_b32 s0, v5 @@ -5923,49 +6401,66 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0 ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_movk_i32 s20, 0x7f ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 -; GFX9-NEXT: s_sub_i32 s8, 0x7f, 64 +; GFX9-NEXT: s_sub_i32 s21, s20, 64 +; GFX9-NEXT: s_sub_i32 s22, 64, s20 +; GFX9-NEXT: s_cmp_lt_u32 s20, 64 +; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s20, 0 +; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[2:3], s[16:17], s20 +; GFX9-NEXT: s_lshl_b64 s[8:9], s[18:19], s22 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX9-NEXT: s_ashr_i32 s3, s19, 31 -; GFX9-NEXT: s_ashr_i64 s[0:1], s[18:19], s8 -; GFX9-NEXT: s_add_u32 s0, s0, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 -; GFX9-NEXT: s_and_b32 s2, s2, 1 -; GFX9-NEXT: s_cmp_lg_u32 s2, 0 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 -; GFX9-NEXT: s_and_b32 s2, s2, 1 -; GFX9-NEXT: s_cmp_lg_u32 s2, 0 -; GFX9-NEXT: s_addc_u32 s2, s3, 0 -; GFX9-NEXT: s_cselect_b32 s10, 1, 0 -; GFX9-NEXT: s_and_b32 s10, s10, 1 -; GFX9-NEXT: s_brev_b32 s9, 1 -; GFX9-NEXT: s_cmp_lg_u32 s10, 0 +; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX9-NEXT: s_ashr_i32 s8, s19, 31 +; GFX9-NEXT: s_ashr_i64 s[0:1], s[18:19], s20 +; GFX9-NEXT: s_ashr_i64 s[10:11], s[18:19], s21 +; GFX9-NEXT: s_cmp_lg_u32 s23, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11] +; GFX9-NEXT: s_cmp_lg_u32 s24, 0 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX9-NEXT: s_cmp_lg_u32 s23, 0 +; GFX9-NEXT: s_mov_b32 s9, s8 +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] +; GFX9-NEXT: s_add_u32 s2, s2, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_and_b32 s8, s8, 1 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 +; GFX9-NEXT: s_addc_u32 s3, s3, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_and_b32 s8, s8, 1 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 +; GFX9-NEXT: s_addc_u32 s0, s0, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX9-NEXT: s_addc_u32 s3, s3, s9 +; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: s_brev_b32 s23, 1 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX9-NEXT: s_addc_u32 s1, s1, s23 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s2 +; GFX9-NEXT: v_mov_b32_e32 v3, s16 ; GFX9-NEXT: s_sub_u32 s0, s4, s12 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: s_cselect_b32 s1, 1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: s_subb_u32 s1, s5, s13 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 +; GFX9-NEXT: v_mov_b32_e32 v2, s3 ; GFX9-NEXT: v_mov_b32_e32 v4, s17 -; GFX9-NEXT: v_mov_b32_e32 v3, s16 ; GFX9-NEXT: s_subb_u32 s2, s6, s14 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc -; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v2, s18 ; GFX9-NEXT: v_mov_b32_e32 v3, s19 ; GFX9-NEXT: s_and_b32 s3, s3, 1 @@ -5993,18 +6488,33 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] ; GFX9-NEXT: s_and_b32 s4, 1, s6 +; GFX9-NEXT: s_cmp_lt_u32 s20, 64 +; GFX9-NEXT: s_cselect_b32 s12, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s20, 0 +; GFX9-NEXT: s_cselect_b32 s13, 1, 0 +; GFX9-NEXT: s_lshr_b64 s[6:7], s[0:1], s20 +; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s22 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 -; GFX9-NEXT: s_ashr_i32 s7, s3, 31 -; GFX9-NEXT: s_ashr_i64 s[4:5], s[2:3], s8 -; GFX9-NEXT: s_add_u32 s4, s4, 0 -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 -; GFX9-NEXT: s_and_b32 s6, s6, 1 -; GFX9-NEXT: s_cmp_lg_u32 s6, 0 -; GFX9-NEXT: s_addc_u32 s5, s5, 0 -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 -; GFX9-NEXT: s_and_b32 s6, s6, 1 -; GFX9-NEXT: s_cmp_lg_u32 s6, 0 -; GFX9-NEXT: s_addc_u32 s6, s7, 0 +; GFX9-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] +; GFX9-NEXT: s_ashr_i32 s8, s3, 31 +; GFX9-NEXT: s_ashr_i64 s[4:5], s[2:3], s20 +; GFX9-NEXT: s_ashr_i64 s[10:11], s[2:3], s21 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11] +; GFX9-NEXT: s_cmp_lg_u32 s13, 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], s[0:1], s[6:7] +; GFX9-NEXT: s_mov_b32 s9, s8 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] +; GFX9-NEXT: s_add_u32 s6, s6, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_and_b32 s8, s8, 1 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 +; GFX9-NEXT: s_addc_u32 s7, s7, 0 +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_and_b32 s8, s8, 1 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 +; GFX9-NEXT: s_addc_u32 s4, s4, 0 ; GFX9-NEXT: s_cselect_b32 s8, 1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 @@ -6013,16 +6523,16 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_mov_b32_e32 v3, s0 ; GFX9-NEXT: v_mov_b32_e32 v8, s1 -; GFX9-NEXT: s_addc_u32 s7, s7, s9 -; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: s_addc_u32 s5, s5, s23 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s7 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc +; GFX9-NEXT: v_mov_b32_e32 v2, s4 ; GFX9-NEXT: v_mov_b32_e32 v8, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s5 ; GFX9-NEXT: v_mov_b32_e32 v9, s3 -; GFX9-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc ; GFX9-NEXT: v_readfirstlane_b32 s0, v5 @@ -6045,7 +6555,6 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX10-NEXT: s_cselect_b32 s18, 1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1] ; GFX10-NEXT: s_and_b32 s18, s18, 1 -; GFX10-NEXT: v_cmp_gt_u64_e64 s1, s[8:9], 0 ; GFX10-NEXT: s_cmp_lg_u32 s18, 0 ; GFX10-NEXT: s_subb_u32 s18, s2, s10 ; GFX10-NEXT: s_cselect_b32 s19, 1, 0 @@ -6055,108 +6564,141 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> ; GFX10-NEXT: s_subb_u32 s19, s3, s11 ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3] ; GFX10-NEXT: s_cmp_eq_u64 s[18:19], s[2:3] -; GFX10-NEXT: v_mov_b32_e32 v3, s19 +; GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 0 ; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: s_and_b32 s0, 1, s20 ; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0 +; GFX10-NEXT: s_movk_i32 s20, 0x7f +; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2 +; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 0 +; GFX10-NEXT: s_and_b32 s1, 1, s1 +; GFX10-NEXT: s_sub_i32 s21, s20, 64 +; GFX10-NEXT: s_sub_i32 s22, 64, s20 +; GFX10-NEXT: s_cmp_lt_u32 s20, 64 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 -; GFX10-NEXT: s_ashr_i32 s3, s19, 31 -; GFX10-NEXT: s_and_b32 s0, 1, s0 +; GFX10-NEXT: s_cselect_b32 s23, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s20, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2 +; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[2:3], s[16:17], s20 +; GFX10-NEXT: s_lshl_b64 s[8:9], s[18:19], s22 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 -; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[10:11], 0 -; GFX10-NEXT: s_sub_i32 s10, 0x7f, 64 -; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 -; GFX10-NEXT: s_brev_b32 s11, 1 -; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1 -; GFX10-NEXT: s_ashr_i64 s[0:1], s[18:19], s10 -; GFX10-NEXT: s_add_u32 s0, s0, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo -; GFX10-NEXT: s_and_b32 s2, s2, 1 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 +; GFX10-NEXT: s_ashr_i32 s10, s19, 31 +; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] +; GFX10-NEXT: s_ashr_i64 s[0:1], s[18:19], s20 +; GFX10-NEXT: s_ashr_i64 s[8:9], s[18:19], s21 +; GFX10-NEXT: s_cmp_lg_u32 s23, 0 +; GFX10-NEXT: s_mov_b32 s11, s10 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[8:9] +; GFX10-NEXT: s_cmp_lg_u32 s24, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo +; GFX10-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX10-NEXT: s_cmp_lg_u32 s23, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, s17 -; GFX10-NEXT: s_cmp_lg_u32 s2, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11] +; GFX10-NEXT: s_add_u32 s2, s2, 0 +; GFX10-NEXT: s_cselect_b32 s8, 1, 0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 -; GFX10-NEXT: s_addc_u32 s1, s1, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, s16 -; GFX10-NEXT: s_and_b32 s2, s2, 1 -; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_cmp_lg_u32 s2, 0 -; GFX10-NEXT: s_addc_u32 s2, s3, 0 +; GFX10-NEXT: s_cmp_lg_u32 s8, 0 +; GFX10-NEXT: s_brev_b32 s23, 1 +; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_cselect_b32 s8, 1, 0 -; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: s_and_b32 s8, s8, 1 +; GFX10-NEXT: v_mov_b32_e32 v3, s19 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 -; GFX10-NEXT: s_addc_u32 s3, s3, s11 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo -; GFX10-NEXT: s_sub_u32 s0, s4, s12 +; GFX10-NEXT: s_addc_u32 s0, s0, 0 ; GFX10-NEXT: s_cselect_b32 s8, 1, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s1, vcc_lo +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: s_and_b32 s8, s8, 1 -; GFX10-NEXT: v_mov_b32_e32 v2, s18 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo -; GFX10-NEXT: s_subb_u32 s1, s5, s13 +; GFX10-NEXT: s_addc_u32 s1, s1, s23 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s2, vcc_lo +; GFX10-NEXT: s_sub_u32 s2, s4, s12 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s3, vcc_lo +; GFX10-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s1, vcc_lo +; GFX10-NEXT: s_and_b32 s3, s3, 1 +; GFX10-NEXT: v_mov_b32_e32 v2, s18 +; GFX10-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10-NEXT: s_subb_u32 s3, s5, s13 ; GFX10-NEXT: s_cselect_b32 s8, 1, 0 -; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5] +; GFX10-NEXT: v_cmp_lt_u64_e64 s1, s[2:3], s[4:5] ; GFX10-NEXT: s_and_b32 s8, s8, 1 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s0, vcc_lo ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 -; GFX10-NEXT: v_cmp_gt_u64_e64 s3, s[12:13], 0 ; GFX10-NEXT: s_subb_u32 s8, s6, s14 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1 ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: v_mov_b32_e32 v7, s8 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: s_subb_u32 s9, s7, s15 ; GFX10-NEXT: s_cmp_eq_u64 s[8:9], s[6:7] -; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[8:9], s[6:7] -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[8:9], s[6:7] +; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, s9 -; GFX10-NEXT: s_and_b32 s2, 1, s2 +; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0 -; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 -; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 -; GFX10-NEXT: s_ashr_i32 s5, s9, 31 -; GFX10-NEXT: s_and_b32 s4, 1, s2 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 +; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[12:13], 0 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s1 +; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_and_b32 s16, 1, s1 +; GFX10-NEXT: s_cmp_lt_u32 s20, 64 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s3 -; GFX10-NEXT: v_cmp_gt_i64_e64 s3, s[14:15], 0 -; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s3 -; GFX10-NEXT: s_ashr_i64 s[2:3], s[8:9], s10 -; GFX10-NEXT: s_add_u32 s2, s2, 0 -; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 +; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[14:15], 0 +; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s20, 0 +; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s16 +; GFX10-NEXT: s_cselect_b32 s12, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[4:5], s[2:3], s20 +; GFX10-NEXT: s_lshl_b64 s[6:7], s[8:9], s22 +; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 +; GFX10-NEXT: s_ashr_i32 s10, s9, 31 +; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; GFX10-NEXT: s_ashr_i64 s[0:1], s[8:9], s20 +; GFX10-NEXT: s_ashr_i64 s[6:7], s[8:9], s21 +; GFX10-NEXT: s_cmp_lg_u32 s17, 0 +; GFX10-NEXT: s_mov_b32 s11, s10 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] +; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo +; GFX10-NEXT: s_cselect_b64 s[4:5], s[2:3], s[4:5] +; GFX10-NEXT: s_cmp_lg_u32 s17, 0 +; GFX10-NEXT: v_mov_b32_e32 v6, s3 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11] +; GFX10-NEXT: s_add_u32 s4, s4, 0 +; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4 ; GFX10-NEXT: s_and_b32 s6, s6, 1 -; GFX10-NEXT: v_mov_b32_e32 v6, s1 +; GFX10-NEXT: v_mov_b32_e32 v5, s2 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0 -; GFX10-NEXT: s_addc_u32 s3, s3, 0 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 -; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4 -; GFX10-NEXT: s_and_b32 s4, s4, 1 -; GFX10-NEXT: v_mov_b32_e32 v5, s0 -; GFX10-NEXT: s_cmp_lg_u32 s4, 0 -; GFX10-NEXT: v_readfirstlane_b32 s0, v0 -; GFX10-NEXT: v_and_b32_e32 v4, 1, v4 -; GFX10-NEXT: s_addc_u32 s4, s5, 0 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: s_addc_u32 s5, s5, 0 ; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: v_and_b32_e32 v4, 1, v4 ; GFX10-NEXT: s_and_b32 s6, s6, 1 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-NEXT: s_cmp_lg_u32 s6, 0 +; GFX10-NEXT: s_addc_u32 s0, s0, 0 +; GFX10-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: s_and_b32 s6, s6, 1 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0 -; GFX10-NEXT: s_addc_u32 s1, s5, s11 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s2, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, s3, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s4, vcc_lo +; GFX10-NEXT: s_addc_u32 s1, s1, s23 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, s5, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v8, s1, vcc_lo +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1 -; GFX10-NEXT: v_readfirstlane_b32 s2, v2 -; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_readfirstlane_b32 s6, v6 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll index 1aadea0..a51626c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll @@ -967,129 +967,129 @@ define i64 @v_udiv_i64_pow2k_denom(i64 %num) { ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0 ; CHECK-NEXT: s_movk_i32 s6, 0xf000 ; CHECK-NEXT: s_movk_i32 s7, 0x1000 -; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CHECK-NEXT: s_bfe_i32 s5, -1, 0x10000 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; CHECK-NEXT: v_mov_b32_e32 v3, s4 -; CHECK-NEXT: v_mov_b32_e32 v4, s5 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; CHECK-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2 -; CHECK-NEXT: v_trunc_f32_e32 v5, v5 -; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5 -; CHECK-NEXT: v_cvt_u32_f32_e32 v5, v5 +; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; CHECK-NEXT: v_trunc_f32_e32 v3, v3 +; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 +; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 -; CHECK-NEXT: v_mul_lo_u32 v6, s6, v5 -; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, -1, v2 -; CHECK-NEXT: v_mul_hi_u32 v9, s6, v2 -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; CHECK-NEXT: v_mul_lo_u32 v8, v5, v7 -; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7 -; CHECK-NEXT: v_mul_hi_u32 v7, v5, v7 -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; CHECK-NEXT: v_mul_lo_u32 v9, v2, v6 -; CHECK-NEXT: v_mul_lo_u32 v11, v5, v6 -; CHECK-NEXT: v_mul_hi_u32 v12, v2, v6 -; CHECK-NEXT: v_mul_hi_u32 v6, v5, v6 -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9 +; CHECK-NEXT: v_mul_lo_u32 v4, s6, v3 +; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2 +; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 +; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5 +; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5 +; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4 +; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4 +; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 +; CHECK-NEXT: v_mul_hi_u32 v4, v3, v4 +; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v11, v7 -; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v12 -; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; CHECK-NEXT: v_add_i32_e32 v9, vcc, v11, v10 -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; CHECK-NEXT: v_addc_u32_e64 v7, s[4:5], v5, v6, vcc -; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v5, v6 -; CHECK-NEXT: v_mul_lo_u32 v6, s6, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, -1, v2 -; CHECK-NEXT: v_mul_hi_u32 v9, s6, v2 -; CHECK-NEXT: v_mul_lo_u32 v10, s6, v7 -; CHECK-NEXT: v_mul_lo_u32 v11, v7, v6 -; CHECK-NEXT: v_mul_hi_u32 v12, v2, v6 -; CHECK-NEXT: v_mul_hi_u32 v6, v7, v6 -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10 -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 -; CHECK-NEXT: v_mul_lo_u32 v9, v2, v8 -; CHECK-NEXT: v_mul_lo_u32 v10, v7, v8 -; CHECK-NEXT: v_mul_hi_u32 v13, v2, v8 -; CHECK-NEXT: v_mul_hi_u32 v7, v7, v8 -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v11, v9 -; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v10, v6 -; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v12 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v13 -; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 -; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v11 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v10 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc +; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4 +; CHECK-NEXT: v_mul_lo_u32 v4, s6, v2 +; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 +; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2 +; CHECK-NEXT: v_mul_lo_u32 v8, s6, v5 +; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4 +; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 +; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7 +; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6 +; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6 +; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6 +; CHECK-NEXT: v_mul_hi_u32 v5, v5, v6 +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v9, v7 +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v8, v4 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 -; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 -; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; CHECK-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; CHECK-NEXT: v_mul_lo_u32 v6, v1, v2 -; CHECK-NEXT: v_mul_hi_u32 v7, v0, v2 +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v11 +; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 +; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v9 +; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v6 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 +; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v5, v6 +; CHECK-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; CHECK-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; CHECK-NEXT: v_mul_lo_u32 v4, v1, v2 +; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, v0, v5 -; CHECK-NEXT: v_mul_lo_u32 v9, v1, v5 -; CHECK-NEXT: v_mul_hi_u32 v10, v0, v5 -; CHECK-NEXT: v_mul_hi_u32 v5, v1, v5 -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2 -; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; CHECK-NEXT: v_mul_lo_u32 v6, v0, v3 +; CHECK-NEXT: v_mul_lo_u32 v7, v1, v3 +; CHECK-NEXT: v_mul_hi_u32 v8, v0, v3 +; CHECK-NEXT: v_mul_hi_u32 v3, v1, v3 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v10 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2 ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CHECK-NEXT: v_mul_lo_u32 v7, s7, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, 0, v2 -; CHECK-NEXT: v_mul_hi_u32 v9, s7, v2 -; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; CHECK-NEXT: v_mul_lo_u32 v6, s7, v5 -; CHECK-NEXT: v_add_i32_e32 v10, vcc, 1, v2 -; CHECK-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; CHECK-NEXT: v_add_i32_e32 v8, vcc, 1, v10 -; CHECK-NEXT: v_addc_u32_e32 v12, vcc, 0, v11, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 -; CHECK-NEXT: v_subb_u32_e64 v7, s[4:5], v1, v6, vcc -; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v6 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2 +; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2 +; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2 +; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4 +; CHECK-NEXT: v_mul_lo_u32 v4, s7, v3 +; CHECK-NEXT: v_add_i32_e32 v8, vcc, 1, v2 +; CHECK-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v8 +; CHECK-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 +; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v4, vcc +; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v4 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0 -; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] -; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v7 -; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[4:5] +; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] +; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc +; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 +; CHECK-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc ; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s7, v0 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v10, v8, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc -; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v6, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; CHECK-NEXT: s_setpc_b64 s[30:31] %result = udiv i64 %num, 4096 ret i64 %result @@ -1099,9 +1099,9 @@ define <2 x i64> @v_udiv_v2i64_pow2k_denom(<2 x i64> %num) { ; GISEL-LABEL: v_udiv_v2i64_pow2k_denom: ; GISEL: ; %bb.0: ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: s_movk_i32 s12, 0x1000 -; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s12 -; GISEL-NEXT: s_sub_u32 s8, 0, s12 +; GISEL-NEXT: s_movk_i32 s10, 0x1000 +; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s10 +; GISEL-NEXT: s_sub_u32 s8, 0, s10 ; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; GISEL-NEXT: v_mov_b32_e32 v6, v4 @@ -1112,12 +1112,10 @@ define <2 x i64> @v_udiv_v2i64_pow2k_denom(<2 x i64> %num) { ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v6 ; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, 0 -; GISEL-NEXT: s_bfe_i32 s10, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 -; GISEL-NEXT: s_sub_u32 s13, 0, s12 +; GISEL-NEXT: s_sub_u32 s11, 0, s10 ; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6 @@ -1130,12 +1128,12 @@ define <2 x i64> @v_udiv_v2i64_pow2k_denom(<2 x i64> %num) { ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_subb_u32 s6, 0, 0 -; GISEL-NEXT: v_mul_lo_u32 v8, s13, v6 +; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s8, v7 -; GISEL-NEXT: v_mul_lo_u32 v10, s13, v4 +; GISEL-NEXT: v_mul_lo_u32 v10, s11, v4 ; GISEL-NEXT: v_mul_lo_u32 v11, s6, v4 -; GISEL-NEXT: v_mul_hi_u32 v12, s13, v4 +; GISEL-NEXT: v_mul_hi_u32 v12, s11, v4 ; GISEL-NEXT: v_mul_lo_u32 v13, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v14, s9, v5 ; GISEL-NEXT: v_mul_hi_u32 v15, s8, v5 @@ -1187,175 +1185,177 @@ define <2 x i64> @v_udiv_v2i64_pow2k_denom(<2 x i64> %num) { ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; GISEL-NEXT: v_addc_u32_e64 v10, s[4:5], v6, v8, vcc -; GISEL-NEXT: v_mul_lo_u32 v11, s13, v4 -; GISEL-NEXT: v_mul_lo_u32 v12, s6, v4 -; GISEL-NEXT: v_mul_hi_u32 v14, s13, v4 +; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 +; GISEL-NEXT: v_mul_lo_u32 v8, s11, v4 +; GISEL-NEXT: v_mul_lo_u32 v11, s6, v4 +; GISEL-NEXT: v_mul_hi_u32 v12, s11, v4 ; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v13 ; GISEL-NEXT: v_addc_u32_e64 v13, s[6:7], v7, v9, s[4:5] -; GISEL-NEXT: v_mul_lo_u32 v15, s8, v5 -; GISEL-NEXT: v_mul_lo_u32 v16, s9, v5 -; GISEL-NEXT: v_mul_hi_u32 v17, s8, v5 -; GISEL-NEXT: v_mul_lo_u32 v18, s8, v13 -; GISEL-NEXT: v_mul_lo_u32 v19, v13, v15 -; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v18 -; GISEL-NEXT: v_mul_hi_u32 v18, v5, v15 -; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v17 -; GISEL-NEXT: v_mul_lo_u32 v17, v5, v16 -; GISEL-NEXT: v_add_i32_e64 v17, s[6:7], v19, v17 -; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v17, s[6:7], v17, v18 -; GISEL-NEXT: v_mul_lo_u32 v17, s13, v10 -; GISEL-NEXT: v_mul_lo_u32 v18, v10, v11 -; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v12, v17 -; GISEL-NEXT: v_mul_hi_u32 v17, v4, v11 -; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v12, v14 -; GISEL-NEXT: v_mul_lo_u32 v14, v4, v12 -; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v18, v14 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v14, v17 -; GISEL-NEXT: v_mov_b32_e32 v14, s10 -; GISEL-NEXT: v_mov_b32_e32 v17, s11 -; GISEL-NEXT: s_bfe_i32 s13, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s14, -1, 0x10000 -; GISEL-NEXT: v_add_i32_e64 v6, s[10:11], v6, v8 -; GISEL-NEXT: v_mov_b32_e32 v8, s13 -; GISEL-NEXT: v_add_i32_e64 v7, s[10:11], v7, v9 -; GISEL-NEXT: v_mul_hi_u32 v9, v10, v11 -; GISEL-NEXT: v_mul_hi_u32 v11, v13, v15 +; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v7, v9 +; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5 +; GISEL-NEXT: v_mul_lo_u32 v14, s9, v5 +; GISEL-NEXT: v_mul_hi_u32 v15, s8, v5 +; GISEL-NEXT: v_mul_lo_u32 v16, s11, v10 +; GISEL-NEXT: v_mul_lo_u32 v17, v10, v8 +; GISEL-NEXT: v_mul_hi_u32 v18, v4, v8 +; GISEL-NEXT: v_mul_hi_u32 v8, v10, v8 +; GISEL-NEXT: v_mul_lo_u32 v19, s8, v13 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 +; GISEL-NEXT: v_mul_lo_u32 v16, v13, v9 +; GISEL-NEXT: v_add_i32_e64 v14, s[6:7], v14, v19 +; GISEL-NEXT: v_mul_hi_u32 v19, v5, v9 +; GISEL-NEXT: v_mul_hi_u32 v9, v13, v9 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v14, v15 +; GISEL-NEXT: v_mul_lo_u32 v14, v4, v11 +; GISEL-NEXT: v_mul_lo_u32 v15, v5, v12 +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v16, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v15, v19 +; GISEL-NEXT: v_mul_lo_u32 v15, v10, v11 +; GISEL-NEXT: v_mul_hi_u32 v19, v4, v11 +; GISEL-NEXT: v_mul_hi_u32 v10, v10, v11 +; GISEL-NEXT: v_mul_lo_u32 v11, v13, v12 +; GISEL-NEXT: v_mul_hi_u32 v13, v13, v12 +; GISEL-NEXT: v_mul_hi_u32 v12, v5, v12 +; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v17, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v8, s[8:9], v15, v8 ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v15, s[8:9], v18, v15 -; GISEL-NEXT: v_mul_lo_u32 v18, v10, v12 -; GISEL-NEXT: v_mul_hi_u32 v10, v10, v12 -; GISEL-NEXT: v_mul_hi_u32 v12, v4, v12 -; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v18, v9 +; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v11, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v14, v18 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v8, s[8:9], v8, v19 ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v9, v12 -; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v18, v12 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 -; GISEL-NEXT: v_mul_lo_u32 v19, v13, v16 -; GISEL-NEXT: v_mul_hi_u32 v13, v13, v16 -; GISEL-NEXT: v_mul_hi_u32 v16, v5, v16 -; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v19, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 -; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v19, v16 -; GISEL-NEXT: v_mov_b32_e32 v19, s14 -; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v15 -; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v12, v15 -; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v16, v18 +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v14, s[6:7], v17, v14 +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v15, v18 +; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v19 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; GISEL-NEXT: v_add_i32_e64 v8, s[6:7], v8, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v16 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v15, v12 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v14 ; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v10, v12 -; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v13, v15 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v13, v11 ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc -; GISEL-NEXT: v_addc_u32_e64 v7, vcc, v7, v12, s[4:5] -; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; GISEL-NEXT: v_addc_u32_e64 v7, vcc, v7, v11, s[4:5] +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc -; GISEL-NEXT: v_mul_lo_u32 v9, v3, v4 +; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4 ; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4 -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v11 +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc -; GISEL-NEXT: v_mul_lo_u32 v11, v1, v5 -; GISEL-NEXT: v_mul_hi_u32 v12, v0, v5 +; GISEL-NEXT: v_mul_lo_u32 v9, v1, v5 +; GISEL-NEXT: v_mul_hi_u32 v11, v0, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5 -; GISEL-NEXT: v_mul_lo_u32 v13, v2, v6 -; GISEL-NEXT: v_mul_lo_u32 v15, v3, v6 -; GISEL-NEXT: v_mul_hi_u32 v16, v2, v6 +; GISEL-NEXT: v_mul_lo_u32 v12, v2, v6 +; GISEL-NEXT: v_mul_lo_u32 v13, v3, v6 +; GISEL-NEXT: v_mul_hi_u32 v14, v2, v6 ; GISEL-NEXT: v_mul_hi_u32 v6, v3, v6 -; GISEL-NEXT: v_mul_lo_u32 v18, v0, v7 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GISEL-NEXT: v_mul_lo_u32 v11, v1, v7 -; GISEL-NEXT: v_mul_hi_u32 v12, v0, v7 +; GISEL-NEXT: v_mul_lo_u32 v15, v0, v7 +; GISEL-NEXT: v_mul_lo_u32 v16, v1, v7 +; GISEL-NEXT: v_mul_hi_u32 v17, v0, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7 -; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v15, v4 -; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 -; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 -; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v16 -; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v12 +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v13, v9 -; GISEL-NEXT: v_add_i32_e32 v10, vcc, v15, v10 -; GISEL-NEXT: v_add_i32_e32 v13, vcc, v18, v16 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v13, v4 +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v16, v5 +; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GISEL-NEXT: v_mul_lo_u32 v10, s12, v4 -; GISEL-NEXT: v_mul_lo_u32 v13, 0, v4 -; GISEL-NEXT: v_mul_hi_u32 v15, s12, v4 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GISEL-NEXT: v_mul_lo_u32 v12, s12, v5 -; GISEL-NEXT: v_mul_lo_u32 v16, 0, v5 -; GISEL-NEXT: v_mul_hi_u32 v18, s12, v5 -; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11 -; GISEL-NEXT: v_mul_lo_u32 v9, s12, v6 -; GISEL-NEXT: v_mul_lo_u32 v11, s12, v7 -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v13, v9 +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v17 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v15, v9 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v16, v11 -; GISEL-NEXT: v_add_i32_e32 v13, vcc, 1, v4 +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8 +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GISEL-NEXT: v_mul_lo_u32 v10, s10, v4 +; GISEL-NEXT: v_mul_lo_u32 v12, 0, v4 +; GISEL-NEXT: v_mul_hi_u32 v13, s10, v4 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9 +; GISEL-NEXT: v_mul_lo_u32 v11, s10, v5 +; GISEL-NEXT: v_mul_lo_u32 v14, 0, v5 +; GISEL-NEXT: v_mul_hi_u32 v15, s10, v5 +; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8 +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 +; GISEL-NEXT: v_mul_lo_u32 v8, s10, v6 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v4 ; GISEL-NEXT: v_addc_u32_e32 v16, vcc, 0, v6, vcc -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; GISEL-NEXT: v_add_i32_e32 v15, vcc, 1, v5 -; GISEL-NEXT: v_addc_u32_e32 v18, vcc, 0, v7, vcc +; GISEL-NEXT: v_mul_lo_u32 v17, s10, v7 +; GISEL-NEXT: v_add_i32_e32 v18, vcc, 1, v5 +; GISEL-NEXT: v_addc_u32_e32 v19, vcc, 0, v7, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; GISEL-NEXT: v_add_i32_e32 v12, vcc, v14, v17 +; GISEL-NEXT: v_add_i32_e32 v14, vcc, 1, v9 +; GISEL-NEXT: v_addc_u32_e32 v17, vcc, 0, v16, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v13 +; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15 +; GISEL-NEXT: v_add_i32_e32 v13, vcc, 1, v18 +; GISEL-NEXT: v_addc_u32_e32 v15, vcc, 0, v19, vcc ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v10 -; GISEL-NEXT: v_subb_u32_e64 v10, s[4:5], v3, v9, vcc -; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v9 -; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s12, v2 -; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] -; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v12 -; GISEL-NEXT: v_subb_u32_e64 v12, s[6:7], v1, v11, s[4:5] -; GISEL-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v11 +; GISEL-NEXT: v_subb_u32_e64 v10, s[4:5], v3, v8, vcc +; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v8 +; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s10, v2 +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v11 +; GISEL-NEXT: v_subb_u32_e64 v11, s[6:7], v1, v12, s[4:5] +; GISEL-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v12 +; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], 0, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[6:7] ; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v10 -; GISEL-NEXT: v_add_i32_e64 v10, s[8:9], 1, v13 -; GISEL-NEXT: v_addc_u32_e64 v11, s[8:9], 0, v16, s[8:9] -; GISEL-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7] -; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], s12, v0 -; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7] -; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v12 -; GISEL-NEXT: v_cndmask_b32_e64 v9, v14, v9, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], 1, v15 -; GISEL-NEXT: v_addc_u32_e64 v14, s[6:7], 0, v18, s[6:7] +; GISEL-NEXT: v_cmp_le_u32_e64 s[8:9], s10, v0 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[8:9] ; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v8, v12, v8, s[6:7] +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v11 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; GISEL-NEXT: v_subbrev_u32_e64 v1, vcc, 0, v1, s[4:5] -; GISEL-NEXT: v_subrev_i32_e32 v2, vcc, s12, v2 +; GISEL-NEXT: v_subrev_i32_e32 v2, vcc, s10, v2 ; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s12, v2 +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s10, v2 ; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0 +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v11 +; GISEL-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc +; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, s10, v0 ; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s10, v0 ; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; GISEL-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GISEL-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GISEL-NEXT: v_cndmask_b32_e32 v1, v13, v10, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v14, vcc ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 -; GISEL-NEXT: v_cndmask_b32_e64 v0, v15, v12, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e32 v3, v16, v11, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v0, v18, v13, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e32 v3, v16, v17, vcc ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v1, vcc -; GISEL-NEXT: v_cndmask_b32_e64 v1, v18, v14, s[4:5] -; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v1, v19, v15, s[4:5] +; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc @@ -1367,11 +1367,7 @@ define <2 x i64> @v_udiv_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x1000 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; CGP-NEXT: s_movk_i32 s8, 0xf000 -; CGP-NEXT: s_movk_i32 s12, 0x1000 -; CGP-NEXT: s_bfe_i32 s10, -1, 0x10000 -; CGP-NEXT: s_bfe_i32 s11, -1, 0x10000 -; CGP-NEXT: s_bfe_i32 s13, -1, 0x10000 -; CGP-NEXT: s_bfe_i32 s14, -1, 0x10000 +; CGP-NEXT: s_movk_i32 s10, 0x1000 ; CGP-NEXT: v_mov_b32_e32 v6, v4 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5 @@ -1445,173 +1441,177 @@ define <2 x i64> @v_udiv_v2i64_pow2k_denom(<2 x i64> %num) { ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v6, v8, vcc -; CGP-NEXT: v_mul_lo_u32 v11, s8, v4 -; CGP-NEXT: v_mul_lo_u32 v12, -1, v4 -; CGP-NEXT: v_mul_hi_u32 v14, s8, v4 +; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 +; CGP-NEXT: v_mul_lo_u32 v8, s8, v4 +; CGP-NEXT: v_mul_lo_u32 v11, -1, v4 +; CGP-NEXT: v_mul_hi_u32 v12, s8, v4 ; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v5, v13 ; CGP-NEXT: v_addc_u32_e64 v13, s[6:7], v7, v9, s[4:5] -; CGP-NEXT: v_mul_lo_u32 v15, s8, v5 -; CGP-NEXT: v_mul_lo_u32 v16, -1, v5 -; CGP-NEXT: v_mul_hi_u32 v17, s8, v5 -; CGP-NEXT: v_mul_lo_u32 v18, s8, v13 -; CGP-NEXT: v_mul_lo_u32 v19, v13, v15 -; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v18 -; CGP-NEXT: v_mul_hi_u32 v18, v5, v15 -; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v17 -; CGP-NEXT: v_mul_lo_u32 v17, v5, v16 -; CGP-NEXT: v_add_i32_e64 v17, s[6:7], v19, v17 -; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v17, s[6:7], v17, v18 -; CGP-NEXT: v_mul_lo_u32 v17, s8, v10 -; CGP-NEXT: v_mul_lo_u32 v18, v10, v11 -; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v12, v17 -; CGP-NEXT: v_mul_hi_u32 v17, v4, v11 -; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v12, v14 -; CGP-NEXT: v_mul_lo_u32 v14, v4, v12 -; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v18, v14 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v14, v17 -; CGP-NEXT: v_mov_b32_e32 v14, s10 -; CGP-NEXT: v_mov_b32_e32 v17, s11 -; CGP-NEXT: v_add_i32_e64 v6, s[10:11], v6, v8 -; CGP-NEXT: v_mov_b32_e32 v8, s13 -; CGP-NEXT: v_add_i32_e64 v7, s[10:11], v7, v9 -; CGP-NEXT: v_mul_hi_u32 v9, v10, v11 -; CGP-NEXT: v_mul_hi_u32 v11, v13, v15 +; CGP-NEXT: v_add_i32_e64 v7, s[6:7], v7, v9 +; CGP-NEXT: v_mul_lo_u32 v9, s8, v5 +; CGP-NEXT: v_mul_lo_u32 v14, -1, v5 +; CGP-NEXT: v_mul_hi_u32 v15, s8, v5 +; CGP-NEXT: v_mul_lo_u32 v16, s8, v10 +; CGP-NEXT: v_mul_lo_u32 v17, v10, v8 +; CGP-NEXT: v_mul_hi_u32 v18, v4, v8 +; CGP-NEXT: v_mul_hi_u32 v8, v10, v8 +; CGP-NEXT: v_mul_lo_u32 v19, s8, v13 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 +; CGP-NEXT: v_mul_lo_u32 v16, v13, v9 +; CGP-NEXT: v_add_i32_e64 v14, s[6:7], v14, v19 +; CGP-NEXT: v_mul_hi_u32 v19, v5, v9 +; CGP-NEXT: v_mul_hi_u32 v9, v13, v9 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v14, v15 +; CGP-NEXT: v_mul_lo_u32 v14, v4, v11 +; CGP-NEXT: v_mul_lo_u32 v15, v5, v12 +; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v16, v15 +; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v15, v19 +; CGP-NEXT: v_mul_lo_u32 v15, v10, v11 +; CGP-NEXT: v_mul_hi_u32 v19, v4, v11 +; CGP-NEXT: v_mul_hi_u32 v10, v10, v11 +; CGP-NEXT: v_mul_lo_u32 v11, v13, v12 +; CGP-NEXT: v_mul_hi_u32 v13, v13, v12 +; CGP-NEXT: v_mul_hi_u32 v12, v5, v12 +; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v17, v14 +; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] +; CGP-NEXT: v_add_i32_e64 v8, s[8:9], v15, v8 ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v15, s[8:9], v18, v15 -; CGP-NEXT: v_mul_lo_u32 v18, v10, v12 -; CGP-NEXT: v_mul_hi_u32 v10, v10, v12 -; CGP-NEXT: v_mul_hi_u32 v12, v4, v12 -; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v18, v9 +; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v11, v9 +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[8:9] +; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v14, v18 +; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[8:9] +; CGP-NEXT: v_add_i32_e64 v8, s[8:9], v8, v19 ; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v9, v12 -; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v18, v12 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 -; CGP-NEXT: v_mul_lo_u32 v19, v13, v16 -; CGP-NEXT: v_mul_hi_u32 v13, v13, v16 -; CGP-NEXT: v_mul_hi_u32 v16, v5, v16 -; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v19, v11 ; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 -; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v19, v16 -; CGP-NEXT: v_mov_b32_e32 v19, s14 -; CGP-NEXT: v_add_i32_e64 v9, s[6:7], v9, v15 -; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v18 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v12, v15 -; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v16, v18 +; CGP-NEXT: v_add_i32_e64 v9, s[6:7], v9, v12 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v14, s[6:7], v17, v14 +; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v15, v18 +; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v19 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; CGP-NEXT: v_add_i32_e64 v8, s[6:7], v8, v14 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v9, s[6:7], v9, v16 +; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v15, v12 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v14 ; CGP-NEXT: v_add_i32_e64 v10, s[6:7], v10, v12 -; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v13, v15 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v13, v11 ; CGP-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc -; CGP-NEXT: v_addc_u32_e64 v7, vcc, v7, v12, s[4:5] -; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; CGP-NEXT: v_addc_u32_e64 v7, vcc, v7, v11, s[4:5] +; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; CGP-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc -; CGP-NEXT: v_mul_lo_u32 v9, v3, v4 +; CGP-NEXT: v_mul_lo_u32 v8, v3, v4 ; CGP-NEXT: v_mul_hi_u32 v10, v2, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v3, v4 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v11 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc -; CGP-NEXT: v_mul_lo_u32 v11, v1, v5 -; CGP-NEXT: v_mul_hi_u32 v12, v0, v5 +; CGP-NEXT: v_mul_lo_u32 v9, v1, v5 +; CGP-NEXT: v_mul_hi_u32 v11, v0, v5 ; CGP-NEXT: v_mul_hi_u32 v5, v1, v5 -; CGP-NEXT: v_mul_lo_u32 v13, v2, v6 -; CGP-NEXT: v_mul_lo_u32 v15, v3, v6 -; CGP-NEXT: v_mul_hi_u32 v16, v2, v6 +; CGP-NEXT: v_mul_lo_u32 v12, v2, v6 +; CGP-NEXT: v_mul_lo_u32 v13, v3, v6 +; CGP-NEXT: v_mul_hi_u32 v14, v2, v6 ; CGP-NEXT: v_mul_hi_u32 v6, v3, v6 -; CGP-NEXT: v_mul_lo_u32 v18, v0, v7 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; CGP-NEXT: v_mul_lo_u32 v11, v1, v7 -; CGP-NEXT: v_mul_hi_u32 v12, v0, v7 +; CGP-NEXT: v_mul_lo_u32 v15, v0, v7 +; CGP-NEXT: v_mul_lo_u32 v16, v1, v7 +; CGP-NEXT: v_mul_hi_u32 v17, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 -; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 -; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v15, v4 -; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 -; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 -; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v16 -; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] -; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v12 +; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v9, vcc, v13, v9 -; CGP-NEXT: v_add_i32_e32 v10, vcc, v15, v10 -; CGP-NEXT: v_add_i32_e32 v13, vcc, v18, v16 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; CGP-NEXT: v_add_i32_e32 v4, vcc, v13, v4 +; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v15 +; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v16, v5 +; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v14 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v13 -; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; CGP-NEXT: v_mul_lo_u32 v10, s12, v4 -; CGP-NEXT: v_mul_lo_u32 v13, 0, v4 -; CGP-NEXT: v_mul_hi_u32 v15, s12, v4 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; CGP-NEXT: v_mul_lo_u32 v12, s12, v5 -; CGP-NEXT: v_mul_lo_u32 v16, 0, v5 -; CGP-NEXT: v_mul_hi_u32 v18, s12, v5 -; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v11 -; CGP-NEXT: v_mul_lo_u32 v9, s12, v6 -; CGP-NEXT: v_mul_lo_u32 v11, s12, v7 -; CGP-NEXT: v_add_i32_e32 v9, vcc, v13, v9 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v17 +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; CGP-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; CGP-NEXT: v_add_i32_e32 v9, vcc, v15, v9 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v16, v11 -; CGP-NEXT: v_add_i32_e32 v13, vcc, 1, v4 +; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8 +; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; CGP-NEXT: v_mul_lo_u32 v10, s10, v4 +; CGP-NEXT: v_mul_lo_u32 v12, 0, v4 +; CGP-NEXT: v_mul_hi_u32 v13, s10, v4 +; CGP-NEXT: v_add_i32_e32 v9, vcc, v11, v9 +; CGP-NEXT: v_mul_lo_u32 v11, s10, v5 +; CGP-NEXT: v_mul_lo_u32 v14, 0, v5 +; CGP-NEXT: v_mul_hi_u32 v15, s10, v5 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8 +; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 +; CGP-NEXT: v_mul_lo_u32 v8, s10, v6 +; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v4 ; CGP-NEXT: v_addc_u32_e32 v16, vcc, 0, v6, vcc -; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v15 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; CGP-NEXT: v_add_i32_e32 v15, vcc, 1, v5 -; CGP-NEXT: v_addc_u32_e32 v18, vcc, 0, v7, vcc +; CGP-NEXT: v_mul_lo_u32 v17, s10, v7 +; CGP-NEXT: v_add_i32_e32 v18, vcc, 1, v5 +; CGP-NEXT: v_addc_u32_e32 v19, vcc, 0, v7, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v17 +; CGP-NEXT: v_add_i32_e32 v14, vcc, 1, v9 +; CGP-NEXT: v_addc_u32_e32 v17, vcc, 0, v16, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v13 +; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15 +; CGP-NEXT: v_add_i32_e32 v13, vcc, 1, v18 +; CGP-NEXT: v_addc_u32_e32 v15, vcc, 0, v19, vcc ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v10 -; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v3, v9, vcc -; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v9 -; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s12, v2 -; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] -; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v12 -; CGP-NEXT: v_subb_u32_e64 v12, s[6:7], v1, v11, s[4:5] -; CGP-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v11 +; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v3, v8, vcc +; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v8 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s10, v2 +; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v11 +; CGP-NEXT: v_subb_u32_e64 v11, s[6:7], v1, v12, s[4:5] +; CGP-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v12 +; CGP-NEXT: v_cmp_le_u32_e64 s[6:7], 0, v10 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[6:7] ; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v10 -; CGP-NEXT: v_add_i32_e64 v10, s[8:9], 1, v13 -; CGP-NEXT: v_addc_u32_e64 v11, s[8:9], 0, v16, s[8:9] -; CGP-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7] -; CGP-NEXT: v_cmp_le_u32_e64 s[6:7], s12, v0 -; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7] -; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v12 -; CGP-NEXT: v_cndmask_b32_e64 v9, v14, v9, s[6:7] -; CGP-NEXT: v_add_i32_e64 v12, s[6:7], 1, v15 -; CGP-NEXT: v_addc_u32_e64 v14, s[6:7], 0, v18, s[6:7] +; CGP-NEXT: v_cmp_le_u32_e64 s[8:9], s10, v0 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[8:9] ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; CGP-NEXT: v_cndmask_b32_e64 v8, v12, v8, s[6:7] +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v11 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; CGP-NEXT: v_subbrev_u32_e64 v1, vcc, 0, v1, s[4:5] -; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s12, v2 +; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s10, v2 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: v_cmp_le_u32_e32 vcc, s12, v2 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, s10, v2 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0 +; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v11 +; CGP-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc +; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s10, v0 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CGP-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, s10, v0 ; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; CGP-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc +; CGP-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc +; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v1, v13, v10, vcc +; CGP-NEXT: v_cndmask_b32_e32 v1, v9, v14, vcc ; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 -; CGP-NEXT: v_cndmask_b32_e64 v0, v15, v12, s[4:5] -; CGP-NEXT: v_cndmask_b32_e32 v3, v16, v11, vcc +; CGP-NEXT: v_cndmask_b32_e64 v0, v18, v13, s[4:5] +; CGP-NEXT: v_cndmask_b32_e32 v3, v16, v17, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; CGP-NEXT: v_cndmask_b32_e32 v2, v4, v1, vcc -; CGP-NEXT: v_cndmask_b32_e64 v1, v18, v14, s[4:5] -; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9 +; CGP-NEXT: v_cndmask_b32_e64 v1, v19, v15, s[4:5] +; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v10 ; CGP-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc @@ -1628,129 +1628,129 @@ define i64 @v_udiv_i64_oddk_denom(i64 %num) { ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0 ; CHECK-NEXT: s_mov_b32 s6, 0xffed2705 ; CHECK-NEXT: s_mov_b32 s7, 0x12d8fb -; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CHECK-NEXT: s_bfe_i32 s5, -1, 0x10000 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; CHECK-NEXT: v_mov_b32_e32 v3, s4 -; CHECK-NEXT: v_mov_b32_e32 v4, s5 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; CHECK-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2 -; CHECK-NEXT: v_trunc_f32_e32 v5, v5 -; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5 -; CHECK-NEXT: v_cvt_u32_f32_e32 v5, v5 +; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; CHECK-NEXT: v_trunc_f32_e32 v3, v3 +; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 +; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 -; CHECK-NEXT: v_mul_lo_u32 v6, s6, v5 -; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, -1, v2 -; CHECK-NEXT: v_mul_hi_u32 v9, s6, v2 -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; CHECK-NEXT: v_mul_lo_u32 v8, v5, v7 -; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7 -; CHECK-NEXT: v_mul_hi_u32 v7, v5, v7 -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; CHECK-NEXT: v_mul_lo_u32 v9, v2, v6 -; CHECK-NEXT: v_mul_lo_u32 v11, v5, v6 -; CHECK-NEXT: v_mul_hi_u32 v12, v2, v6 -; CHECK-NEXT: v_mul_hi_u32 v6, v5, v6 -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9 +; CHECK-NEXT: v_mul_lo_u32 v4, s6, v3 +; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2 +; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 +; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5 +; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5 +; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4 +; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4 +; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 +; CHECK-NEXT: v_mul_hi_u32 v4, v3, v4 +; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v11, v7 -; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v12 -; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; CHECK-NEXT: v_add_i32_e32 v9, vcc, v11, v10 -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; CHECK-NEXT: v_addc_u32_e64 v7, s[4:5], v5, v6, vcc -; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v5, v6 -; CHECK-NEXT: v_mul_lo_u32 v6, s6, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, -1, v2 -; CHECK-NEXT: v_mul_hi_u32 v9, s6, v2 -; CHECK-NEXT: v_mul_lo_u32 v10, s6, v7 -; CHECK-NEXT: v_mul_lo_u32 v11, v7, v6 -; CHECK-NEXT: v_mul_hi_u32 v12, v2, v6 -; CHECK-NEXT: v_mul_hi_u32 v6, v7, v6 -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10 -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 -; CHECK-NEXT: v_mul_lo_u32 v9, v2, v8 -; CHECK-NEXT: v_mul_lo_u32 v10, v7, v8 -; CHECK-NEXT: v_mul_hi_u32 v13, v2, v8 -; CHECK-NEXT: v_mul_hi_u32 v7, v7, v8 -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v11, v9 -; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v10, v6 -; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v12 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v13 -; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 -; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v11 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v10 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc +; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4 +; CHECK-NEXT: v_mul_lo_u32 v4, s6, v2 +; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 +; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2 +; CHECK-NEXT: v_mul_lo_u32 v8, s6, v5 +; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4 +; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 +; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7 +; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6 +; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6 +; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6 +; CHECK-NEXT: v_mul_hi_u32 v5, v5, v6 +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v9, v7 +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v8, v4 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 -; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 -; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; CHECK-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; CHECK-NEXT: v_mul_lo_u32 v6, v1, v2 -; CHECK-NEXT: v_mul_hi_u32 v7, v0, v2 +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v11 +; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 +; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v9 +; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v6 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 +; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v5, v6 +; CHECK-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; CHECK-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; CHECK-NEXT: v_mul_lo_u32 v4, v1, v2 +; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, v0, v5 -; CHECK-NEXT: v_mul_lo_u32 v9, v1, v5 -; CHECK-NEXT: v_mul_hi_u32 v10, v0, v5 -; CHECK-NEXT: v_mul_hi_u32 v5, v1, v5 -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2 -; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; CHECK-NEXT: v_mul_lo_u32 v6, v0, v3 +; CHECK-NEXT: v_mul_lo_u32 v7, v1, v3 +; CHECK-NEXT: v_mul_hi_u32 v8, v0, v3 +; CHECK-NEXT: v_mul_hi_u32 v3, v1, v3 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v10 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2 ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CHECK-NEXT: v_mul_lo_u32 v7, s7, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, 0, v2 -; CHECK-NEXT: v_mul_hi_u32 v9, s7, v2 -; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; CHECK-NEXT: v_mul_lo_u32 v6, s7, v5 -; CHECK-NEXT: v_add_i32_e32 v10, vcc, 1, v2 -; CHECK-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; CHECK-NEXT: v_add_i32_e32 v8, vcc, 1, v10 -; CHECK-NEXT: v_addc_u32_e32 v12, vcc, 0, v11, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 -; CHECK-NEXT: v_subb_u32_e64 v7, s[4:5], v1, v6, vcc -; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v6 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2 +; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2 +; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2 +; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4 +; CHECK-NEXT: v_mul_lo_u32 v4, s7, v3 +; CHECK-NEXT: v_add_i32_e32 v8, vcc, 1, v2 +; CHECK-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v8 +; CHECK-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 +; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v4, vcc +; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v4 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0 -; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] -; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v7 -; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[4:5] +; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] +; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc +; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 +; CHECK-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc ; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s7, v0 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v10, v8, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc -; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v6, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; CHECK-NEXT: s_setpc_b64 s[30:31] %result = udiv i64 %num, 1235195 ret i64 %result @@ -1760,9 +1760,9 @@ define <2 x i64> @v_udiv_v2i64_oddk_denom(<2 x i64> %num) { ; GISEL-LABEL: v_udiv_v2i64_oddk_denom: ; GISEL: ; %bb.0: ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: s_mov_b32 s12, 0x12d8fb -; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s12 -; GISEL-NEXT: s_sub_u32 s8, 0, s12 +; GISEL-NEXT: s_mov_b32 s10, 0x12d8fb +; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s10 +; GISEL-NEXT: s_sub_u32 s8, 0, s10 ; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; GISEL-NEXT: v_mov_b32_e32 v6, v4 @@ -1773,12 +1773,10 @@ define <2 x i64> @v_udiv_v2i64_oddk_denom(<2 x i64> %num) { ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v6 ; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, 0 -; GISEL-NEXT: s_bfe_i32 s10, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 -; GISEL-NEXT: s_sub_u32 s13, 0, s12 +; GISEL-NEXT: s_sub_u32 s11, 0, s10 ; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6 @@ -1791,12 +1789,12 @@ define <2 x i64> @v_udiv_v2i64_oddk_denom(<2 x i64> %num) { ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_subb_u32 s6, 0, 0 -; GISEL-NEXT: v_mul_lo_u32 v8, s13, v6 +; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s8, v7 -; GISEL-NEXT: v_mul_lo_u32 v10, s13, v4 +; GISEL-NEXT: v_mul_lo_u32 v10, s11, v4 ; GISEL-NEXT: v_mul_lo_u32 v11, s6, v4 -; GISEL-NEXT: v_mul_hi_u32 v12, s13, v4 +; GISEL-NEXT: v_mul_hi_u32 v12, s11, v4 ; GISEL-NEXT: v_mul_lo_u32 v13, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v14, s9, v5 ; GISEL-NEXT: v_mul_hi_u32 v15, s8, v5 @@ -1848,175 +1846,177 @@ define <2 x i64> @v_udiv_v2i64_oddk_denom(<2 x i64> %num) { ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; GISEL-NEXT: v_addc_u32_e64 v10, s[4:5], v6, v8, vcc -; GISEL-NEXT: v_mul_lo_u32 v11, s13, v4 -; GISEL-NEXT: v_mul_lo_u32 v12, s6, v4 -; GISEL-NEXT: v_mul_hi_u32 v14, s13, v4 +; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 +; GISEL-NEXT: v_mul_lo_u32 v8, s11, v4 +; GISEL-NEXT: v_mul_lo_u32 v11, s6, v4 +; GISEL-NEXT: v_mul_hi_u32 v12, s11, v4 ; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v13 ; GISEL-NEXT: v_addc_u32_e64 v13, s[6:7], v7, v9, s[4:5] -; GISEL-NEXT: v_mul_lo_u32 v15, s8, v5 -; GISEL-NEXT: v_mul_lo_u32 v16, s9, v5 -; GISEL-NEXT: v_mul_hi_u32 v17, s8, v5 -; GISEL-NEXT: v_mul_lo_u32 v18, s8, v13 -; GISEL-NEXT: v_mul_lo_u32 v19, v13, v15 -; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v18 -; GISEL-NEXT: v_mul_hi_u32 v18, v5, v15 -; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v17 -; GISEL-NEXT: v_mul_lo_u32 v17, v5, v16 -; GISEL-NEXT: v_add_i32_e64 v17, s[6:7], v19, v17 -; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v17, s[6:7], v17, v18 -; GISEL-NEXT: v_mul_lo_u32 v17, s13, v10 -; GISEL-NEXT: v_mul_lo_u32 v18, v10, v11 -; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v12, v17 -; GISEL-NEXT: v_mul_hi_u32 v17, v4, v11 -; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v12, v14 -; GISEL-NEXT: v_mul_lo_u32 v14, v4, v12 -; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v18, v14 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v14, v17 -; GISEL-NEXT: v_mov_b32_e32 v14, s10 -; GISEL-NEXT: v_mov_b32_e32 v17, s11 -; GISEL-NEXT: s_bfe_i32 s13, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s14, -1, 0x10000 -; GISEL-NEXT: v_add_i32_e64 v6, s[10:11], v6, v8 -; GISEL-NEXT: v_mov_b32_e32 v8, s13 -; GISEL-NEXT: v_add_i32_e64 v7, s[10:11], v7, v9 -; GISEL-NEXT: v_mul_hi_u32 v9, v10, v11 -; GISEL-NEXT: v_mul_hi_u32 v11, v13, v15 +; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v7, v9 +; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5 +; GISEL-NEXT: v_mul_lo_u32 v14, s9, v5 +; GISEL-NEXT: v_mul_hi_u32 v15, s8, v5 +; GISEL-NEXT: v_mul_lo_u32 v16, s11, v10 +; GISEL-NEXT: v_mul_lo_u32 v17, v10, v8 +; GISEL-NEXT: v_mul_hi_u32 v18, v4, v8 +; GISEL-NEXT: v_mul_hi_u32 v8, v10, v8 +; GISEL-NEXT: v_mul_lo_u32 v19, s8, v13 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 +; GISEL-NEXT: v_mul_lo_u32 v16, v13, v9 +; GISEL-NEXT: v_add_i32_e64 v14, s[6:7], v14, v19 +; GISEL-NEXT: v_mul_hi_u32 v19, v5, v9 +; GISEL-NEXT: v_mul_hi_u32 v9, v13, v9 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v14, v15 +; GISEL-NEXT: v_mul_lo_u32 v14, v4, v11 +; GISEL-NEXT: v_mul_lo_u32 v15, v5, v12 +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v16, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v15, v19 +; GISEL-NEXT: v_mul_lo_u32 v15, v10, v11 +; GISEL-NEXT: v_mul_hi_u32 v19, v4, v11 +; GISEL-NEXT: v_mul_hi_u32 v10, v10, v11 +; GISEL-NEXT: v_mul_lo_u32 v11, v13, v12 +; GISEL-NEXT: v_mul_hi_u32 v13, v13, v12 +; GISEL-NEXT: v_mul_hi_u32 v12, v5, v12 +; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v17, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v8, s[8:9], v15, v8 ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v15, s[8:9], v18, v15 -; GISEL-NEXT: v_mul_lo_u32 v18, v10, v12 -; GISEL-NEXT: v_mul_hi_u32 v10, v10, v12 -; GISEL-NEXT: v_mul_hi_u32 v12, v4, v12 -; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v18, v9 +; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v11, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v14, v18 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v8, s[8:9], v8, v19 ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v9, v12 -; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v18, v12 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 -; GISEL-NEXT: v_mul_lo_u32 v19, v13, v16 -; GISEL-NEXT: v_mul_hi_u32 v13, v13, v16 -; GISEL-NEXT: v_mul_hi_u32 v16, v5, v16 -; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v19, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 -; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v19, v16 -; GISEL-NEXT: v_mov_b32_e32 v19, s14 -; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v15 -; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v12, v15 -; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v16, v18 +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v14, s[6:7], v17, v14 +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v15, v18 +; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v19 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; GISEL-NEXT: v_add_i32_e64 v8, s[6:7], v8, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v16 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v15, v12 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v14 ; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v10, v12 -; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v13, v15 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v13, v11 ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc -; GISEL-NEXT: v_addc_u32_e64 v7, vcc, v7, v12, s[4:5] -; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; GISEL-NEXT: v_addc_u32_e64 v7, vcc, v7, v11, s[4:5] +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc -; GISEL-NEXT: v_mul_lo_u32 v9, v3, v4 +; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4 ; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4 -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v11 +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc -; GISEL-NEXT: v_mul_lo_u32 v11, v1, v5 -; GISEL-NEXT: v_mul_hi_u32 v12, v0, v5 +; GISEL-NEXT: v_mul_lo_u32 v9, v1, v5 +; GISEL-NEXT: v_mul_hi_u32 v11, v0, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5 -; GISEL-NEXT: v_mul_lo_u32 v13, v2, v6 -; GISEL-NEXT: v_mul_lo_u32 v15, v3, v6 -; GISEL-NEXT: v_mul_hi_u32 v16, v2, v6 +; GISEL-NEXT: v_mul_lo_u32 v12, v2, v6 +; GISEL-NEXT: v_mul_lo_u32 v13, v3, v6 +; GISEL-NEXT: v_mul_hi_u32 v14, v2, v6 ; GISEL-NEXT: v_mul_hi_u32 v6, v3, v6 -; GISEL-NEXT: v_mul_lo_u32 v18, v0, v7 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GISEL-NEXT: v_mul_lo_u32 v11, v1, v7 -; GISEL-NEXT: v_mul_hi_u32 v12, v0, v7 +; GISEL-NEXT: v_mul_lo_u32 v15, v0, v7 +; GISEL-NEXT: v_mul_lo_u32 v16, v1, v7 +; GISEL-NEXT: v_mul_hi_u32 v17, v0, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7 -; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v15, v4 -; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 -; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 -; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v16 -; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v12 +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v13, v9 -; GISEL-NEXT: v_add_i32_e32 v10, vcc, v15, v10 -; GISEL-NEXT: v_add_i32_e32 v13, vcc, v18, v16 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v13, v4 +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v16, v5 +; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GISEL-NEXT: v_mul_lo_u32 v10, s12, v4 -; GISEL-NEXT: v_mul_lo_u32 v13, 0, v4 -; GISEL-NEXT: v_mul_hi_u32 v15, s12, v4 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GISEL-NEXT: v_mul_lo_u32 v12, s12, v5 -; GISEL-NEXT: v_mul_lo_u32 v16, 0, v5 -; GISEL-NEXT: v_mul_hi_u32 v18, s12, v5 -; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11 -; GISEL-NEXT: v_mul_lo_u32 v9, s12, v6 -; GISEL-NEXT: v_mul_lo_u32 v11, s12, v7 -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v13, v9 +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v17 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v15, v9 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v16, v11 -; GISEL-NEXT: v_add_i32_e32 v13, vcc, 1, v4 +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8 +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GISEL-NEXT: v_mul_lo_u32 v10, s10, v4 +; GISEL-NEXT: v_mul_lo_u32 v12, 0, v4 +; GISEL-NEXT: v_mul_hi_u32 v13, s10, v4 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9 +; GISEL-NEXT: v_mul_lo_u32 v11, s10, v5 +; GISEL-NEXT: v_mul_lo_u32 v14, 0, v5 +; GISEL-NEXT: v_mul_hi_u32 v15, s10, v5 +; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8 +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 +; GISEL-NEXT: v_mul_lo_u32 v8, s10, v6 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v4 ; GISEL-NEXT: v_addc_u32_e32 v16, vcc, 0, v6, vcc -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; GISEL-NEXT: v_add_i32_e32 v15, vcc, 1, v5 -; GISEL-NEXT: v_addc_u32_e32 v18, vcc, 0, v7, vcc +; GISEL-NEXT: v_mul_lo_u32 v17, s10, v7 +; GISEL-NEXT: v_add_i32_e32 v18, vcc, 1, v5 +; GISEL-NEXT: v_addc_u32_e32 v19, vcc, 0, v7, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; GISEL-NEXT: v_add_i32_e32 v12, vcc, v14, v17 +; GISEL-NEXT: v_add_i32_e32 v14, vcc, 1, v9 +; GISEL-NEXT: v_addc_u32_e32 v17, vcc, 0, v16, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v13 +; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15 +; GISEL-NEXT: v_add_i32_e32 v13, vcc, 1, v18 +; GISEL-NEXT: v_addc_u32_e32 v15, vcc, 0, v19, vcc ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v10 -; GISEL-NEXT: v_subb_u32_e64 v10, s[4:5], v3, v9, vcc -; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v9 -; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s12, v2 -; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] -; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v12 -; GISEL-NEXT: v_subb_u32_e64 v12, s[6:7], v1, v11, s[4:5] -; GISEL-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v11 +; GISEL-NEXT: v_subb_u32_e64 v10, s[4:5], v3, v8, vcc +; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v8 +; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s10, v2 +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v11 +; GISEL-NEXT: v_subb_u32_e64 v11, s[6:7], v1, v12, s[4:5] +; GISEL-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v12 +; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], 0, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[6:7] ; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v10 -; GISEL-NEXT: v_add_i32_e64 v10, s[8:9], 1, v13 -; GISEL-NEXT: v_addc_u32_e64 v11, s[8:9], 0, v16, s[8:9] -; GISEL-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7] -; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], s12, v0 -; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7] -; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v12 -; GISEL-NEXT: v_cndmask_b32_e64 v9, v14, v9, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], 1, v15 -; GISEL-NEXT: v_addc_u32_e64 v14, s[6:7], 0, v18, s[6:7] +; GISEL-NEXT: v_cmp_le_u32_e64 s[8:9], s10, v0 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[8:9] ; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v8, v12, v8, s[6:7] +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v11 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; GISEL-NEXT: v_subbrev_u32_e64 v1, vcc, 0, v1, s[4:5] -; GISEL-NEXT: v_subrev_i32_e32 v2, vcc, s12, v2 +; GISEL-NEXT: v_subrev_i32_e32 v2, vcc, s10, v2 ; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s12, v2 +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s10, v2 ; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0 +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v11 +; GISEL-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc +; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, s10, v0 ; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s10, v0 ; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; GISEL-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GISEL-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GISEL-NEXT: v_cndmask_b32_e32 v1, v13, v10, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v14, vcc ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 -; GISEL-NEXT: v_cndmask_b32_e64 v0, v15, v12, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e32 v3, v16, v11, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v0, v18, v13, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e32 v3, v16, v17, vcc ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v1, vcc -; GISEL-NEXT: v_cndmask_b32_e64 v1, v18, v14, s[4:5] -; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v1, v19, v15, s[4:5] +; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc @@ -2028,11 +2028,7 @@ define <2 x i64> @v_udiv_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; CGP-NEXT: s_mov_b32 s8, 0xffed2705 -; CGP-NEXT: s_mov_b32 s12, 0x12d8fb -; CGP-NEXT: s_bfe_i32 s10, -1, 0x10000 -; CGP-NEXT: s_bfe_i32 s11, -1, 0x10000 -; CGP-NEXT: s_bfe_i32 s13, -1, 0x10000 -; CGP-NEXT: s_bfe_i32 s14, -1, 0x10000 +; CGP-NEXT: s_mov_b32 s10, 0x12d8fb ; CGP-NEXT: v_mov_b32_e32 v6, v4 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5 @@ -2106,173 +2102,177 @@ define <2 x i64> @v_udiv_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v6, v8, vcc -; CGP-NEXT: v_mul_lo_u32 v11, s8, v4 -; CGP-NEXT: v_mul_lo_u32 v12, -1, v4 -; CGP-NEXT: v_mul_hi_u32 v14, s8, v4 +; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 +; CGP-NEXT: v_mul_lo_u32 v8, s8, v4 +; CGP-NEXT: v_mul_lo_u32 v11, -1, v4 +; CGP-NEXT: v_mul_hi_u32 v12, s8, v4 ; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v5, v13 ; CGP-NEXT: v_addc_u32_e64 v13, s[6:7], v7, v9, s[4:5] -; CGP-NEXT: v_mul_lo_u32 v15, s8, v5 -; CGP-NEXT: v_mul_lo_u32 v16, -1, v5 -; CGP-NEXT: v_mul_hi_u32 v17, s8, v5 -; CGP-NEXT: v_mul_lo_u32 v18, s8, v13 -; CGP-NEXT: v_mul_lo_u32 v19, v13, v15 -; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v18 -; CGP-NEXT: v_mul_hi_u32 v18, v5, v15 -; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v17 -; CGP-NEXT: v_mul_lo_u32 v17, v5, v16 -; CGP-NEXT: v_add_i32_e64 v17, s[6:7], v19, v17 -; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v17, s[6:7], v17, v18 -; CGP-NEXT: v_mul_lo_u32 v17, s8, v10 -; CGP-NEXT: v_mul_lo_u32 v18, v10, v11 -; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v12, v17 -; CGP-NEXT: v_mul_hi_u32 v17, v4, v11 -; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v12, v14 -; CGP-NEXT: v_mul_lo_u32 v14, v4, v12 -; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v18, v14 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v14, v17 -; CGP-NEXT: v_mov_b32_e32 v14, s10 -; CGP-NEXT: v_mov_b32_e32 v17, s11 -; CGP-NEXT: v_add_i32_e64 v6, s[10:11], v6, v8 -; CGP-NEXT: v_mov_b32_e32 v8, s13 -; CGP-NEXT: v_add_i32_e64 v7, s[10:11], v7, v9 -; CGP-NEXT: v_mul_hi_u32 v9, v10, v11 -; CGP-NEXT: v_mul_hi_u32 v11, v13, v15 +; CGP-NEXT: v_add_i32_e64 v7, s[6:7], v7, v9 +; CGP-NEXT: v_mul_lo_u32 v9, s8, v5 +; CGP-NEXT: v_mul_lo_u32 v14, -1, v5 +; CGP-NEXT: v_mul_hi_u32 v15, s8, v5 +; CGP-NEXT: v_mul_lo_u32 v16, s8, v10 +; CGP-NEXT: v_mul_lo_u32 v17, v10, v8 +; CGP-NEXT: v_mul_hi_u32 v18, v4, v8 +; CGP-NEXT: v_mul_hi_u32 v8, v10, v8 +; CGP-NEXT: v_mul_lo_u32 v19, s8, v13 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 +; CGP-NEXT: v_mul_lo_u32 v16, v13, v9 +; CGP-NEXT: v_add_i32_e64 v14, s[6:7], v14, v19 +; CGP-NEXT: v_mul_hi_u32 v19, v5, v9 +; CGP-NEXT: v_mul_hi_u32 v9, v13, v9 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v14, v15 +; CGP-NEXT: v_mul_lo_u32 v14, v4, v11 +; CGP-NEXT: v_mul_lo_u32 v15, v5, v12 +; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v16, v15 +; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v15, v19 +; CGP-NEXT: v_mul_lo_u32 v15, v10, v11 +; CGP-NEXT: v_mul_hi_u32 v19, v4, v11 +; CGP-NEXT: v_mul_hi_u32 v10, v10, v11 +; CGP-NEXT: v_mul_lo_u32 v11, v13, v12 +; CGP-NEXT: v_mul_hi_u32 v13, v13, v12 +; CGP-NEXT: v_mul_hi_u32 v12, v5, v12 +; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v17, v14 +; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] +; CGP-NEXT: v_add_i32_e64 v8, s[8:9], v15, v8 ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v15, s[8:9], v18, v15 -; CGP-NEXT: v_mul_lo_u32 v18, v10, v12 -; CGP-NEXT: v_mul_hi_u32 v10, v10, v12 -; CGP-NEXT: v_mul_hi_u32 v12, v4, v12 -; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v18, v9 +; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v11, v9 +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[8:9] +; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v14, v18 +; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[8:9] +; CGP-NEXT: v_add_i32_e64 v8, s[8:9], v8, v19 ; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v9, v12 -; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v18, v12 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 -; CGP-NEXT: v_mul_lo_u32 v19, v13, v16 -; CGP-NEXT: v_mul_hi_u32 v13, v13, v16 -; CGP-NEXT: v_mul_hi_u32 v16, v5, v16 -; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v19, v11 ; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 -; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v19, v16 -; CGP-NEXT: v_mov_b32_e32 v19, s14 -; CGP-NEXT: v_add_i32_e64 v9, s[6:7], v9, v15 -; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v18 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v12, v15 -; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v16, v18 +; CGP-NEXT: v_add_i32_e64 v9, s[6:7], v9, v12 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v14, s[6:7], v17, v14 +; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v15, v18 +; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v19 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; CGP-NEXT: v_add_i32_e64 v8, s[6:7], v8, v14 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v9, s[6:7], v9, v16 +; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v15, v12 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v14 ; CGP-NEXT: v_add_i32_e64 v10, s[6:7], v10, v12 -; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v13, v15 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v13, v11 ; CGP-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc -; CGP-NEXT: v_addc_u32_e64 v7, vcc, v7, v12, s[4:5] -; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; CGP-NEXT: v_addc_u32_e64 v7, vcc, v7, v11, s[4:5] +; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; CGP-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc -; CGP-NEXT: v_mul_lo_u32 v9, v3, v4 +; CGP-NEXT: v_mul_lo_u32 v8, v3, v4 ; CGP-NEXT: v_mul_hi_u32 v10, v2, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v3, v4 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v11 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc -; CGP-NEXT: v_mul_lo_u32 v11, v1, v5 -; CGP-NEXT: v_mul_hi_u32 v12, v0, v5 +; CGP-NEXT: v_mul_lo_u32 v9, v1, v5 +; CGP-NEXT: v_mul_hi_u32 v11, v0, v5 ; CGP-NEXT: v_mul_hi_u32 v5, v1, v5 -; CGP-NEXT: v_mul_lo_u32 v13, v2, v6 -; CGP-NEXT: v_mul_lo_u32 v15, v3, v6 -; CGP-NEXT: v_mul_hi_u32 v16, v2, v6 +; CGP-NEXT: v_mul_lo_u32 v12, v2, v6 +; CGP-NEXT: v_mul_lo_u32 v13, v3, v6 +; CGP-NEXT: v_mul_hi_u32 v14, v2, v6 ; CGP-NEXT: v_mul_hi_u32 v6, v3, v6 -; CGP-NEXT: v_mul_lo_u32 v18, v0, v7 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; CGP-NEXT: v_mul_lo_u32 v11, v1, v7 -; CGP-NEXT: v_mul_hi_u32 v12, v0, v7 +; CGP-NEXT: v_mul_lo_u32 v15, v0, v7 +; CGP-NEXT: v_mul_lo_u32 v16, v1, v7 +; CGP-NEXT: v_mul_hi_u32 v17, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 -; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 -; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v15, v4 -; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 -; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 -; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v16 -; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] -; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v12 +; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v9, vcc, v13, v9 -; CGP-NEXT: v_add_i32_e32 v10, vcc, v15, v10 -; CGP-NEXT: v_add_i32_e32 v13, vcc, v18, v16 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; CGP-NEXT: v_add_i32_e32 v4, vcc, v13, v4 +; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v15 +; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v16, v5 +; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v14 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v13 -; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; CGP-NEXT: v_mul_lo_u32 v10, s12, v4 -; CGP-NEXT: v_mul_lo_u32 v13, 0, v4 -; CGP-NEXT: v_mul_hi_u32 v15, s12, v4 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; CGP-NEXT: v_mul_lo_u32 v12, s12, v5 -; CGP-NEXT: v_mul_lo_u32 v16, 0, v5 -; CGP-NEXT: v_mul_hi_u32 v18, s12, v5 -; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v11 -; CGP-NEXT: v_mul_lo_u32 v9, s12, v6 -; CGP-NEXT: v_mul_lo_u32 v11, s12, v7 -; CGP-NEXT: v_add_i32_e32 v9, vcc, v13, v9 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v17 +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; CGP-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; CGP-NEXT: v_add_i32_e32 v9, vcc, v15, v9 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v16, v11 -; CGP-NEXT: v_add_i32_e32 v13, vcc, 1, v4 +; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8 +; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; CGP-NEXT: v_mul_lo_u32 v10, s10, v4 +; CGP-NEXT: v_mul_lo_u32 v12, 0, v4 +; CGP-NEXT: v_mul_hi_u32 v13, s10, v4 +; CGP-NEXT: v_add_i32_e32 v9, vcc, v11, v9 +; CGP-NEXT: v_mul_lo_u32 v11, s10, v5 +; CGP-NEXT: v_mul_lo_u32 v14, 0, v5 +; CGP-NEXT: v_mul_hi_u32 v15, s10, v5 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8 +; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 +; CGP-NEXT: v_mul_lo_u32 v8, s10, v6 +; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v4 ; CGP-NEXT: v_addc_u32_e32 v16, vcc, 0, v6, vcc -; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v15 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; CGP-NEXT: v_add_i32_e32 v15, vcc, 1, v5 -; CGP-NEXT: v_addc_u32_e32 v18, vcc, 0, v7, vcc +; CGP-NEXT: v_mul_lo_u32 v17, s10, v7 +; CGP-NEXT: v_add_i32_e32 v18, vcc, 1, v5 +; CGP-NEXT: v_addc_u32_e32 v19, vcc, 0, v7, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v17 +; CGP-NEXT: v_add_i32_e32 v14, vcc, 1, v9 +; CGP-NEXT: v_addc_u32_e32 v17, vcc, 0, v16, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v13 +; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15 +; CGP-NEXT: v_add_i32_e32 v13, vcc, 1, v18 +; CGP-NEXT: v_addc_u32_e32 v15, vcc, 0, v19, vcc ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v10 -; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v3, v9, vcc -; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v9 -; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s12, v2 -; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] -; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v12 -; CGP-NEXT: v_subb_u32_e64 v12, s[6:7], v1, v11, s[4:5] -; CGP-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v11 +; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v3, v8, vcc +; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v8 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s10, v2 +; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v11 +; CGP-NEXT: v_subb_u32_e64 v11, s[6:7], v1, v12, s[4:5] +; CGP-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v12 +; CGP-NEXT: v_cmp_le_u32_e64 s[6:7], 0, v10 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[6:7] ; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v10 -; CGP-NEXT: v_add_i32_e64 v10, s[8:9], 1, v13 -; CGP-NEXT: v_addc_u32_e64 v11, s[8:9], 0, v16, s[8:9] -; CGP-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7] -; CGP-NEXT: v_cmp_le_u32_e64 s[6:7], s12, v0 -; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7] -; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v12 -; CGP-NEXT: v_cndmask_b32_e64 v9, v14, v9, s[6:7] -; CGP-NEXT: v_add_i32_e64 v12, s[6:7], 1, v15 -; CGP-NEXT: v_addc_u32_e64 v14, s[6:7], 0, v18, s[6:7] +; CGP-NEXT: v_cmp_le_u32_e64 s[8:9], s10, v0 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[8:9] ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc +; CGP-NEXT: v_cndmask_b32_e64 v8, v12, v8, s[6:7] +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v11 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; CGP-NEXT: v_subbrev_u32_e64 v1, vcc, 0, v1, s[4:5] -; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s12, v2 +; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s10, v2 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: v_cmp_le_u32_e32 vcc, s12, v2 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, s10, v2 ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0 +; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v11 +; CGP-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc +; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s10, v0 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CGP-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, s10, v0 ; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; CGP-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc +; CGP-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc +; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v1, v13, v10, vcc +; CGP-NEXT: v_cndmask_b32_e32 v1, v9, v14, vcc ; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 -; CGP-NEXT: v_cndmask_b32_e64 v0, v15, v12, s[4:5] -; CGP-NEXT: v_cndmask_b32_e32 v3, v16, v11, vcc +; CGP-NEXT: v_cndmask_b32_e64 v0, v18, v13, s[4:5] +; CGP-NEXT: v_cndmask_b32_e32 v3, v16, v17, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; CGP-NEXT: v_cndmask_b32_e32 v2, v4, v1, vcc -; CGP-NEXT: v_cndmask_b32_e64 v1, v18, v14, s[4:5] -; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9 +; CGP-NEXT: v_cndmask_b32_e64 v1, v19, v15, s[4:5] +; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v10 ; CGP-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc @@ -3191,10 +3191,6 @@ define <2 x i64> @v_udiv_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) { ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19 ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e32 v19, vcc, v20, v19 -; GISEL-NEXT: s_bfe_i32 s10, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s12, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s13, -1, 0x10000 ; GISEL-NEXT: v_and_b32_e32 v0, s6, v0 ; GISEL-NEXT: v_and_b32_e32 v2, s6, v2 ; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12 @@ -3209,176 +3205,180 @@ define <2 x i64> @v_udiv_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) { ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v16 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v14 ; GISEL-NEXT: v_addc_u32_e64 v14, s[4:5], v8, v12, vcc -; GISEL-NEXT: v_mul_lo_u32 v15, v6, v1 +; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v12 +; GISEL-NEXT: v_mul_lo_u32 v12, v6, v1 ; GISEL-NEXT: v_mul_lo_u32 v7, v7, v1 +; GISEL-NEXT: v_mul_hi_u32 v15, v6, v1 ; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v17 ; GISEL-NEXT: v_addc_u32_e64 v16, s[6:7], v11, v13, s[4:5] -; GISEL-NEXT: v_mul_lo_u32 v17, v9, v5 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v13 +; GISEL-NEXT: v_mul_lo_u32 v13, v9, v5 ; GISEL-NEXT: v_mul_lo_u32 v10, v10, v5 -; GISEL-NEXT: v_mul_hi_u32 v18, v9, v5 +; GISEL-NEXT: v_mul_hi_u32 v17, v9, v5 +; GISEL-NEXT: v_mul_lo_u32 v6, v6, v14 +; GISEL-NEXT: v_mul_lo_u32 v18, v14, v12 +; GISEL-NEXT: v_mul_hi_u32 v19, v1, v12 +; GISEL-NEXT: v_mul_hi_u32 v12, v14, v12 ; GISEL-NEXT: v_mul_lo_u32 v9, v9, v16 -; GISEL-NEXT: v_mul_lo_u32 v19, v16, v17 +; GISEL-NEXT: v_add_i32_e64 v6, s[6:7], v7, v6 +; GISEL-NEXT: v_mul_lo_u32 v7, v16, v13 ; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v10, v9 -; GISEL-NEXT: v_mul_hi_u32 v10, v5, v17 -; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v18 -; GISEL-NEXT: v_mul_lo_u32 v18, v5, v9 -; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v18, v10 -; GISEL-NEXT: v_mul_hi_u32 v10, v6, v1 -; GISEL-NEXT: v_mul_lo_u32 v6, v6, v14 -; GISEL-NEXT: v_mul_lo_u32 v18, v14, v15 -; GISEL-NEXT: v_add_i32_e64 v6, s[8:9], v7, v6 -; GISEL-NEXT: v_mul_hi_u32 v7, v1, v15 -; GISEL-NEXT: v_add_i32_e64 v6, s[8:9], v6, v10 -; GISEL-NEXT: v_mul_lo_u32 v10, v1, v6 -; GISEL-NEXT: v_add_i32_e64 v10, s[8:9], v18, v10 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v7, s[8:9], v10, v7 -; GISEL-NEXT: v_mov_b32_e32 v7, s10 -; GISEL-NEXT: v_mov_b32_e32 v10, s11 -; GISEL-NEXT: v_add_i32_e64 v8, s[10:11], v8, v12 -; GISEL-NEXT: v_mov_b32_e32 v12, s12 -; GISEL-NEXT: v_add_i32_e64 v11, s[10:11], v11, v13 -; GISEL-NEXT: v_mul_hi_u32 v13, v14, v15 -; GISEL-NEXT: v_mul_hi_u32 v15, v16, v17 -; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v17, s[8:9], v18, v17 -; GISEL-NEXT: v_mul_lo_u32 v18, v14, v6 -; GISEL-NEXT: v_mul_hi_u32 v14, v14, v6 -; GISEL-NEXT: v_mul_hi_u32 v6, v1, v6 -; GISEL-NEXT: v_add_i32_e64 v13, s[8:9], v18, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v6, s[8:9], v13, v6 -; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v13, s[8:9], v18, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 -; GISEL-NEXT: v_mul_lo_u32 v19, v16, v9 +; GISEL-NEXT: v_mul_hi_u32 v10, v5, v13 +; GISEL-NEXT: v_mul_hi_u32 v13, v16, v13 +; GISEL-NEXT: v_add_i32_e64 v6, s[6:7], v6, v15 +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v17 +; GISEL-NEXT: v_mul_lo_u32 v15, v1, v6 +; GISEL-NEXT: v_mul_lo_u32 v17, v5, v9 +; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v7, v17 +; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v7, v10 +; GISEL-NEXT: v_mul_lo_u32 v7, v14, v6 +; GISEL-NEXT: v_mul_hi_u32 v10, v1, v6 +; GISEL-NEXT: v_mul_hi_u32 v6, v14, v6 +; GISEL-NEXT: v_mul_lo_u32 v14, v16, v9 ; GISEL-NEXT: v_mul_hi_u32 v16, v16, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v5, v9 -; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v19, v15 +; GISEL-NEXT: v_add_i32_e64 v15, s[8:9], v18, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v7, s[8:9], v7, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v13, s[8:9], v14, v13 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v15, s[8:9], v15, v19 +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v7, s[8:9], v7, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[8:9] ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v15, v9 -; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v19, v15 -; GISEL-NEXT: v_mov_b32_e32 v19, s13 -; GISEL-NEXT: v_add_i32_e64 v6, s[6:7], v6, v17 -; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], v13, v17 -; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v15, v18 +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v13, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v18, v15 +; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v12, v10 +; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v17, v19 ; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], v14, v13 -; GISEL-NEXT: v_add_i32_e64 v14, s[6:7], v16, v15 -; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc -; GISEL-NEXT: v_addc_u32_e64 v11, vcc, v11, v14, s[4:5] -; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6 -; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc -; GISEL-NEXT: v_mul_lo_u32 v8, 0, v1 -; GISEL-NEXT: v_mul_hi_u32 v13, v0, v1 +; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v7, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v10, v14 +; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v13, v12 +; GISEL-NEXT: v_add_i32_e64 v6, s[6:7], v6, v10 +; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v16, v12 +; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v8, v6, vcc +; GISEL-NEXT: v_addc_u32_e64 v8, vcc, v11, v10, s[4:5] +; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v7 +; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc +; GISEL-NEXT: v_mul_lo_u32 v7, 0, v1 +; GISEL-NEXT: v_mul_hi_u32 v10, v0, v1 ; GISEL-NEXT: v_mul_hi_u32 v1, 0, v1 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9 -; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v11, vcc -; GISEL-NEXT: v_mul_lo_u32 v11, 0, v5 -; GISEL-NEXT: v_mul_hi_u32 v14, v2, v5 +; GISEL-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc +; GISEL-NEXT: v_mul_lo_u32 v9, 0, v5 +; GISEL-NEXT: v_mul_hi_u32 v11, v2, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, 0, v5 -; GISEL-NEXT: v_mul_lo_u32 v15, v0, v6 -; GISEL-NEXT: v_mul_lo_u32 v16, 0, v6 -; GISEL-NEXT: v_mul_hi_u32 v17, v0, v6 +; GISEL-NEXT: v_mul_lo_u32 v12, v0, v6 +; GISEL-NEXT: v_mul_lo_u32 v13, 0, v6 +; GISEL-NEXT: v_mul_hi_u32 v14, v0, v6 ; GISEL-NEXT: v_mul_hi_u32 v6, 0, v6 -; GISEL-NEXT: v_mul_lo_u32 v18, v2, v9 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 -; GISEL-NEXT: v_mul_lo_u32 v11, 0, v9 -; GISEL-NEXT: v_mul_hi_u32 v14, v2, v9 -; GISEL-NEXT: v_mul_hi_u32 v9, 0, v9 -; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v15 -; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v1, s[4:5], v16, v1 -; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 -; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v1, s[4:5], v1, v17 -; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v14 -; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v8, vcc, v15, v8 -; GISEL-NEXT: v_add_i32_e32 v13, vcc, v16, v13 -; GISEL-NEXT: v_add_i32_e32 v15, vcc, v18, v17 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 -; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v8 -; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v15 -; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v8, vcc, v13, v8 -; GISEL-NEXT: v_mul_lo_u32 v13, v3, v1 -; GISEL-NEXT: v_mul_lo_u32 v15, 0, v1 -; GISEL-NEXT: v_mul_hi_u32 v16, v3, v1 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 -; GISEL-NEXT: v_mul_lo_u32 v14, v4, v5 -; GISEL-NEXT: v_mul_lo_u32 v17, 0, v5 -; GISEL-NEXT: v_mul_hi_u32 v18, v4, v5 -; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v11 -; GISEL-NEXT: v_mul_lo_u32 v9, v3, v6 -; GISEL-NEXT: v_mul_lo_u32 v11, v4, v8 +; GISEL-NEXT: v_mul_lo_u32 v15, v2, v8 +; GISEL-NEXT: v_mul_lo_u32 v16, 0, v8 +; GISEL-NEXT: v_mul_hi_u32 v17, v2, v8 +; GISEL-NEXT: v_mul_hi_u32 v8, 0, v8 +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1 +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v16, v5 +; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11 +; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v17 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v12, v7 +; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v15, v9 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v17, v11 -; GISEL-NEXT: v_add_i32_e32 v15, vcc, 1, v1 -; GISEL-NEXT: v_addc_u32_e32 v17, vcc, 0, v6, vcc -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v16 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v13 -; GISEL-NEXT: v_subb_u32_e64 v13, s[4:5], 0, v9, vcc +; GISEL-NEXT: v_add_i32_e32 v11, vcc, v16, v11 +; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v7 +; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v10, v7 +; GISEL-NEXT: v_mul_lo_u32 v10, v3, v1 +; GISEL-NEXT: v_mul_lo_u32 v12, 0, v1 +; GISEL-NEXT: v_mul_hi_u32 v13, v3, v1 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9 +; GISEL-NEXT: v_mul_lo_u32 v11, v4, v5 +; GISEL-NEXT: v_mul_lo_u32 v14, 0, v5 +; GISEL-NEXT: v_mul_hi_u32 v15, v4, v5 +; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v9 +; GISEL-NEXT: v_mul_lo_u32 v8, v3, v6 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v1 +; GISEL-NEXT: v_addc_u32_e32 v16, vcc, 0, v6, vcc +; GISEL-NEXT: v_mul_lo_u32 v17, v4, v7 +; GISEL-NEXT: v_add_i32_e32 v18, vcc, 1, v5 +; GISEL-NEXT: v_addc_u32_e32 v19, vcc, 0, v7, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; GISEL-NEXT: v_add_i32_e32 v12, vcc, v14, v17 +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v13 +; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15 +; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v10 +; GISEL-NEXT: v_subb_u32_e64 v10, s[4:5], 0, v8, vcc ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3 -; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, -1, s[4:5] -; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13 -; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], 1, v5 -; GISEL-NEXT: v_addc_u32_e64 v18, s[6:7], 0, v8, s[6:7] -; GISEL-NEXT: v_sub_i32_e64 v2, s[6:7], v2, v14 -; GISEL-NEXT: v_subb_u32_e64 v14, s[8:9], 0, v11, s[6:7] -; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v16, s[4:5] -; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4 -; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, -1, s[4:5] -; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14 -; GISEL-NEXT: v_cndmask_b32_e64 v12, v12, v16, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], 1, v15 -; GISEL-NEXT: v_addc_u32_e64 v16, s[4:5], 0, v17, s[4:5] -; GISEL-NEXT: v_sub_i32_e64 v11, s[4:5], 0, v11 -; GISEL-NEXT: v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[6:7] -; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v4 -; GISEL-NEXT: v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[4:5] -; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4 -; GISEL-NEXT: v_add_i32_e64 v2, s[6:7], 1, v13 -; GISEL-NEXT: v_addc_u32_e64 v4, s[6:7], 0, v18, s[6:7] -; GISEL-NEXT: v_sub_i32_e64 v9, s[6:7], 0, v9 -; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5] +; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v11 +; GISEL-NEXT: v_subb_u32_e64 v11, s[6:7], 0, v12, s[4:5] +; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v4 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[6:7] +; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], 0, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, s[6:7] +; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v10 +; GISEL-NEXT: v_cmp_le_u32_e64 s[8:9], 0, v11 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[8:9] +; GISEL-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v11 +; GISEL-NEXT: v_add_i32_e64 v11, s[10:11], 1, v9 +; GISEL-NEXT: v_addc_u32_e64 v17, s[10:11], 0, v16, s[10:11] +; GISEL-NEXT: v_sub_i32_e64 v8, s[10:11], 0, v8 +; GISEL-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v8, vcc ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 -; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc +; GISEL-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v8, vcc ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 -; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5] -; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 -; GISEL-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc -; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v11 -; GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc -; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GISEL-NEXT: v_cndmask_b32_e32 v0, v15, v14, vcc -; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v3 -; GISEL-NEXT: v_cndmask_b32_e64 v2, v13, v2, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e32 v3, v17, v16, vcc -; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 -; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GISEL-NEXT: v_cndmask_b32_e64 v4, v18, v4, s[4:5] -; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v12 +; GISEL-NEXT: v_add_i32_e64 v0, s[10:11], 1, v18 +; GISEL-NEXT: v_addc_u32_e64 v3, s[10:11], 0, v19, s[10:11] +; GISEL-NEXT: v_sub_i32_e64 v12, s[10:11], 0, v12 +; GISEL-NEXT: v_subbrev_u32_e64 v12, s[4:5], 0, v12, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e64 v13, v15, v13, s[6:7] +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v14, s[8:9] +; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v4 +; GISEL-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v12, vcc +; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 +; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v8 +; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8 +; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v15, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12 +; GISEL-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 +; GISEL-NEXT: v_cndmask_b32_e32 v4, v9, v11, vcc +; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v2 +; GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v0, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e32 v8, v16, v17, vcc +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 +; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s[4:5] +; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc -; GISEL-NEXT: v_cndmask_b32_e64 v3, v8, v4, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5] ; GISEL-NEXT: s_setpc_b64 s[30:31] ; ; CGP-LABEL: v_udiv_v2i64_24bit: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll index 954022f..7411807 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll @@ -998,127 +998,127 @@ define i64 @v_urem_i64_oddk_denom(i64 %num) { ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0 ; CHECK-NEXT: s_mov_b32 s6, 0xffed2705 ; CHECK-NEXT: s_mov_b32 s7, 0x12d8fb -; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 -; CHECK-NEXT: s_bfe_i32 s5, -1, 0x10000 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; CHECK-NEXT: v_mov_b32_e32 v3, s4 -; CHECK-NEXT: v_mov_b32_e32 v4, s5 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; CHECK-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2 -; CHECK-NEXT: v_trunc_f32_e32 v5, v5 -; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5 -; CHECK-NEXT: v_cvt_u32_f32_e32 v5, v5 +; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; CHECK-NEXT: v_trunc_f32_e32 v3, v3 +; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 +; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 -; CHECK-NEXT: v_mul_lo_u32 v6, s6, v5 -; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, -1, v2 -; CHECK-NEXT: v_mul_hi_u32 v9, s6, v2 -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; CHECK-NEXT: v_mul_lo_u32 v8, v5, v7 -; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7 -; CHECK-NEXT: v_mul_hi_u32 v7, v5, v7 -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; CHECK-NEXT: v_mul_lo_u32 v9, v2, v6 -; CHECK-NEXT: v_mul_lo_u32 v11, v5, v6 -; CHECK-NEXT: v_mul_hi_u32 v12, v2, v6 -; CHECK-NEXT: v_mul_hi_u32 v6, v5, v6 -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9 +; CHECK-NEXT: v_mul_lo_u32 v4, s6, v3 +; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2 +; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 +; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5 +; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5 +; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4 +; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4 +; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 +; CHECK-NEXT: v_mul_hi_u32 v4, v3, v4 +; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v11, v7 -; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v12 -; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; CHECK-NEXT: v_add_i32_e32 v9, vcc, v11, v10 -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; CHECK-NEXT: v_addc_u32_e64 v7, s[4:5], v5, v6, vcc -; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v5, v6 -; CHECK-NEXT: v_mul_lo_u32 v6, s6, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, -1, v2 -; CHECK-NEXT: v_mul_hi_u32 v9, s6, v2 -; CHECK-NEXT: v_mul_lo_u32 v10, s6, v7 -; CHECK-NEXT: v_mul_lo_u32 v11, v7, v6 -; CHECK-NEXT: v_mul_hi_u32 v12, v2, v6 -; CHECK-NEXT: v_mul_hi_u32 v6, v7, v6 -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10 -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 -; CHECK-NEXT: v_mul_lo_u32 v9, v2, v8 -; CHECK-NEXT: v_mul_lo_u32 v10, v7, v8 -; CHECK-NEXT: v_mul_hi_u32 v13, v2, v8 -; CHECK-NEXT: v_mul_hi_u32 v7, v7, v8 -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v11, v9 -; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v10, v6 -; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v12 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v13 -; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 -; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v11 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v10 +; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc +; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4 +; CHECK-NEXT: v_mul_lo_u32 v4, s6, v2 +; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 +; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2 +; CHECK-NEXT: v_mul_lo_u32 v8, s6, v5 +; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4 +; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 +; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7 +; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6 +; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6 +; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6 +; CHECK-NEXT: v_mul_hi_u32 v5, v5, v6 +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v9, v7 +; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v8, v4 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] -; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 -; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 -; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; CHECK-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; CHECK-NEXT: v_mul_lo_u32 v6, v1, v2 -; CHECK-NEXT: v_mul_hi_u32 v7, v0, v2 +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v11 +; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 +; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v9 +; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v6 +; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] +; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 +; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v5, v6 +; CHECK-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; CHECK-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; CHECK-NEXT: v_mul_lo_u32 v4, v1, v2 +; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, v0, v5 -; CHECK-NEXT: v_mul_lo_u32 v9, v1, v5 -; CHECK-NEXT: v_mul_hi_u32 v10, v0, v5 -; CHECK-NEXT: v_mul_hi_u32 v5, v1, v5 -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2 -; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; CHECK-NEXT: v_mul_lo_u32 v6, v0, v3 +; CHECK-NEXT: v_mul_lo_u32 v7, v1, v3 +; CHECK-NEXT: v_mul_hi_u32 v8, v0, v3 +; CHECK-NEXT: v_mul_hi_u32 v3, v1, v3 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v10 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2 ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc -; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; CHECK-NEXT: v_mul_lo_u32 v7, s7, v2 -; CHECK-NEXT: v_mul_lo_u32 v8, 0, v2 +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2 +; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, s7, v2 -; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; CHECK-NEXT: v_mul_lo_u32 v5, s7, v5 -; CHECK-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2 -; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 -; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v2, vcc +; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4 +; CHECK-NEXT: v_mul_lo_u32 v3, s7, v3 +; CHECK-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 +; CHECK-NEXT: v_subb_u32_e64 v3, s[4:5], v1, v2, vcc ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5] -; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 -; CHECK-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[4:5] +; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v3 +; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s7, v0 +; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, s7, v0 ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s7, v3 +; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s7, v4 +; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s7, v4 +; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; CHECK-NEXT: v_subrev_i32_e32 v6, vcc, s7, v3 -; CHECK-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v1, vcc -; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 +; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; CHECK-NEXT: s_setpc_b64 s[30:31] %result = urem i64 %num, 1235195 ret i64 %result @@ -1128,9 +1128,9 @@ define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) { ; GISEL-LABEL: v_urem_v2i64_oddk_denom: ; GISEL: ; %bb.0: ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: s_mov_b32 s12, 0x12d8fb -; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s12 -; GISEL-NEXT: s_sub_u32 s8, 0, s12 +; GISEL-NEXT: s_mov_b32 s10, 0x12d8fb +; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s10 +; GISEL-NEXT: s_sub_u32 s8, 0, s10 ; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; GISEL-NEXT: v_mov_b32_e32 v6, v4 @@ -1141,12 +1141,10 @@ define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) { ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v6 ; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, 0 -; GISEL-NEXT: s_bfe_i32 s10, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 -; GISEL-NEXT: s_sub_u32 s13, 0, s12 +; GISEL-NEXT: s_sub_u32 s11, 0, s10 ; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6 @@ -1159,12 +1157,12 @@ define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) { ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_subb_u32 s6, 0, 0 -; GISEL-NEXT: v_mul_lo_u32 v8, s13, v6 +; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s8, v7 -; GISEL-NEXT: v_mul_lo_u32 v10, s13, v4 +; GISEL-NEXT: v_mul_lo_u32 v10, s11, v4 ; GISEL-NEXT: v_mul_lo_u32 v11, s6, v4 -; GISEL-NEXT: v_mul_hi_u32 v12, s13, v4 +; GISEL-NEXT: v_mul_hi_u32 v12, s11, v4 ; GISEL-NEXT: v_mul_lo_u32 v13, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v14, s9, v5 ; GISEL-NEXT: v_mul_hi_u32 v15, s8, v5 @@ -1216,170 +1214,172 @@ define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) { ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; GISEL-NEXT: v_addc_u32_e64 v10, s[4:5], v6, v8, vcc -; GISEL-NEXT: v_mul_lo_u32 v11, s13, v4 -; GISEL-NEXT: v_mul_lo_u32 v12, s6, v4 -; GISEL-NEXT: v_mul_hi_u32 v14, s13, v4 +; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 +; GISEL-NEXT: v_mul_lo_u32 v8, s11, v4 +; GISEL-NEXT: v_mul_lo_u32 v11, s6, v4 +; GISEL-NEXT: v_mul_hi_u32 v12, s11, v4 ; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v13 ; GISEL-NEXT: v_addc_u32_e64 v13, s[6:7], v7, v9, s[4:5] -; GISEL-NEXT: v_mul_lo_u32 v15, s8, v5 -; GISEL-NEXT: v_mul_lo_u32 v16, s9, v5 -; GISEL-NEXT: v_mul_hi_u32 v17, s8, v5 -; GISEL-NEXT: v_mul_lo_u32 v18, s8, v13 -; GISEL-NEXT: v_mul_lo_u32 v19, v13, v15 -; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v18 -; GISEL-NEXT: v_mul_hi_u32 v18, v5, v15 -; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v17 -; GISEL-NEXT: v_mul_lo_u32 v17, v5, v16 -; GISEL-NEXT: v_add_i32_e64 v17, s[6:7], v19, v17 -; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v17, s[6:7], v17, v18 -; GISEL-NEXT: v_mul_lo_u32 v17, s13, v10 -; GISEL-NEXT: v_mul_lo_u32 v18, v10, v11 -; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v12, v17 -; GISEL-NEXT: v_mul_hi_u32 v17, v4, v11 -; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v12, v14 -; GISEL-NEXT: v_mul_lo_u32 v14, v4, v12 -; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v18, v14 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v14, v17 -; GISEL-NEXT: v_mov_b32_e32 v14, s10 -; GISEL-NEXT: v_mov_b32_e32 v17, s11 -; GISEL-NEXT: s_bfe_i32 s13, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s14, -1, 0x10000 -; GISEL-NEXT: v_add_i32_e64 v6, s[10:11], v6, v8 -; GISEL-NEXT: v_mov_b32_e32 v8, s13 -; GISEL-NEXT: v_add_i32_e64 v7, s[10:11], v7, v9 -; GISEL-NEXT: v_mul_hi_u32 v9, v10, v11 -; GISEL-NEXT: v_mul_hi_u32 v11, v13, v15 +; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v7, v9 +; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5 +; GISEL-NEXT: v_mul_lo_u32 v14, s9, v5 +; GISEL-NEXT: v_mul_hi_u32 v15, s8, v5 +; GISEL-NEXT: v_mul_lo_u32 v16, s11, v10 +; GISEL-NEXT: v_mul_lo_u32 v17, v10, v8 +; GISEL-NEXT: v_mul_hi_u32 v18, v4, v8 +; GISEL-NEXT: v_mul_hi_u32 v8, v10, v8 +; GISEL-NEXT: v_mul_lo_u32 v19, s8, v13 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 +; GISEL-NEXT: v_mul_lo_u32 v16, v13, v9 +; GISEL-NEXT: v_add_i32_e64 v14, s[6:7], v14, v19 +; GISEL-NEXT: v_mul_hi_u32 v19, v5, v9 +; GISEL-NEXT: v_mul_hi_u32 v9, v13, v9 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v14, v15 +; GISEL-NEXT: v_mul_lo_u32 v14, v4, v11 +; GISEL-NEXT: v_mul_lo_u32 v15, v5, v12 +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v16, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v15, v19 +; GISEL-NEXT: v_mul_lo_u32 v15, v10, v11 +; GISEL-NEXT: v_mul_hi_u32 v19, v4, v11 +; GISEL-NEXT: v_mul_hi_u32 v10, v10, v11 +; GISEL-NEXT: v_mul_lo_u32 v11, v13, v12 +; GISEL-NEXT: v_mul_hi_u32 v13, v13, v12 +; GISEL-NEXT: v_mul_hi_u32 v12, v5, v12 +; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v17, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v8, s[8:9], v15, v8 ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v15, s[8:9], v18, v15 -; GISEL-NEXT: v_mul_lo_u32 v18, v10, v12 -; GISEL-NEXT: v_mul_hi_u32 v10, v10, v12 -; GISEL-NEXT: v_mul_hi_u32 v12, v4, v12 -; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v18, v9 +; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v11, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v14, v18 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v8, s[8:9], v8, v19 ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v9, v12 -; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v18, v12 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 -; GISEL-NEXT: v_mul_lo_u32 v19, v13, v16 -; GISEL-NEXT: v_mul_hi_u32 v13, v13, v16 -; GISEL-NEXT: v_mul_hi_u32 v16, v5, v16 -; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v19, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 -; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v19, v16 -; GISEL-NEXT: v_mov_b32_e32 v19, s14 -; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v15 -; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v12, v15 -; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v16, v18 +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v14, s[6:7], v17, v14 +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v15, v18 +; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v19 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; GISEL-NEXT: v_add_i32_e64 v8, s[6:7], v8, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v16 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v15, v12 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v14 ; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v10, v12 -; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v13, v15 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v13, v11 ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc -; GISEL-NEXT: v_addc_u32_e64 v7, vcc, v7, v12, s[4:5] -; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; GISEL-NEXT: v_addc_u32_e64 v7, vcc, v7, v11, s[4:5] +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc -; GISEL-NEXT: v_mul_lo_u32 v9, v3, v4 +; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4 ; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4 -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v11 +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc -; GISEL-NEXT: v_mul_lo_u32 v11, v1, v5 -; GISEL-NEXT: v_mul_hi_u32 v12, v0, v5 +; GISEL-NEXT: v_mul_lo_u32 v9, v1, v5 +; GISEL-NEXT: v_mul_hi_u32 v11, v0, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5 -; GISEL-NEXT: v_mul_lo_u32 v13, v2, v6 -; GISEL-NEXT: v_mul_lo_u32 v15, v3, v6 -; GISEL-NEXT: v_mul_hi_u32 v16, v2, v6 +; GISEL-NEXT: v_mul_lo_u32 v12, v2, v6 +; GISEL-NEXT: v_mul_lo_u32 v13, v3, v6 +; GISEL-NEXT: v_mul_hi_u32 v14, v2, v6 ; GISEL-NEXT: v_mul_hi_u32 v6, v3, v6 -; GISEL-NEXT: v_mul_lo_u32 v18, v0, v7 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GISEL-NEXT: v_mul_lo_u32 v11, v1, v7 -; GISEL-NEXT: v_mul_hi_u32 v12, v0, v7 +; GISEL-NEXT: v_mul_lo_u32 v15, v0, v7 +; GISEL-NEXT: v_mul_lo_u32 v16, v1, v7 +; GISEL-NEXT: v_mul_hi_u32 v17, v0, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7 -; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v15, v4 -; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 -; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 -; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v16 -; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v12 +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v13, v9 -; GISEL-NEXT: v_add_i32_e32 v10, vcc, v15, v10 -; GISEL-NEXT: v_add_i32_e32 v13, vcc, v18, v16 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v13, v4 +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v16, v5 +; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GISEL-NEXT: v_mul_lo_u32 v10, s12, v4 -; GISEL-NEXT: v_mul_lo_u32 v13, 0, v4 -; GISEL-NEXT: v_mul_hi_u32 v4, s12, v4 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GISEL-NEXT: v_mul_lo_u32 v12, s12, v5 -; GISEL-NEXT: v_mul_lo_u32 v15, 0, v5 -; GISEL-NEXT: v_mul_hi_u32 v5, s12, v5 -; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11 -; GISEL-NEXT: v_mul_lo_u32 v6, s12, v6 -; GISEL-NEXT: v_mul_lo_u32 v7, s12, v7 -; GISEL-NEXT: v_add_i32_e32 v6, vcc, v13, v6 -; GISEL-NEXT: v_add_i32_e32 v7, vcc, v15, v7 +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v17 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v15, v9 +; GISEL-NEXT: v_add_i32_e32 v11, vcc, v16, v11 +; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8 +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GISEL-NEXT: v_mul_lo_u32 v10, s10, v4 +; GISEL-NEXT: v_mul_lo_u32 v12, 0, v4 +; GISEL-NEXT: v_mul_hi_u32 v4, s10, v4 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9 +; GISEL-NEXT: v_mul_lo_u32 v11, s10, v5 +; GISEL-NEXT: v_mul_lo_u32 v13, 0, v5 +; GISEL-NEXT: v_mul_hi_u32 v5, s10, v5 +; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8 +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 +; GISEL-NEXT: v_mul_lo_u32 v6, s10, v6 +; GISEL-NEXT: v_mul_lo_u32 v7, s10, v7 +; GISEL-NEXT: v_add_i32_e32 v6, vcc, v12, v6 +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v13, v7 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v10 ; GISEL-NEXT: v_subb_u32_e64 v6, s[4:5], v3, v4, vcc ; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4 -; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s12, v2 +; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s10, v2 ; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] -; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v12 +; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v11 ; GISEL-NEXT: v_subb_u32_e64 v7, s[6:7], v1, v5, s[4:5] ; GISEL-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v5 -; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], s12, v0 +; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], s10, v0 ; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[6:7] -; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6 -; GISEL-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[6:7] +; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], 0, v6 +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7] ; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7 -; GISEL-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v7 +; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GISEL-NEXT: v_subbrev_u32_e64 v1, vcc, 0, v1, s[4:5] -; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, s12, v2 +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 +; GISEL-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc +; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, s10, v2 ; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s12, v8 -; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc -; GISEL-NEXT: v_subrev_i32_e32 v10, vcc, s12, v0 +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s10, v8 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7 +; GISEL-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc +; GISEL-NEXT: v_subrev_i32_e32 v9, vcc, s10, v0 ; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s12, v10 +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s10, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc +; GISEL-NEXT: v_subrev_i32_e32 v13, vcc, s10, v8 +; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v3, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, vcc +; GISEL-NEXT: v_subrev_i32_e32 v16, vcc, s10, v9 +; GISEL-NEXT: v_subbrev_u32_e32 v17, vcc, 0, v1, vcc ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; GISEL-NEXT: v_cndmask_b32_e32 v9, v19, v9, vcc -; GISEL-NEXT: v_subrev_i32_e32 v12, vcc, s12, v8 -; GISEL-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v3, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GISEL-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc -; GISEL-NEXT: v_subrev_i32_e32 v14, vcc, s12, v10 -; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc -; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 -; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 +; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v13, vcc ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v11 -; GISEL-NEXT: v_cndmask_b32_e64 v9, v10, v14, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v9, v9, v16, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v14, vcc ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc -; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v15, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5] ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 ; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] @@ -1392,11 +1392,7 @@ define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; CGP-NEXT: s_mov_b32 s8, 0xffed2705 -; CGP-NEXT: s_mov_b32 s12, 0x12d8fb -; CGP-NEXT: s_bfe_i32 s10, -1, 0x10000 -; CGP-NEXT: s_bfe_i32 s11, -1, 0x10000 -; CGP-NEXT: s_bfe_i32 s13, -1, 0x10000 -; CGP-NEXT: s_bfe_i32 s14, -1, 0x10000 +; CGP-NEXT: s_mov_b32 s10, 0x12d8fb ; CGP-NEXT: v_mov_b32_e32 v6, v4 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5 @@ -1470,168 +1466,172 @@ define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) { ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v6, v8, vcc -; CGP-NEXT: v_mul_lo_u32 v11, s8, v4 -; CGP-NEXT: v_mul_lo_u32 v12, -1, v4 -; CGP-NEXT: v_mul_hi_u32 v14, s8, v4 +; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 +; CGP-NEXT: v_mul_lo_u32 v8, s8, v4 +; CGP-NEXT: v_mul_lo_u32 v11, -1, v4 +; CGP-NEXT: v_mul_hi_u32 v12, s8, v4 ; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v5, v13 ; CGP-NEXT: v_addc_u32_e64 v13, s[6:7], v7, v9, s[4:5] -; CGP-NEXT: v_mul_lo_u32 v15, s8, v5 -; CGP-NEXT: v_mul_lo_u32 v16, -1, v5 -; CGP-NEXT: v_mul_hi_u32 v17, s8, v5 -; CGP-NEXT: v_mul_lo_u32 v18, s8, v13 -; CGP-NEXT: v_mul_lo_u32 v19, v13, v15 -; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v18 -; CGP-NEXT: v_mul_hi_u32 v18, v5, v15 -; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v17 -; CGP-NEXT: v_mul_lo_u32 v17, v5, v16 -; CGP-NEXT: v_add_i32_e64 v17, s[6:7], v19, v17 -; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v17, s[6:7], v17, v18 -; CGP-NEXT: v_mul_lo_u32 v17, s8, v10 -; CGP-NEXT: v_mul_lo_u32 v18, v10, v11 -; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v12, v17 -; CGP-NEXT: v_mul_hi_u32 v17, v4, v11 -; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v12, v14 -; CGP-NEXT: v_mul_lo_u32 v14, v4, v12 -; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v18, v14 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v14, v17 -; CGP-NEXT: v_mov_b32_e32 v14, s10 -; CGP-NEXT: v_mov_b32_e32 v17, s11 -; CGP-NEXT: v_add_i32_e64 v6, s[10:11], v6, v8 -; CGP-NEXT: v_mov_b32_e32 v8, s13 -; CGP-NEXT: v_add_i32_e64 v7, s[10:11], v7, v9 -; CGP-NEXT: v_mul_hi_u32 v9, v10, v11 -; CGP-NEXT: v_mul_hi_u32 v11, v13, v15 +; CGP-NEXT: v_add_i32_e64 v7, s[6:7], v7, v9 +; CGP-NEXT: v_mul_lo_u32 v9, s8, v5 +; CGP-NEXT: v_mul_lo_u32 v14, -1, v5 +; CGP-NEXT: v_mul_hi_u32 v15, s8, v5 +; CGP-NEXT: v_mul_lo_u32 v16, s8, v10 +; CGP-NEXT: v_mul_lo_u32 v17, v10, v8 +; CGP-NEXT: v_mul_hi_u32 v18, v4, v8 +; CGP-NEXT: v_mul_hi_u32 v8, v10, v8 +; CGP-NEXT: v_mul_lo_u32 v19, s8, v13 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 +; CGP-NEXT: v_mul_lo_u32 v16, v13, v9 +; CGP-NEXT: v_add_i32_e64 v14, s[6:7], v14, v19 +; CGP-NEXT: v_mul_hi_u32 v19, v5, v9 +; CGP-NEXT: v_mul_hi_u32 v9, v13, v9 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v14, v15 +; CGP-NEXT: v_mul_lo_u32 v14, v4, v11 +; CGP-NEXT: v_mul_lo_u32 v15, v5, v12 +; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v16, v15 +; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v15, v19 +; CGP-NEXT: v_mul_lo_u32 v15, v10, v11 +; CGP-NEXT: v_mul_hi_u32 v19, v4, v11 +; CGP-NEXT: v_mul_hi_u32 v10, v10, v11 +; CGP-NEXT: v_mul_lo_u32 v11, v13, v12 +; CGP-NEXT: v_mul_hi_u32 v13, v13, v12 +; CGP-NEXT: v_mul_hi_u32 v12, v5, v12 +; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v17, v14 +; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] +; CGP-NEXT: v_add_i32_e64 v8, s[8:9], v15, v8 ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v15, s[8:9], v18, v15 -; CGP-NEXT: v_mul_lo_u32 v18, v10, v12 -; CGP-NEXT: v_mul_hi_u32 v10, v10, v12 -; CGP-NEXT: v_mul_hi_u32 v12, v4, v12 -; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v18, v9 +; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v11, v9 +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[8:9] +; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v14, v18 +; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[8:9] +; CGP-NEXT: v_add_i32_e64 v8, s[8:9], v8, v19 ; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v9, v12 -; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[8:9] -; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v18, v12 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 -; CGP-NEXT: v_mul_lo_u32 v19, v13, v16 -; CGP-NEXT: v_mul_hi_u32 v13, v13, v16 -; CGP-NEXT: v_mul_hi_u32 v16, v5, v16 -; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v19, v11 ; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 -; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v19, v16 -; CGP-NEXT: v_mov_b32_e32 v19, s14 -; CGP-NEXT: v_add_i32_e64 v9, s[6:7], v9, v15 -; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v18 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v12, v15 -; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v16, v18 +; CGP-NEXT: v_add_i32_e64 v9, s[6:7], v9, v12 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v14, s[6:7], v17, v14 +; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v15, v18 +; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v19 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12 +; CGP-NEXT: v_add_i32_e64 v8, s[6:7], v8, v14 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v9, s[6:7], v9, v16 +; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7] +; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v15, v12 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v14 ; CGP-NEXT: v_add_i32_e64 v10, s[6:7], v10, v12 -; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v13, v15 +; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v13, v11 ; CGP-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc -; CGP-NEXT: v_addc_u32_e64 v7, vcc, v7, v12, s[4:5] -; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; CGP-NEXT: v_addc_u32_e64 v7, vcc, v7, v11, s[4:5] +; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; CGP-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc -; CGP-NEXT: v_mul_lo_u32 v9, v3, v4 +; CGP-NEXT: v_mul_lo_u32 v8, v3, v4 ; CGP-NEXT: v_mul_hi_u32 v10, v2, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v3, v4 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v11 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc -; CGP-NEXT: v_mul_lo_u32 v11, v1, v5 -; CGP-NEXT: v_mul_hi_u32 v12, v0, v5 +; CGP-NEXT: v_mul_lo_u32 v9, v1, v5 +; CGP-NEXT: v_mul_hi_u32 v11, v0, v5 ; CGP-NEXT: v_mul_hi_u32 v5, v1, v5 -; CGP-NEXT: v_mul_lo_u32 v13, v2, v6 -; CGP-NEXT: v_mul_lo_u32 v15, v3, v6 -; CGP-NEXT: v_mul_hi_u32 v16, v2, v6 +; CGP-NEXT: v_mul_lo_u32 v12, v2, v6 +; CGP-NEXT: v_mul_lo_u32 v13, v3, v6 +; CGP-NEXT: v_mul_hi_u32 v14, v2, v6 ; CGP-NEXT: v_mul_hi_u32 v6, v3, v6 -; CGP-NEXT: v_mul_lo_u32 v18, v0, v7 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; CGP-NEXT: v_mul_lo_u32 v11, v1, v7 -; CGP-NEXT: v_mul_hi_u32 v12, v0, v7 +; CGP-NEXT: v_mul_lo_u32 v15, v0, v7 +; CGP-NEXT: v_mul_lo_u32 v16, v1, v7 +; CGP-NEXT: v_mul_hi_u32 v17, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 -; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 -; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v15, v4 -; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 -; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 -; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v16 -; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] -; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v12 +; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v9, vcc, v13, v9 -; CGP-NEXT: v_add_i32_e32 v10, vcc, v15, v10 -; CGP-NEXT: v_add_i32_e32 v13, vcc, v18, v16 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; CGP-NEXT: v_add_i32_e32 v4, vcc, v13, v4 +; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v15 +; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v16, v5 +; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v14 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v13 -; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc -; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; CGP-NEXT: v_mul_lo_u32 v10, s12, v4 -; CGP-NEXT: v_mul_lo_u32 v13, 0, v4 -; CGP-NEXT: v_mul_hi_u32 v4, s12, v4 -; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; CGP-NEXT: v_mul_lo_u32 v12, s12, v5 -; CGP-NEXT: v_mul_lo_u32 v15, 0, v5 -; CGP-NEXT: v_mul_hi_u32 v5, s12, v5 -; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v11 -; CGP-NEXT: v_mul_lo_u32 v6, s12, v6 -; CGP-NEXT: v_mul_lo_u32 v7, s12, v7 -; CGP-NEXT: v_add_i32_e32 v6, vcc, v13, v6 -; CGP-NEXT: v_add_i32_e32 v7, vcc, v15, v7 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v17 +; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v12, v8 +; CGP-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; CGP-NEXT: v_add_i32_e32 v9, vcc, v15, v9 +; CGP-NEXT: v_add_i32_e32 v11, vcc, v16, v11 +; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8 +; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; CGP-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; CGP-NEXT: v_mul_lo_u32 v10, s10, v4 +; CGP-NEXT: v_mul_lo_u32 v12, 0, v4 +; CGP-NEXT: v_mul_hi_u32 v4, s10, v4 +; CGP-NEXT: v_add_i32_e32 v9, vcc, v11, v9 +; CGP-NEXT: v_mul_lo_u32 v11, s10, v5 +; CGP-NEXT: v_mul_lo_u32 v13, 0, v5 +; CGP-NEXT: v_mul_hi_u32 v5, s10, v5 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8 +; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 +; CGP-NEXT: v_mul_lo_u32 v6, s10, v6 +; CGP-NEXT: v_mul_lo_u32 v7, s10, v7 +; CGP-NEXT: v_add_i32_e32 v6, vcc, v12, v6 +; CGP-NEXT: v_add_i32_e32 v7, vcc, v13, v7 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v10 ; CGP-NEXT: v_subb_u32_e64 v6, s[4:5], v3, v4, vcc ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4 -; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s12, v2 +; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s10, v2 ; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] -; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v12 +; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v11 ; CGP-NEXT: v_subb_u32_e64 v7, s[6:7], v1, v5, s[4:5] ; CGP-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v5 -; CGP-NEXT: v_cmp_le_u32_e64 s[6:7], s12, v0 +; CGP-NEXT: v_cmp_le_u32_e64 s[6:7], s10, v0 ; CGP-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[6:7] -; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6 -; CGP-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[6:7] +; CGP-NEXT: v_cmp_le_u32_e64 s[6:7], 0, v6 +; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7] ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7 -; CGP-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v7 +; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; CGP-NEXT: v_subbrev_u32_e64 v1, vcc, 0, v1, s[4:5] -; CGP-NEXT: v_subrev_i32_e32 v8, vcc, s12, v2 +; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 +; CGP-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc +; CGP-NEXT: v_subrev_i32_e32 v8, vcc, s10, v2 ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc -; CGP-NEXT: v_cmp_le_u32_e32 vcc, s12, v8 -; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc -; CGP-NEXT: v_subrev_i32_e32 v10, vcc, s12, v0 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, s10, v8 +; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc +; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7 +; CGP-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc +; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s10, v0 ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; CGP-NEXT: v_cmp_le_u32_e32 vcc, s12, v10 +; CGP-NEXT: v_cmp_le_u32_e32 vcc, s10, v9 ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 +; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc +; CGP-NEXT: v_subrev_i32_e32 v13, vcc, s10, v8 +; CGP-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v3, vcc +; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 +; CGP-NEXT: v_cndmask_b32_e64 v15, 0, -1, vcc +; CGP-NEXT: v_subrev_i32_e32 v16, vcc, s10, v9 +; CGP-NEXT: v_subbrev_u32_e32 v17, vcc, 0, v1, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; CGP-NEXT: v_cndmask_b32_e32 v9, v19, v9, vcc -; CGP-NEXT: v_subrev_i32_e32 v12, vcc, s12, v8 -; CGP-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v3, vcc +; CGP-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc -; CGP-NEXT: v_subrev_i32_e32 v14, vcc, s12, v10 -; CGP-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc -; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 -; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc +; CGP-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc +; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 +; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v13, vcc ; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v11 -; CGP-NEXT: v_cndmask_b32_e64 v9, v10, v14, s[4:5] -; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc +; CGP-NEXT: v_cndmask_b32_e64 v9, v9, v16, s[4:5] +; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v14, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc -; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v15, s[4:5] +; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5] ; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] @@ -2540,10 +2540,6 @@ define <2 x i64> @v_urem_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) { ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19 ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e32 v19, vcc, v20, v19 -; GISEL-NEXT: s_bfe_i32 s10, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s12, -1, 0x10000 -; GISEL-NEXT: s_bfe_i32 s13, -1, 0x10000 ; GISEL-NEXT: v_and_b32_e32 v0, s6, v0 ; GISEL-NEXT: v_and_b32_e32 v2, s6, v2 ; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12 @@ -2558,172 +2554,176 @@ define <2 x i64> @v_urem_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) { ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v16 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v14 ; GISEL-NEXT: v_addc_u32_e64 v14, s[4:5], v8, v12, vcc -; GISEL-NEXT: v_mul_lo_u32 v15, v6, v1 +; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v12 +; GISEL-NEXT: v_mul_lo_u32 v12, v6, v1 ; GISEL-NEXT: v_mul_lo_u32 v7, v7, v1 +; GISEL-NEXT: v_mul_hi_u32 v15, v6, v1 ; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v17 ; GISEL-NEXT: v_addc_u32_e64 v16, s[6:7], v11, v13, s[4:5] -; GISEL-NEXT: v_mul_lo_u32 v17, v9, v5 +; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v13 +; GISEL-NEXT: v_mul_lo_u32 v13, v9, v5 ; GISEL-NEXT: v_mul_lo_u32 v10, v10, v5 -; GISEL-NEXT: v_mul_hi_u32 v18, v9, v5 +; GISEL-NEXT: v_mul_hi_u32 v17, v9, v5 +; GISEL-NEXT: v_mul_lo_u32 v6, v6, v14 +; GISEL-NEXT: v_mul_lo_u32 v18, v14, v12 +; GISEL-NEXT: v_mul_hi_u32 v19, v1, v12 +; GISEL-NEXT: v_mul_hi_u32 v12, v14, v12 ; GISEL-NEXT: v_mul_lo_u32 v9, v9, v16 -; GISEL-NEXT: v_mul_lo_u32 v19, v16, v17 +; GISEL-NEXT: v_add_i32_e64 v6, s[6:7], v7, v6 +; GISEL-NEXT: v_mul_lo_u32 v7, v16, v13 ; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v10, v9 -; GISEL-NEXT: v_mul_hi_u32 v10, v5, v17 -; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v18 -; GISEL-NEXT: v_mul_lo_u32 v18, v5, v9 -; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v18, v10 -; GISEL-NEXT: v_mul_hi_u32 v10, v6, v1 -; GISEL-NEXT: v_mul_lo_u32 v6, v6, v14 -; GISEL-NEXT: v_mul_lo_u32 v18, v14, v15 -; GISEL-NEXT: v_add_i32_e64 v6, s[8:9], v7, v6 -; GISEL-NEXT: v_mul_hi_u32 v7, v1, v15 -; GISEL-NEXT: v_add_i32_e64 v6, s[8:9], v6, v10 -; GISEL-NEXT: v_mul_lo_u32 v10, v1, v6 -; GISEL-NEXT: v_add_i32_e64 v10, s[8:9], v18, v10 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v7, s[8:9], v10, v7 -; GISEL-NEXT: v_mov_b32_e32 v7, s10 -; GISEL-NEXT: v_mov_b32_e32 v10, s11 -; GISEL-NEXT: v_add_i32_e64 v8, s[10:11], v8, v12 -; GISEL-NEXT: v_mov_b32_e32 v12, s12 -; GISEL-NEXT: v_add_i32_e64 v11, s[10:11], v11, v13 -; GISEL-NEXT: v_mul_hi_u32 v13, v14, v15 -; GISEL-NEXT: v_mul_hi_u32 v15, v16, v17 -; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v17, s[8:9], v18, v17 -; GISEL-NEXT: v_mul_lo_u32 v18, v14, v6 -; GISEL-NEXT: v_mul_hi_u32 v14, v14, v6 -; GISEL-NEXT: v_mul_hi_u32 v6, v1, v6 -; GISEL-NEXT: v_add_i32_e64 v13, s[8:9], v18, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v6, s[8:9], v13, v6 -; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[8:9] -; GISEL-NEXT: v_add_i32_e64 v13, s[8:9], v18, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 -; GISEL-NEXT: v_mul_lo_u32 v19, v16, v9 +; GISEL-NEXT: v_mul_hi_u32 v10, v5, v13 +; GISEL-NEXT: v_mul_hi_u32 v13, v16, v13 +; GISEL-NEXT: v_add_i32_e64 v6, s[6:7], v6, v15 +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v17 +; GISEL-NEXT: v_mul_lo_u32 v15, v1, v6 +; GISEL-NEXT: v_mul_lo_u32 v17, v5, v9 +; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v7, v17 +; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v7, v10 +; GISEL-NEXT: v_mul_lo_u32 v7, v14, v6 +; GISEL-NEXT: v_mul_hi_u32 v10, v1, v6 +; GISEL-NEXT: v_mul_hi_u32 v6, v14, v6 +; GISEL-NEXT: v_mul_lo_u32 v14, v16, v9 ; GISEL-NEXT: v_mul_hi_u32 v16, v16, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v5, v9 -; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v19, v15 +; GISEL-NEXT: v_add_i32_e64 v15, s[8:9], v18, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v7, s[8:9], v7, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v13, s[8:9], v14, v13 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v15, s[8:9], v15, v19 +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[8:9] +; GISEL-NEXT: v_add_i32_e64 v7, s[8:9], v7, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[8:9] ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v15, v9 -; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v19, v15 -; GISEL-NEXT: v_mov_b32_e32 v19, s13 -; GISEL-NEXT: v_add_i32_e64 v6, s[6:7], v6, v17 -; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] -; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], v13, v17 -; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v15, v18 +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v13, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v18, v15 +; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v12, v10 +; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v17, v19 ; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], v14, v13 -; GISEL-NEXT: v_add_i32_e64 v14, s[6:7], v16, v15 -; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc -; GISEL-NEXT: v_addc_u32_e64 v11, vcc, v11, v14, s[4:5] -; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6 -; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc -; GISEL-NEXT: v_mul_lo_u32 v8, 0, v1 -; GISEL-NEXT: v_mul_hi_u32 v13, v0, v1 +; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v7, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v10, v14 +; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v13, v12 +; GISEL-NEXT: v_add_i32_e64 v6, s[6:7], v6, v10 +; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v16, v12 +; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v8, v6, vcc +; GISEL-NEXT: v_addc_u32_e64 v8, vcc, v11, v10, s[4:5] +; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v7 +; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc +; GISEL-NEXT: v_mul_lo_u32 v7, 0, v1 +; GISEL-NEXT: v_mul_hi_u32 v10, v0, v1 ; GISEL-NEXT: v_mul_hi_u32 v1, 0, v1 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9 -; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v11, vcc -; GISEL-NEXT: v_mul_lo_u32 v11, 0, v5 -; GISEL-NEXT: v_mul_hi_u32 v14, v2, v5 +; GISEL-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc +; GISEL-NEXT: v_mul_lo_u32 v9, 0, v5 +; GISEL-NEXT: v_mul_hi_u32 v11, v2, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, 0, v5 -; GISEL-NEXT: v_mul_lo_u32 v15, v0, v6 -; GISEL-NEXT: v_mul_lo_u32 v16, 0, v6 -; GISEL-NEXT: v_mul_hi_u32 v17, v0, v6 +; GISEL-NEXT: v_mul_lo_u32 v12, v0, v6 +; GISEL-NEXT: v_mul_lo_u32 v13, 0, v6 +; GISEL-NEXT: v_mul_hi_u32 v14, v0, v6 ; GISEL-NEXT: v_mul_hi_u32 v6, 0, v6 -; GISEL-NEXT: v_mul_lo_u32 v18, v2, v9 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18 -; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 -; GISEL-NEXT: v_mul_lo_u32 v11, 0, v9 -; GISEL-NEXT: v_mul_hi_u32 v14, v2, v9 -; GISEL-NEXT: v_mul_hi_u32 v9, 0, v9 -; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v15 -; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v1, s[4:5], v16, v1 -; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 -; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v13 -; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] -; GISEL-NEXT: v_add_i32_e64 v1, s[4:5], v1, v17 -; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v14 -; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v8, vcc, v15, v8 -; GISEL-NEXT: v_add_i32_e32 v13, vcc, v16, v13 -; GISEL-NEXT: v_add_i32_e32 v15, vcc, v18, v17 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 -; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v8 -; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v15 -; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc -; GISEL-NEXT: v_add_i32_e32 v8, vcc, v13, v8 -; GISEL-NEXT: v_mul_lo_u32 v13, v3, v1 -; GISEL-NEXT: v_mul_lo_u32 v15, 0, v1 +; GISEL-NEXT: v_mul_lo_u32 v15, v2, v8 +; GISEL-NEXT: v_mul_lo_u32 v16, 0, v8 +; GISEL-NEXT: v_mul_hi_u32 v17, v2, v8 +; GISEL-NEXT: v_mul_hi_u32 v8, 0, v8 +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1 +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15 +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v16, v5 +; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11 +; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v17 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v12, v7 +; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v15, v9 +; GISEL-NEXT: v_add_i32_e32 v11, vcc, v16, v11 +; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v7 +; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9 +; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v10, v7 +; GISEL-NEXT: v_mul_lo_u32 v10, v3, v1 +; GISEL-NEXT: v_mul_lo_u32 v12, 0, v1 ; GISEL-NEXT: v_mul_hi_u32 v1, v3, v1 -; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 -; GISEL-NEXT: v_mul_lo_u32 v14, v4, v5 -; GISEL-NEXT: v_mul_lo_u32 v16, 0, v5 +; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9 +; GISEL-NEXT: v_mul_lo_u32 v11, v4, v5 +; GISEL-NEXT: v_mul_lo_u32 v13, 0, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5 -; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v11 +; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v9 ; GISEL-NEXT: v_mul_lo_u32 v6, v3, v6 -; GISEL-NEXT: v_mul_lo_u32 v8, v4, v8 -; GISEL-NEXT: v_add_i32_e32 v6, vcc, v15, v6 -; GISEL-NEXT: v_add_i32_e32 v8, vcc, v16, v8 +; GISEL-NEXT: v_mul_lo_u32 v7, v4, v7 +; GISEL-NEXT: v_add_i32_e32 v6, vcc, v12, v6 +; GISEL-NEXT: v_add_i32_e32 v7, vcc, v13, v7 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v6, v1 -; GISEL-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v13 +; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v10 ; GISEL-NEXT: v_subb_u32_e64 v6, s[4:5], 0, v1, vcc ; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], 0, v1 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3 -; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] -; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v14 -; GISEL-NEXT: v_subb_u32_e64 v9, s[6:7], 0, v5, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] +; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v11 +; GISEL-NEXT: v_subb_u32_e64 v8, s[6:7], 0, v5, s[4:5] ; GISEL-NEXT: v_sub_i32_e64 v5, s[6:7], 0, v5 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v4 -; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[6:7] -; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6 -; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[6:7] +; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7] +; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], 0, v6 +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[6:7] ; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 -; GISEL-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v8 +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc ; GISEL-NEXT: v_subbrev_u32_e64 v5, vcc, 0, v5, s[4:5] -; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v0, v3 +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 +; GISEL-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc +; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v0, v3 ; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v11, v3 +; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v10, v3 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc -; GISEL-NEXT: v_sub_i32_e32 v13, vcc, v2, v4 +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8 +; GISEL-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc +; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v2, v4 ; GISEL-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc -; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v13, v4 +; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v11, v4 +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, vcc +; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v10, v3 +; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc +; GISEL-NEXT: v_cmp_le_u32_e32 vcc, 0, v5 +; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, -1, vcc +; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v11, v4 +; GISEL-NEXT: v_subbrev_u32_e32 v17, vcc, 0, v5, vcc ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc -; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v11, v3 -; GISEL-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v1, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 -; GISEL-NEXT: v_cndmask_b32_e32 v14, v19, v14, vcc -; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v13, v4 -; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v5, vcc -; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 -; GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc -; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v14 -; GISEL-NEXT: v_cndmask_b32_e64 v4, v13, v4, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 +; GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc +; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v13 +; GISEL-NEXT: v_cndmask_b32_e64 v4, v11, v4, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, v15, s[4:5] -; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8 +; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, v17, s[4:5] +; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GISEL-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5] ; GISEL-NEXT: s_setpc_b64 s[30:31] ; ; CGP-LABEL: v_urem_v2i64_24bit: -- 2.7.4