From 527d3523fc801029f5c1f4a34809e3f0a57869d0 Mon Sep 17 00:00:00 2001 From: Zhigang Gong Date: Fri, 20 Dec 2013 09:31:04 +0800 Subject: [PATCH] GBE: we should allocate register for ExtractElement insn. We should allocate register when we firstly visit ExtractElement instruction, as we may refer the value before we visit that instruction at the emit instruction pass. The case which trigger this corner case is as below: Clang/llvm may generate some code similar to the following IRs: ... (there is no definition of %7) br label 2 label1: %10 = add i32 %7, %6 ... ret label2: %8 = load <4 x i8> addrspace(1)* %3, align 4, !tbaa !1 %7 = extractelement <4 x i8> %8, i32 0 ... br label1 The value %7 is assigned after label2 but is referred at label1. From the control flow, the IRs is valid. As the reference will be executed after the assignment. But the previous implementation doesn't allocate proxyvalue for %7, that's the root cause why it triggers an assert when visit the instruction %10 = add i32 %7, %6 Signed-off-by: Zhigang Gong Reviewed-by: "Yang, Rong R" --- backend/src/llvm/llvm_gen_backend.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp index 0d4fb87..18e6967 100644 --- a/backend/src/llvm/llvm_gen_backend.cpp +++ b/backend/src/llvm/llvm_gen_backend.cpp @@ -1846,8 +1846,7 @@ namespace gbe } } - void GenWriter::regAllocateExtractElement(ExtractElementInst &I) {} - void GenWriter::emitExtractElement(ExtractElementInst &I) { + void GenWriter::regAllocateExtractElement(ExtractElementInst &I) { Value *vec = I.getVectorOperand(); const Value *index = I.getIndexOperand(); const ConstantInt *c = dyn_cast(index); @@ -1856,6 +1855,9 @@ namespace gbe regTranslator.newValueProxy(vec, &I, i, 0); } + void GenWriter::emitExtractElement(ExtractElementInst &I) { + } + void GenWriter::regAllocateShuffleVectorInst(ShuffleVectorInst &I) {} void GenWriter::emitShuffleVectorInst(ShuffleVectorInst &I) {} -- 2.7.4