From 52708be182e57dbe98972815ca807dc762dced12 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 22 Sep 2022 11:57:21 -0700 Subject: [PATCH] [RISCV] Remove support for the unratified Zbe, Zbf, and Zbm extensions. These extensions do not appear to be on their way to ratification. --- clang/include/clang/Basic/BuiltinsRISCV.def | 23 ----- clang/lib/CodeGen/CGBuiltin.cpp | 56 ------------ .../CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c | 33 ------- .../CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c | 18 ---- .../CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c | 75 ---------------- .../CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c | 63 ------------- .../CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c | 33 ------- .../CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c | 99 -------------------- clang/test/Driver/riscv-arch.c | 18 ++-- clang/test/Preprocessor/riscv-target-features.c | 50 ----------- llvm/docs/RISCVUsage.rst | 3 - llvm/docs/ReleaseNotes.rst | 6 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 21 ----- llvm/lib/Support/RISCVISAInfo.cpp | 8 +- llvm/lib/Target/RISCV/RISCV.td | 28 ------ llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 63 ------------- llvm/lib/Target/RISCV/RISCVISelLowering.h | 15 ---- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 100 --------------------- llvm/lib/Target/RISCV/RISCVSchedRocket.td | 3 - llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 3 - llvm/lib/Target/RISCV/RISCVScheduleB.td | 58 ------------ llvm/lib/Target/RISCV/RISCVSubtarget.h | 8 -- llvm/test/CodeGen/RISCV/attributes.ll | 16 ---- llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll | 25 ------ llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll | 14 --- llvm/test/CodeGen/RISCV/rv32zbr.ll | 69 -------------- llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll | 73 --------------- llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll | 25 ------ llvm/test/CodeGen/RISCV/rv64zbr.ll | 91 ------------------- llvm/test/MC/RISCV/attribute-arch-invalid.s | 12 --- llvm/test/MC/RISCV/attribute-arch.s | 15 ---- llvm/test/MC/RISCV/rv32zbe-invalid.s | 8 -- llvm/test/MC/RISCV/rv32zbe-valid.s | 18 ---- llvm/test/MC/RISCV/rv32zbf-invalid.s | 5 -- llvm/test/MC/RISCV/rv32zbf-valid.s | 15 ---- llvm/test/MC/RISCV/rv32zbr-invalid.s | 16 ---- llvm/test/MC/RISCV/rv32zbr-valid.s | 25 ------ llvm/test/MC/RISCV/rv64zbe-invalid.s | 6 -- llvm/test/MC/RISCV/rv64zbe-valid.s | 13 --- llvm/test/MC/RISCV/rv64zbf-invalid.s | 4 - llvm/test/MC/RISCV/rv64zbf-valid.s | 10 --- llvm/test/MC/RISCV/rv64zbm-invalid.s | 8 -- llvm/test/MC/RISCV/rv64zbm-valid.s | 16 ---- llvm/test/MC/RISCV/rv64zbr-invalid.s | 6 -- llvm/test/MC/RISCV/rv64zbr-valid.s | 31 ------- 45 files changed, 13 insertions(+), 1292 deletions(-) delete mode 100644 clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c delete mode 100644 clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c delete mode 100644 clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c delete mode 100644 clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c delete mode 100644 clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c delete mode 100644 clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c delete mode 100644 llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll delete mode 100644 llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll delete mode 100644 llvm/test/CodeGen/RISCV/rv32zbr.ll delete mode 100644 llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll delete mode 100644 llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll delete mode 100644 llvm/test/CodeGen/RISCV/rv64zbr.ll delete mode 100644 llvm/test/MC/RISCV/rv32zbe-invalid.s delete mode 100644 llvm/test/MC/RISCV/rv32zbe-valid.s delete mode 100644 llvm/test/MC/RISCV/rv32zbf-invalid.s delete mode 100644 llvm/test/MC/RISCV/rv32zbf-valid.s delete mode 100644 llvm/test/MC/RISCV/rv32zbr-invalid.s delete mode 100644 llvm/test/MC/RISCV/rv32zbr-valid.s delete mode 100644 llvm/test/MC/RISCV/rv64zbe-invalid.s delete mode 100644 llvm/test/MC/RISCV/rv64zbe-valid.s delete mode 100644 llvm/test/MC/RISCV/rv64zbf-invalid.s delete mode 100644 llvm/test/MC/RISCV/rv64zbf-valid.s delete mode 100644 llvm/test/MC/RISCV/rv64zbm-invalid.s delete mode 100644 llvm/test/MC/RISCV/rv64zbm-valid.s delete mode 100644 llvm/test/MC/RISCV/rv64zbr-invalid.s delete mode 100644 llvm/test/MC/RISCV/rv64zbr-valid.s diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def index f51cba9..c26e3b8 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.def +++ b/clang/include/clang/Basic/BuiltinsRISCV.def @@ -32,29 +32,6 @@ TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "zbc") TARGET_BUILTIN(__builtin_riscv_xperm4, "LiLiLi", "nc", "zbkx") TARGET_BUILTIN(__builtin_riscv_xperm8, "LiLiLi", "nc", "zbkx") -// Zbe extension -TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe") -TARGET_BUILTIN(__builtin_riscv_bcompress_64, "WiWiWi", "nc", - "experimental-zbe,64bit") -TARGET_BUILTIN(__builtin_riscv_bdecompress_32, "ZiZiZi", "nc", - "experimental-zbe") -TARGET_BUILTIN(__builtin_riscv_bdecompress_64, "WiWiWi", "nc", - "experimental-zbe,64bit") - -// Zbf extension -TARGET_BUILTIN(__builtin_riscv_bfp_32, "ZiZiZi", "nc", "experimental-zbf") -TARGET_BUILTIN(__builtin_riscv_bfp_64, "WiWiWi", "nc", "experimental-zbf,64bit") - -// Zbr extension -TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr,64bit") -TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr,64bit") - // Zbkb extension TARGET_BUILTIN(__builtin_riscv_brev8, "LiLi", "nc", "zbkb") TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb,32bit") diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 43361b5..a43c50a 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -19186,22 +19186,8 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_clmul: case RISCV::BI__builtin_riscv_clmulh: case RISCV::BI__builtin_riscv_clmulr: - case RISCV::BI__builtin_riscv_bcompress_32: - case RISCV::BI__builtin_riscv_bcompress_64: - case RISCV::BI__builtin_riscv_bdecompress_32: - case RISCV::BI__builtin_riscv_bdecompress_64: - case RISCV::BI__builtin_riscv_bfp_32: - case RISCV::BI__builtin_riscv_bfp_64: case RISCV::BI__builtin_riscv_xperm4: case RISCV::BI__builtin_riscv_xperm8: - case RISCV::BI__builtin_riscv_crc32_b: - case RISCV::BI__builtin_riscv_crc32_h: - case RISCV::BI__builtin_riscv_crc32_w: - case RISCV::BI__builtin_riscv_crc32_d: - case RISCV::BI__builtin_riscv_crc32c_b: - case RISCV::BI__builtin_riscv_crc32c_h: - case RISCV::BI__builtin_riscv_crc32c_w: - case RISCV::BI__builtin_riscv_crc32c_d: case RISCV::BI__builtin_riscv_brev8: case RISCV::BI__builtin_riscv_zip_32: case RISCV::BI__builtin_riscv_unzip_32: { @@ -19234,48 +19220,6 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, ID = Intrinsic::riscv_clmulr; break; - // Zbe - case RISCV::BI__builtin_riscv_bcompress_32: - case RISCV::BI__builtin_riscv_bcompress_64: - ID = Intrinsic::riscv_bcompress; - break; - case RISCV::BI__builtin_riscv_bdecompress_32: - case RISCV::BI__builtin_riscv_bdecompress_64: - ID = Intrinsic::riscv_bdecompress; - break; - - // Zbf - case RISCV::BI__builtin_riscv_bfp_32: - case RISCV::BI__builtin_riscv_bfp_64: - ID = Intrinsic::riscv_bfp; - break; - - // Zbr - case RISCV::BI__builtin_riscv_crc32_b: - ID = Intrinsic::riscv_crc32_b; - break; - case RISCV::BI__builtin_riscv_crc32_h: - ID = Intrinsic::riscv_crc32_h; - break; - case RISCV::BI__builtin_riscv_crc32_w: - ID = Intrinsic::riscv_crc32_w; - break; - case RISCV::BI__builtin_riscv_crc32_d: - ID = Intrinsic::riscv_crc32_d; - break; - case RISCV::BI__builtin_riscv_crc32c_b: - ID = Intrinsic::riscv_crc32c_b; - break; - case RISCV::BI__builtin_riscv_crc32c_h: - ID = Intrinsic::riscv_crc32c_h; - break; - case RISCV::BI__builtin_riscv_crc32c_w: - ID = Intrinsic::riscv_crc32c_w; - break; - case RISCV::BI__builtin_riscv_crc32c_d: - ID = Intrinsic::riscv_crc32c_d; - break; - // Zbkx case RISCV::BI__builtin_riscv_xperm8: ID = Intrinsic::riscv_xperm8; diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c deleted file mode 100644 index abbb54e..0000000 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c +++ /dev/null @@ -1,33 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple riscv32 -target-feature +experimental-zbe -emit-llvm %s -o - \ -// RUN: | FileCheck %s -check-prefix=RV32ZBE - -// RV32ZBE-LABEL: @bcompress( -// RV32ZBE-NEXT: entry: -// RV32ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 -// RV32ZBE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4 -// RV32ZBE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 -// RV32ZBE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4 -// RV32ZBE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bcompress.i32(i32 [[TMP0]], i32 [[TMP1]]) -// RV32ZBE-NEXT: ret i32 [[TMP2]] -// -long bcompress(long rs1, long rs2) { - return __builtin_riscv_bcompress_32(rs1, rs2); -} - -// RV32ZBE-LABEL: @bdecompress( -// RV32ZBE-NEXT: entry: -// RV32ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 -// RV32ZBE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4 -// RV32ZBE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 -// RV32ZBE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4 -// RV32ZBE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bdecompress.i32(i32 [[TMP0]], i32 [[TMP1]]) -// RV32ZBE-NEXT: ret i32 [[TMP2]] -// -long bdecompress(long rs1, long rs2) { - return __builtin_riscv_bdecompress_32(rs1, rs2); -} diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c deleted file mode 100644 index e7afb0d..0000000 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c +++ /dev/null @@ -1,18 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple riscv32 -target-feature +experimental-zbf -emit-llvm %s -o - \ -// RUN: | FileCheck %s -check-prefix=RV32ZBF - -// RV32ZBF-LABEL: @bfp32( -// RV32ZBF-NEXT: entry: -// RV32ZBF-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBF-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBF-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 -// RV32ZBF-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4 -// RV32ZBF-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// RV32ZBF-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// RV32ZBF-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bfp.i32(i32 [[TMP0]], i32 [[TMP1]]) -// RV32ZBF-NEXT: ret i32 [[TMP2]] -// -int bfp32(int a, int b) { - return __builtin_riscv_bfp_32(a, b); -} diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c deleted file mode 100644 index b4e496f..0000000 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c +++ /dev/null @@ -1,75 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple riscv32 -target-feature +experimental-zbr -emit-llvm %s -o - \ -// RUN: | FileCheck %s -check-prefix=RV32ZBR - -// RV32ZBR-LABEL: @crc32_b( -// RV32ZBR-NEXT: entry: -// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.b.i32(i32 [[TMP0]]) -// RV32ZBR-NEXT: ret i32 [[TMP1]] -// -long crc32_b(long a) { - return __builtin_riscv_crc32_b(a); -} - -// RV32ZBR-LABEL: @crc32_h( -// RV32ZBR-NEXT: entry: -// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.h.i32(i32 [[TMP0]]) -// RV32ZBR-NEXT: ret i32 [[TMP1]] -// -long crc32_h(long a) { - return __builtin_riscv_crc32_h(a); -} - -// RV32ZBR-LABEL: @crc32_w( -// RV32ZBR-NEXT: entry: -// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.w.i32(i32 [[TMP0]]) -// RV32ZBR-NEXT: ret i32 [[TMP1]] -// -long crc32_w(long a) { - return __builtin_riscv_crc32_w(a); -} - -// RV32ZBR-LABEL: @crc32c_b( -// RV32ZBR-NEXT: entry: -// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.b.i32(i32 [[TMP0]]) -// RV32ZBR-NEXT: ret i32 [[TMP1]] -// -long crc32c_b(long a) { - return __builtin_riscv_crc32c_b(a); -} - -// RV32ZBR-LABEL: @crc32c_h( -// RV32ZBR-NEXT: entry: -// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.h.i32(i32 [[TMP0]]) -// RV32ZBR-NEXT: ret i32 [[TMP1]] -// -long crc32c_h(long a) { - return __builtin_riscv_crc32c_h(a); -} - -// RV32ZBR-LABEL: @crc32c_w( -// RV32ZBR-NEXT: entry: -// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.w.i32(i32 [[TMP0]]) -// RV32ZBR-NEXT: ret i32 [[TMP1]] -// -long crc32c_w(long a) { - return __builtin_riscv_crc32c_w(a); -} diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c deleted file mode 100644 index 64b6d31..0000000 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c +++ /dev/null @@ -1,63 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +experimental-zbe -emit-llvm %s -o - \ -// RUN: | FileCheck %s -check-prefix=RV64ZBE - -// RV64ZBE-LABEL: @bcompressw( -// RV64ZBE-NEXT: entry: -// RV64ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 -// RV64ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 -// RV64ZBE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 -// RV64ZBE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4 -// RV64ZBE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 -// RV64ZBE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4 -// RV64ZBE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bcompress.i32(i32 [[TMP0]], i32 [[TMP1]]) -// RV64ZBE-NEXT: ret i32 [[TMP2]] -// -int bcompressw(int rs1, int rs2) { - return __builtin_riscv_bcompress_32(rs1, rs2); -} - -// RV64ZBE-LABEL: @bdecompressw( -// RV64ZBE-NEXT: entry: -// RV64ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 -// RV64ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 -// RV64ZBE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 -// RV64ZBE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4 -// RV64ZBE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 -// RV64ZBE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4 -// RV64ZBE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bdecompress.i32(i32 [[TMP0]], i32 [[TMP1]]) -// RV64ZBE-NEXT: ret i32 [[TMP2]] -// -int bdecompressw(int rs1, int rs2) { - return __builtin_riscv_bdecompress_32(rs1, rs2); -} - -// RV64ZBE-LABEL: @bcompress( -// RV64ZBE-NEXT: entry: -// RV64ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBE-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8 -// RV64ZBE-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8 -// RV64ZBE-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8 -// RV64ZBE-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8 -// RV64ZBE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.bcompress.i64(i64 [[TMP0]], i64 [[TMP1]]) -// RV64ZBE-NEXT: ret i64 [[TMP2]] -// -long bcompress(long rs1, long rs2) { - return __builtin_riscv_bcompress_64(rs1, rs2); -} - -// RV64ZBE-LABEL: @bdecompress( -// RV64ZBE-NEXT: entry: -// RV64ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBE-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8 -// RV64ZBE-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8 -// RV64ZBE-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8 -// RV64ZBE-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8 -// RV64ZBE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.bdecompress.i64(i64 [[TMP0]], i64 [[TMP1]]) -// RV64ZBE-NEXT: ret i64 [[TMP2]] -// -long bdecompress(long rs1, long rs2) { - return __builtin_riscv_bdecompress_64(rs1, rs2); -} diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c deleted file mode 100644 index 46d7d31..0000000 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c +++ /dev/null @@ -1,33 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +experimental-zbf -emit-llvm %s -o - \ -// RUN: | FileCheck %s -check-prefix=RV64ZBF - -// RV64ZBF-LABEL: @bfp32( -// RV64ZBF-NEXT: entry: -// RV64ZBF-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV64ZBF-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// RV64ZBF-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 -// RV64ZBF-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4 -// RV64ZBF-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// RV64ZBF-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// RV64ZBF-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bfp.i32(i32 [[TMP0]], i32 [[TMP1]]) -// RV64ZBF-NEXT: ret i32 [[TMP2]] -// -int bfp32(int a, int b) { - return __builtin_riscv_bfp_32(a, b); -} - -// RV64ZBF-LABEL: @bfp64( -// RV64ZBF-NEXT: entry: -// RV64ZBF-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBF-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBF-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 -// RV64ZBF-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8 -// RV64ZBF-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// RV64ZBF-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8 -// RV64ZBF-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.bfp.i64(i64 [[TMP0]], i64 [[TMP1]]) -// RV64ZBF-NEXT: ret i64 [[TMP2]] -// -long bfp64(long a, long b) { - return __builtin_riscv_bfp_64(a, b); -} diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c deleted file mode 100644 index 992c670..0000000 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c +++ /dev/null @@ -1,99 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +experimental-zbr -emit-llvm %s -o - \ -// RUN: | FileCheck %s -check-prefix=RV64ZBR - -// RV64ZBR-LABEL: @crc32_b( -// RV64ZBR-NEXT: entry: -// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.b.i64(i64 [[TMP0]]) -// RV64ZBR-NEXT: ret i64 [[TMP1]] -// -long crc32_b(long a) { - return __builtin_riscv_crc32_b(a); -} - -// RV64ZBR-LABEL: @crc32_h( -// RV64ZBR-NEXT: entry: -// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.h.i64(i64 [[TMP0]]) -// RV64ZBR-NEXT: ret i64 [[TMP1]] -// -long crc32_h(long a) { - return __builtin_riscv_crc32_h(a); -} - -// RV64ZBR-LABEL: @crc32_w( -// RV64ZBR-NEXT: entry: -// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.w.i64(i64 [[TMP0]]) -// RV64ZBR-NEXT: ret i64 [[TMP1]] -// -long crc32_w(long a) { - return __builtin_riscv_crc32_w(a); -} - -// RV64ZBR-LABEL: @crc32c_b( -// RV64ZBR-NEXT: entry: -// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.b.i64(i64 [[TMP0]]) -// RV64ZBR-NEXT: ret i64 [[TMP1]] -// -long crc32c_b(long a) { - return __builtin_riscv_crc32c_b(a); -} - -// RV64ZBR-LABEL: @crc32c_h( -// RV64ZBR-NEXT: entry: -// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.h.i64(i64 [[TMP0]]) -// RV64ZBR-NEXT: ret i64 [[TMP1]] -// -long crc32c_h(long a) { - return __builtin_riscv_crc32c_h(a); -} - -// RV64ZBR-LABEL: @crc32c_w( -// RV64ZBR-NEXT: entry: -// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.w.i64(i64 [[TMP0]]) -// RV64ZBR-NEXT: ret i64 [[TMP1]] -// -long crc32c_w(long a) { - return __builtin_riscv_crc32c_w(a); -} - -// RV64ZBR-LABEL: @crc32_d( -// RV64ZBR-NEXT: entry: -// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.d.i64(i64 [[TMP0]]) -// RV64ZBR-NEXT: ret i64 [[TMP1]] -// -long crc32_d(long a) { - return __builtin_riscv_crc32_d(a); -} - -// RV64ZBR-LABEL: @crc32c_d( -// RV64ZBR-NEXT: entry: -// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.d.i64(i64 [[TMP0]]) -// RV64ZBR-NEXT: ret i64 [[TMP1]] -// -long crc32c_d(long a) { - return __builtin_riscv_crc32c_d(a); -} diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 37bd7e2..7e86423 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -412,24 +412,24 @@ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s // RV32-ZFHMIN: "-target-feature" "+zfhmin" -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s -// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izbt' +// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izca' // RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -menable-experimental-extensions -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s -// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izbt' +// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izca' // RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p1 -menable-experimental-extensions -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca0p1 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s -// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izbt0p1' -// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zbt' (this compiler supports 0.93) +// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izca0p1' +// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zca' (this compiler supports 0.70) -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p93 -menable-experimental-extensions -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca0p70 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s -// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zbt" +// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zca" // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index a925c45..c1c29da 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -22,12 +22,7 @@ // CHECK-NOT: __riscv_zba // CHECK-NOT: __riscv_zbb // CHECK-NOT: __riscv_zbc -// CHECK-NOT: __riscv_zbe -// CHECK-NOT: __riscv_zbf -// CHECK-NOT: __riscv_zbm -// CHECK-NOT: __riscv_zbr // CHECK-NOT: __riscv_zbs -// CHECK-NOT: __riscv_zbt // CHECK-NOT: __riscv_zfh // CHECK-NOT: __riscv_v // CHECK-NOT: __riscv_vector @@ -163,42 +158,6 @@ // CHECK-ZBC-NOT: __riscv_b // CHECK-ZBC-EXT: __riscv_zbc 1000000{{$}} -// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbe0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZBE-EXT %s -// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbe0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZBE-EXT %s -// CHECK-ZBE-NOT: __riscv_b -// CHECK-ZBE-EXT: __riscv_zbe 93000{{$}} - -// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbf0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZBF-EXT %s -// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbf0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZBF-EXT %s -// CHECK-ZBF-NOT: __riscv_b -// CHECK-ZBF-EXT: __riscv_zbf 93000{{$}} - -// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbm0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZBM-EXT %s -// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbm0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZBM-EXT %s -// CHECK-ZBM-NOT: __riscv_b -// CHECK-ZBM-EXT: __riscv_zbm 93000{{$}} - -// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbr0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s -// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbr0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s -// CHECK-ZBR-NOT: __riscv_b -// CHECK-ZBR-EXT: __riscv_zbr 93000{{$}} - // RUN: %clang -target riscv32-unknown-linux-gnu \ // RUN: -march=rv32izbs1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s @@ -214,15 +173,6 @@ // CHECK-ZBS-NOT: __riscv_b // CHECK-ZBS-EXT: __riscv_zbs 1000000{{$}} -// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbt0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZBT-EXT %s -// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbt0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZBT-EXT %s -// CHECK-ZBT-NOT: __riscv_b -// CHECK-ZBT-EXT: __riscv_zbt 93000{{$}} - // RUN: %clang -target riscv32-unknown-linux-gnu \ // RUN: -march=rv32iv1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 754360f..f5234ec 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -131,9 +131,6 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zawrs`` LLVM implements the `1.0-rc3 draft specification `_. Note that have been backwards incompatible changes made between release candidates for the 1.0 draft. -``experimental-zbe``, ``experimental-zbf``, ``experimental-zbm``, ``experimental-zbr`` - LLVM implements the `latest state of the bitmanip working branch `_, which is largely similar to the 0.93 draft specification but with some instruction naming changes. These are individual portions of the bitmanip efforts which did *not* get ratified. Given ratification for these sub-extensions appears stalled; they are a likely candidate for removal in the future. - ``experimental-zca`` LLVM implements the `0.70 draft specification `_. diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index ca7444d..99e1e9d 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -62,7 +62,7 @@ and there is no way to suppress this error. Changes to the LLVM IR ---------------------- -* The constant expression variants of the following instructions have been +* The constant expression variants of the following instructions has been removed: * ``fneg`` @@ -112,8 +112,8 @@ Changes to the PowerPC Backend Changes to the RISC-V Backend ----------------------------- -* Support the unratified Zbp extension has been removed. -* Support the unratified Zbt extension has been removed. +* Support for the unratified Zbe, Zbf, Zbm, Zbp, and Zbt extensions have been + removed. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 3b0f64e..002920a 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -87,10 +87,6 @@ let TargetPrefix = "riscv" in { : Intrinsic<[llvm_any_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; - class BitManipGPRGPRGRIntrinsics - : Intrinsic<[llvm_any_ty], - [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], - [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; // Zbb def int_riscv_orc_b : BitManipGPRIntrinsics; @@ -102,23 +98,6 @@ let TargetPrefix = "riscv" in { // Zbc def int_riscv_clmulr : BitManipGPRGPRIntrinsics; - // Zbe - def int_riscv_bcompress : BitManipGPRGPRIntrinsics; - def int_riscv_bdecompress : BitManipGPRGPRIntrinsics; - - // Zbf - def int_riscv_bfp : BitManipGPRGPRIntrinsics; - - // Zbr - def int_riscv_crc32_b : BitManipGPRIntrinsics; - def int_riscv_crc32_h : BitManipGPRIntrinsics; - def int_riscv_crc32_w : BitManipGPRIntrinsics; - def int_riscv_crc32_d : BitManipGPRIntrinsics; - def int_riscv_crc32c_b : BitManipGPRIntrinsics; - def int_riscv_crc32c_h : BitManipGPRIntrinsics; - def int_riscv_crc32c_w : BitManipGPRIntrinsics; - def int_riscv_crc32c_d : BitManipGPRIntrinsics; - // Zbkb def int_riscv_brev8 : BitManipGPRIntrinsics; def int_riscv_zip : BitManipGPRIntrinsics; diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index a9ae607..9cf7e04 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -106,12 +106,6 @@ static const RISCVSupportedExtension SupportedExtensions[] = { static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zihintntl", RISCVExtensionVersion{0, 2}}, - {"zbe", RISCVExtensionVersion{0, 93}}, - {"zbf", RISCVExtensionVersion{0, 93}}, - {"zbm", RISCVExtensionVersion{0, 93}}, - {"zbp", RISCVExtensionVersion{0, 93}}, - {"zbr", RISCVExtensionVersion{0, 93}}, - {"zbt", RISCVExtensionVersion{0, 93}}, {"zca", RISCVExtensionVersion{0, 70}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"zawrs", RISCVExtensionVersion{1, 0}}, @@ -123,7 +117,7 @@ static bool stripExperimentalPrefix(StringRef &Ext) { } // This function finds the first character that doesn't belong to a version -// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will +// (e.g. zba1p0 is extension 'zba' of version '1p0'). So the function will // consume [0-9]*p[0-9]* starting from the backward. An extension name will not // end with a digit or the letter 'p', so this function will parse correctly. // NOTE: This function is NOT able to take empty strings or strings that only diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 593ecfa..438c614 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -153,34 +153,6 @@ def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, AssemblerPredicate<(all_of FeatureStdExtZbc), "'Zbc' (Carry-Less Multiplication)">; -def FeatureStdExtZbe - : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true", - "'Zbe' (Extract-Deposit 'Zb' Instructions)">; -def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">, - AssemblerPredicate<(all_of FeatureStdExtZbe), - "'Zbe' (Extract-Deposit 'Zb' Instructions)">; - -def FeatureStdExtZbf - : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true", - "'Zbf' (Bit-Field 'Zb' Instructions)">; -def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">, - AssemblerPredicate<(all_of FeatureStdExtZbf), - "'Zbf' (Bit-Field 'Zb' Instructions)">; - -def FeatureStdExtZbm - : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true", - "'Zbm' (Matrix 'Zb' Instructions)">; -def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">, - AssemblerPredicate<(all_of FeatureStdExtZbm), - "'Zbm' (Matrix 'Zb' Instructions)">; - -def FeatureStdExtZbr - : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true", - "'Zbr' (Polynomial Reduction 'Zb' Instructions)">; -def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">, - AssemblerPredicate<(all_of FeatureStdExtZbr), - "'Zbr' (Polynomial Reduction 'Zb' Instructions)">; - def FeatureStdExtZbs : SubtargetFeature<"zbs", "HasStdExtZbs", "true", "'Zbs' (Single-Bit Instructions)">; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index abeee98..9526226 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -5114,15 +5114,6 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, IntNo == Intrinsic::riscv_zip ? RISCVISD::ZIP : RISCVISD::UNZIP; return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1)); } - case Intrinsic::riscv_bcompress: - case Intrinsic::riscv_bdecompress: { - unsigned Opc = IntNo == Intrinsic::riscv_bcompress ? RISCVISD::BCOMPRESS - : RISCVISD::BDECOMPRESS; - return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2)); - } - case Intrinsic::riscv_bfp: - return DAG.getNode(RISCVISD::BFP, DL, XLenVT, Op.getOperand(1), - Op.getOperand(2)); case Intrinsic::riscv_vmv_x_s: assert(Op.getValueType() == XLenVT && "Unexpected VT!"); return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(), @@ -7058,34 +7049,6 @@ SDValue RISCVTargetLowering::lowerEH_DWARF_CFA(SDValue Op, return DAG.getFrameIndex(FI, PtrVT); } -static RISCVISD::NodeType getRISCVWOpcodeByIntr(unsigned IntNo) { - switch (IntNo) { - default: - llvm_unreachable("Unexpected Intrinsic"); - case Intrinsic::riscv_bcompress: - return RISCVISD::BCOMPRESSW; - case Intrinsic::riscv_bdecompress: - return RISCVISD::BDECOMPRESSW; - case Intrinsic::riscv_bfp: - return RISCVISD::BFPW; - } -} - -// Converts the given intrinsic to a i64 operation with any extension. -static SDValue customLegalizeToWOpByIntr(SDNode *N, SelectionDAG &DAG, - unsigned IntNo) { - SDLoc DL(N); - RISCVISD::NodeType WOpcode = getRISCVWOpcodeByIntr(IntNo); - // Deal with the Instruction Operands - SmallVector NewOps; - for (SDValue Op : drop_begin(N->ops())) - // Promote the operand to i64 type - NewOps.push_back(DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op)); - SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOps); - // ReplaceNodeResults requires we maintain the same type for the return value. - return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes); -} - // Returns the opcode of the target-specific SDNode that implements the 32-bit // form of the given Opcode. static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) { @@ -7541,14 +7504,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, default: llvm_unreachable( "Don't know how to custom type legalize this intrinsic!"); - case Intrinsic::riscv_bcompress: - case Intrinsic::riscv_bdecompress: - case Intrinsic::riscv_bfp: { - assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && - "Unexpected custom legalisation"); - Results.push_back(customLegalizeToWOpByIntr(N, DAG, IntNo)); - break; - } case Intrinsic::riscv_orc_b: { SDValue NewOp = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); @@ -8916,15 +8871,6 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, return SDValue(N, 0); break; } - case RISCVISD::BCOMPRESSW: - case RISCVISD::BDECOMPRESSW: { - // Only the lower 32 bits of LHS and RHS are read. - if (SimplifyDemandedLowBitsHelper(0, 32) || - SimplifyDemandedLowBitsHelper(1, 32)) - return SDValue(N, 0); - - break; - } case RISCVISD::FMV_X_ANYEXTH: case RISCVISD::FMV_X_ANYEXTW_RV64: { SDLoc DL(N); @@ -9615,9 +9561,6 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode( case RISCVISD::REMUW: case RISCVISD::ROLW: case RISCVISD::RORW: - case RISCVISD::BCOMPRESSW: - case RISCVISD::BDECOMPRESSW: - case RISCVISD::BFPW: case RISCVISD::FCVT_W_RV64: case RISCVISD::FCVT_WU_RV64: case RISCVISD::STRICT_FCVT_W_RV64: @@ -11670,12 +11613,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(ORC_B) NODE_NAME_CASE(ZIP) NODE_NAME_CASE(UNZIP) - NODE_NAME_CASE(BFP) - NODE_NAME_CASE(BFPW) - NODE_NAME_CASE(BCOMPRESS) - NODE_NAME_CASE(BCOMPRESSW) - NODE_NAME_CASE(BDECOMPRESS) - NODE_NAME_CASE(BDECOMPRESSW) NODE_NAME_CASE(VMV_V_X_VL) NODE_NAME_CASE(VFMV_V_F_VL) NODE_NAME_CASE(VMV_X_S) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 698aab6..f3b39d0 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -114,21 +114,6 @@ enum NodeType : unsigned { ORC_B, ZIP, UNZIP, - // Bit Compress/Decompress implement the generic bit extract and bit deposit - // functions. This operation is also referred to as bit gather/scatter, bit - // pack/unpack, parallel extract/deposit, compress/expand, or right - // compress/right expand. - BCOMPRESS, - BCOMPRESSW, - BDECOMPRESS, - BDECOMPRESSW, - // The bit field place (bfp) instruction places up to XLEN/2 LSB bits from rs2 - // into the value in rs1. The upper bits of rs2 control the length of the bit - // field and target position. The layout of rs2 is chosen in a way that makes - // it possible to construct rs2 easily using pack[h] instructions and/or - // andi/lui. - BFP, - BFPW, // Vector Extension // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand // for the VL value to be used for the operation. The first operand is diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td index 8b17976..6604c8b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -12,10 +12,6 @@ // Zbb - 1.0 // Zbc - 1.0 // Zbs - 1.0 -// Zbe - 0.93 *experimental -// Zbf - 0.93 *experimental -// Zbm - 0.93 *experimental -// Zbr - 0.93 *experimental // // The experimental extensions appeared in an earlier draft of the Bitmanip // extensions. They are not ratified and subject to change. @@ -41,12 +37,6 @@ def riscv_brev8 : SDNode<"RISCVISD::BREV8", SDTIntUnaryOp>; def riscv_orc_b : SDNode<"RISCVISD::ORC_B", SDTIntUnaryOp>; def riscv_zip : SDNode<"RISCVISD::ZIP", SDTIntUnaryOp>; def riscv_unzip : SDNode<"RISCVISD::UNZIP", SDTIntUnaryOp>; -def riscv_bfp : SDNode<"RISCVISD::BFP", SDTIntBinOp>; -def riscv_bfpw : SDNode<"RISCVISD::BFPW", SDT_RISCVIntBinOpW>; -def riscv_bcompress : SDNode<"RISCVISD::BCOMPRESS", SDTIntBinOp>; -def riscv_bcompressw : SDNode<"RISCVISD::BCOMPRESSW", SDT_RISCVIntBinOpW>; -def riscv_bdecompress : SDNode<"RISCVISD::BDECOMPRESS", SDTIntBinOp>; -def riscv_bdecompressw : SDNode<"RISCVISD::BDECOMPRESSW",SDT_RISCVIntBinOpW>; def UImmLog2XLenHalfAsmOperand : AsmOperandClass { let Name = "UImmLog2XLenHalf"; @@ -413,30 +403,6 @@ def SEXT_H : RVBUnary<0b0110000, 0b00101, 0b001, OPC_OP_IMM, "sext.h">, Sched<[WriteIALU, ReadIALU]>; } // Predicates = [HasStdExtZbb] -let Predicates = [HasStdExtZbr] in { -def CRC32_B : RVBUnary<0b0110000, 0b10000, 0b001, OPC_OP_IMM, "crc32.b">, - Sched<[WriteCRCB, ReadCRCB]>; -def CRC32_H : RVBUnary<0b0110000, 0b10001, 0b001, OPC_OP_IMM, "crc32.h">, - Sched<[WriteCRCH, ReadCRCH]>; -def CRC32_W : RVBUnary<0b0110000, 0b10010, 0b001, OPC_OP_IMM, "crc32.w">, - Sched<[WriteCRCW, ReadCRCW]>; - -def CRC32C_B : RVBUnary<0b0110000, 0b11000, 0b001, OPC_OP_IMM, "crc32c.b">, - Sched<[WriteCRCCB, ReadCRCCB]>; -def CRC32C_H : RVBUnary<0b0110000, 0b11001, 0b001, OPC_OP_IMM, "crc32c.h">, - Sched<[WriteCRCCH, ReadCRCCH]>; -def CRC32C_W : RVBUnary<0b0110000, 0b11010, 0b001, OPC_OP_IMM, "crc32c.w">, - Sched<[WriteCRCCW, ReadCRCCW]>; -} // Predicates = [HasStdExtZbr] - -let Predicates = [HasStdExtZbr, IsRV64] in { -def CRC32_D : RVBUnary<0b0110000, 0b10011, 0b001, OPC_OP_IMM, "crc32.d">, - Sched<[WriteCRCD, ReadCRCD]>; - -def CRC32C_D : RVBUnary<0b0110000, 0b11011, 0b001, OPC_OP_IMM, "crc32c.d">, - Sched<[WriteCRCCD, ReadCRCCD]>; -} // Predicates = [HasStdExtZbr, IsRV64] - let Predicates = [HasStdExtZbc] in { def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr", /*Commutable*/1>, Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>; @@ -460,24 +426,6 @@ def MAXU : ALU_rr<0b0000101, 0b111, "maxu", /*Commutable*/1>, Sched<[WriteIALU, ReadIALU, ReadIALU]>; } // Predicates = [HasStdExtZbb] -let Predicates = [HasStdExtZbe] in { -// NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with -// bext in the 0.93 spec. -def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, - Sched<[WriteDecompress, ReadDecompress, ReadDecompress]>; -def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, - Sched<[WriteCompress, ReadCompress, ReadCompress]>; -} // Predicates = [HasStdExtZbe] - -let Predicates = [HasStdExtZbe, IsRV64] in { -// NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with -// bextw in the 0.93 spec. -def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, - Sched<[WriteDecompress32, ReadDecompress32, ReadDecompress32]>; -def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, - Sched<[WriteCompress32, ReadCompress32, ReadCompress32]>; -} // Predicates = [HasStdExtZbe, IsRV64] - let Predicates = [HasStdExtZbkb] in { def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[WritePACK, ReadPACK, ReadPACK]>; @@ -489,24 +437,6 @@ let Predicates = [HasStdExtZbkb, IsRV64] in def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[WritePACK32, ReadPACK32, ReadPACK32]>; -let Predicates = [HasStdExtZbm, IsRV64] in { -def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, OPC_OP_IMM, "bmatflip">, - Sched<[WriteBMatrix, ReadBMatrix]>; - -def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, - Sched<[WriteBMatrix, ReadBMatrix, ReadBMatrix]>; -def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, - Sched<[WriteBMatrix, ReadBMatrix, ReadBMatrix]>; -} // Predicates = [HasStdExtZbm, IsRV64] - -let Predicates = [HasStdExtZbf] in -def BFP : ALU_rr<0b0100100, 0b111, "bfp">, - Sched<[WriteBFP, ReadBFP, ReadBFP]>; - -let Predicates = [HasStdExtZbf, IsRV64] in -def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, - Sched<[WriteBFP32, ReadBFP32, ReadBFP32]>; - let Predicates = [HasStdExtZbb, IsRV32] in { def ZEXT_H_RV32 : RVBUnary<0b0000100, 0b00000, 0b100, OPC_OP, "zext.h">, Sched<[WriteIALU, ReadIALU]>; @@ -857,36 +787,6 @@ def : PatGprGpr; let Predicates = [HasStdExtZbc] in def : PatGprGpr; -let Predicates = [HasStdExtZbe] in { -def : PatGprGpr; -def : PatGprGpr; -} // Predicates = [HasStdExtZbe] - -let Predicates = [HasStdExtZbe, IsRV64] in { -def : PatGprGpr; -def : PatGprGpr; -} // Predicates = [HasStdExtZbe, IsRV64] - -let Predicates = [HasStdExtZbr] in { -def : PatGpr; -def : PatGpr; -def : PatGpr; -def : PatGpr; -def : PatGpr; -def : PatGpr; -} // Predicates = [HasStdExtZbr] - -let Predicates = [HasStdExtZbr, IsRV64] in { -def : PatGpr; -def : PatGpr; -} // Predicates = [HasStdExtZbr, IsRV64] - -let Predicates = [HasStdExtZbf] in -def : PatGprGpr; - -let Predicates = [HasStdExtZbf, IsRV64] in -def : PatGprGpr; - let Predicates = [HasStdExtZbkx] in { def : PatGprGpr; def : PatGprGpr; diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td index f457adc..9a8b5e9 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -243,9 +243,6 @@ defm : UnsupportedSchedZba; defm : UnsupportedSchedZbb; defm : UnsupportedSchedZbc; defm : UnsupportedSchedZbs; -defm : UnsupportedSchedZbe; -defm : UnsupportedSchedZbf; -defm : UnsupportedSchedZbm; defm : UnsupportedSchedZbkb; defm : UnsupportedSchedZbr; defm : UnsupportedSchedZfh; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index 4edfff7..a35e935 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -230,9 +230,6 @@ defm : UnsupportedSchedZba; defm : UnsupportedSchedZbb; defm : UnsupportedSchedZbc; defm : UnsupportedSchedZbs; -defm : UnsupportedSchedZbe; -defm : UnsupportedSchedZbf; -defm : UnsupportedSchedZbm; defm : UnsupportedSchedZbkb; defm : UnsupportedSchedZbr; defm : UnsupportedSchedZfh; diff --git a/llvm/lib/Target/RISCV/RISCVScheduleB.td b/llvm/lib/Target/RISCV/RISCVScheduleB.td index 68aeb8a..ab78438 100644 --- a/llvm/lib/Target/RISCV/RISCVScheduleB.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleB.td @@ -33,19 +33,6 @@ def WriteCLMUL : SchedWrite; // CLMUL/CLMULR/CLMULH def WriteSingleBit : SchedWrite; // BCLR/BSET/BINV/BEXT def WriteSingleBitImm: SchedWrite; // BCLRI/BSETI/BINVI/BEXTI -// Zbe extension -def WriteDecompress : SchedWrite; // bdecompress -def WriteCompress : SchedWrite; // bcompress -def WriteDecompress32: SchedWrite; // bdecompressw -def WriteCompress32 : SchedWrite; // bcompressw - -// Zbf extension -def WriteBFP : SchedWrite; // BFP -def WriteBFP32 : SchedWrite; // BFPW - -// Zbm extension -def WriteBMatrix : SchedWrite; // bmator/bmatxor/bmatflip - // Zbkb extension def WritePACK : SchedWrite; // pack/packh def WritePACK32 : SchedWrite; // packw @@ -89,19 +76,6 @@ def ReadCLMUL : SchedRead; // CLMUL/CLMULR/CLMULH def ReadSingleBit : SchedRead; // BCLR/BSET/BINV/BEXT def ReadSingleBitImm: SchedRead; // BCLRI/BSETI/BINVI/BEXTI -// Zbe extension -def ReadDecompress : SchedRead; // bdecompress -def ReadCompress : SchedRead; // bcompress -def ReadDecompress32: SchedRead; // bdecompressw -def ReadCompress32 : SchedRead; // bcompressw - -// Zbf extension -def ReadBFP : SchedRead; // BFP -def ReadBFP32 : SchedRead; // BFPW - -// Zbm extension -def ReadBMatrix : SchedRead; // bmator/bmatxor/bmatflip - // Zbkb extension def ReadPACK : SchedRead; // pack/packh def ReadPACK32 : SchedRead; // packw @@ -178,38 +152,6 @@ def : ReadAdvance; } } -multiclass UnsupportedSchedZbe { -let Unsupported = true in { -def : WriteRes; -def : WriteRes; -def : WriteRes; -def : WriteRes; - -def : ReadAdvance; -def : ReadAdvance; -def : ReadAdvance; -def : ReadAdvance; -} -} - -multiclass UnsupportedSchedZbf { -let Unsupported = true in { -def : WriteRes; -def : WriteRes; - -def : ReadAdvance; -def : ReadAdvance; -} -} - -multiclass UnsupportedSchedZbm { -let Unsupported = true in { -def : WriteRes; - -def : ReadAdvance; -} -} - multiclass UnsupportedSchedZbkb { let Unsupported = true in { def : WriteRes; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 6881ad8..7861946 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -54,10 +54,6 @@ private: bool HasStdExtZba = false; bool HasStdExtZbb = false; bool HasStdExtZbc = false; - bool HasStdExtZbe = false; - bool HasStdExtZbf = false; - bool HasStdExtZbm = false; - bool HasStdExtZbr = false; bool HasStdExtZbs = false; bool HasStdExtZca = false; bool HasStdExtV = false; @@ -163,10 +159,6 @@ public: bool hasStdExtZba() const { return HasStdExtZba; } bool hasStdExtZbb() const { return HasStdExtZbb; } bool hasStdExtZbc() const { return HasStdExtZbc; } - bool hasStdExtZbe() const { return HasStdExtZbe; } - bool hasStdExtZbf() const { return HasStdExtZbf; } - bool hasStdExtZbm() const { return HasStdExtZbm; } - bool hasStdExtZbr() const { return HasStdExtZbr; } bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZca() const { return HasStdExtZca; } bool hasStdExtZvl() const { return ZvlLen != 0; } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index fa23d3d..4136c6f 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -14,10 +14,6 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zba %s -o - | FileCheck --check-prefix=RV32ZBA %s ; RUN: llc -mtriple=riscv32 -mattr=+zbb %s -o - | FileCheck --check-prefix=RV32ZBB %s ; RUN: llc -mtriple=riscv32 -mattr=+zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV32ZBE %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s ; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s ; RUN: llc -mtriple=riscv32 -mattr=+v %s -o - | FileCheck --check-prefix=RV32V %s ; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s @@ -54,10 +50,6 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefix=RV64ZBA %s ; RUN: llc -mtriple=riscv64 -mattr=+zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s ; RUN: llc -mtriple=riscv64 -mattr=+zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s ; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s ; RUN: llc -mtriple=riscv64 -mattr=+v %s -o - | FileCheck --check-prefix=RV64V %s ; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s @@ -97,10 +89,6 @@ ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0" ; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0" ; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0" -; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93" -; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93" -; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93" -; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" ; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" @@ -138,10 +126,6 @@ ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0" ; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0" ; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0" -; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93" -; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93" -; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93" -; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93" ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" ; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" diff --git a/llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll deleted file mode 100644 index c5fbb2b..0000000 --- a/llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll +++ /dev/null @@ -1,25 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32ZBE - -declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) - -define i32 @bcompress32(i32 %a, i32 %b) nounwind { -; RV32ZBE-LABEL: bcompress32: -; RV32ZBE: # %bb.0: -; RV32ZBE-NEXT: bcompress a0, a0, a1 -; RV32ZBE-NEXT: ret - %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) - ret i32 %tmp -} - -declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b) - -define i32 @bdecompress32(i32 %a, i32 %b) nounwind { -; RV32ZBE-LABEL: bdecompress32: -; RV32ZBE: # %bb.0: -; RV32ZBE-NEXT: bdecompress a0, a0, a1 -; RV32ZBE-NEXT: ret - %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b) - ret i32 %tmp -} diff --git a/llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll deleted file mode 100644 index b9c6693..0000000 --- a/llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll +++ /dev/null @@ -1,14 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32ZBF - -declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b) - -define i32 @bfp32(i32 %a, i32 %b) nounwind { -; RV32ZBF-LABEL: bfp32: -; RV32ZBF: # %bb.0: -; RV32ZBF-NEXT: bfp a0, a0, a1 -; RV32ZBF-NEXT: ret - %tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b) - ret i32 %tmp -} diff --git a/llvm/test/CodeGen/RISCV/rv32zbr.ll b/llvm/test/CodeGen/RISCV/rv32zbr.ll deleted file mode 100644 index d4f8899..0000000 --- a/llvm/test/CodeGen/RISCV/rv32zbr.ll +++ /dev/null @@ -1,69 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32ZBR - -declare i32 @llvm.riscv.crc32.b.i32(i32) - -define i32 @crc32b(i32 %a) nounwind { -; RV32ZBR-LABEL: crc32b: -; RV32ZBR: # %bb.0: -; RV32ZBR-NEXT: crc32.b a0, a0 -; RV32ZBR-NEXT: ret - %tmp = call i32 @llvm.riscv.crc32.b.i32(i32 %a) - ret i32 %tmp -} - -declare i32 @llvm.riscv.crc32.h.i32(i32) - -define i32 @crc32h(i32 %a) nounwind { -; RV32ZBR-LABEL: crc32h: -; RV32ZBR: # %bb.0: -; RV32ZBR-NEXT: crc32.h a0, a0 -; RV32ZBR-NEXT: ret - %tmp = call i32 @llvm.riscv.crc32.h.i32(i32 %a) - ret i32 %tmp -} - -declare i32 @llvm.riscv.crc32.w.i32(i32) - -define i32 @crc32w(i32 %a) nounwind { -; RV32ZBR-LABEL: crc32w: -; RV32ZBR: # %bb.0: -; RV32ZBR-NEXT: crc32.w a0, a0 -; RV32ZBR-NEXT: ret - %tmp = call i32 @llvm.riscv.crc32.w.i32(i32 %a) - ret i32 %tmp -} - -declare i32 @llvm.riscv.crc32c.b.i32(i32) - -define i32 @crc32cb(i32 %a) nounwind { -; RV32ZBR-LABEL: crc32cb: -; RV32ZBR: # %bb.0: -; RV32ZBR-NEXT: crc32c.b a0, a0 -; RV32ZBR-NEXT: ret - %tmp = call i32 @llvm.riscv.crc32c.b.i32(i32 %a) - ret i32 %tmp -} - -declare i32 @llvm.riscv.crc32c.h.i32(i32) - -define i32 @crc32ch(i32 %a) nounwind { -; RV32ZBR-LABEL: crc32ch: -; RV32ZBR: # %bb.0: -; RV32ZBR-NEXT: crc32c.h a0, a0 -; RV32ZBR-NEXT: ret - %tmp = call i32 @llvm.riscv.crc32c.h.i32(i32 %a) - ret i32 %tmp -} - -declare i32 @llvm.riscv.crc32c.w.i32(i32) - -define i32 @crc32cw(i32 %a) nounwind { -; RV32ZBR-LABEL: crc32cw: -; RV32ZBR: # %bb.0: -; RV32ZBR-NEXT: crc32c.w a0, a0 -; RV32ZBR-NEXT: ret - %tmp = call i32 @llvm.riscv.crc32c.w.i32(i32 %a) - ret i32 %tmp -} diff --git a/llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll deleted file mode 100644 index c470285..0000000 --- a/llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll +++ /dev/null @@ -1,73 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64ZBE - -declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) - -define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind { -; RV64ZBE-LABEL: bcompress32: -; RV64ZBE: # %bb.0: -; RV64ZBE-NEXT: bcompressw a0, a0, a1 -; RV64ZBE-NEXT: ret - %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) - ret i32 %tmp -} - -define signext i32 @bcompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { -; RV64ZBE-LABEL: bcompress32_demandedbits: -; RV64ZBE: # %bb.0: -; RV64ZBE-NEXT: add a0, a0, a1 -; RV64ZBE-NEXT: add a1, a2, a3 -; RV64ZBE-NEXT: bcompressw a0, a0, a1 -; RV64ZBE-NEXT: ret - %e = add i32 %a, %b - %f = add i32 %c, %d - %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %e, i32 %f) - ret i32 %tmp -} - -declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b) - -define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind { -; RV64ZBE-LABEL: bdecompress32: -; RV64ZBE: # %bb.0: -; RV64ZBE-NEXT: bdecompressw a0, a0, a1 -; RV64ZBE-NEXT: ret - %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b) - ret i32 %tmp -} - -define signext i32 @bdecompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { -; RV64ZBE-LABEL: bdecompress32_demandedbits: -; RV64ZBE: # %bb.0: -; RV64ZBE-NEXT: add a0, a0, a1 -; RV64ZBE-NEXT: add a1, a2, a3 -; RV64ZBE-NEXT: bdecompressw a0, a0, a1 -; RV64ZBE-NEXT: ret - %e = add i32 %a, %b - %f = add i32 %c, %d - %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %e, i32 %f) - ret i32 %tmp -} - -declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b) - -define i64 @bcompress64(i64 %a, i64 %b) nounwind { -; RV64ZBE-LABEL: bcompress64: -; RV64ZBE: # %bb.0: -; RV64ZBE-NEXT: bcompress a0, a0, a1 -; RV64ZBE-NEXT: ret - %tmp = call i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b) - ret i64 %tmp -} - -declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b) - -define i64 @bdecompress64(i64 %a, i64 %b) nounwind { -; RV64ZBE-LABEL: bdecompress64: -; RV64ZBE: # %bb.0: -; RV64ZBE-NEXT: bdecompress a0, a0, a1 -; RV64ZBE-NEXT: ret - %tmp = call i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b) - ret i64 %tmp -} diff --git a/llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll deleted file mode 100644 index 9e41177..0000000 --- a/llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll +++ /dev/null @@ -1,25 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64ZBF - -declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b) - -define signext i32 @bfp32(i32 signext %a, i32 signext %b) nounwind { -; RV64ZBF-LABEL: bfp32: -; RV64ZBF: # %bb.0: -; RV64ZBF-NEXT: bfpw a0, a0, a1 -; RV64ZBF-NEXT: ret - %tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b) - ret i32 %tmp -} - -declare i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b) - -define i64 @bfp64(i64 %a, i64 %b) nounwind { -; RV64ZBF-LABEL: bfp64: -; RV64ZBF: # %bb.0: -; RV64ZBF-NEXT: bfp a0, a0, a1 -; RV64ZBF-NEXT: ret - %tmp = call i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b) - ret i64 %tmp -} diff --git a/llvm/test/CodeGen/RISCV/rv64zbr.ll b/llvm/test/CodeGen/RISCV/rv64zbr.ll deleted file mode 100644 index fadb2cb..0000000 --- a/llvm/test/CodeGen/RISCV/rv64zbr.ll +++ /dev/null @@ -1,91 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64ZBR - -declare i64 @llvm.riscv.crc32.b.i64(i64) - -define i64 @crc32b(i64 %a) nounwind { -; RV64ZBR-LABEL: crc32b: -; RV64ZBR: # %bb.0: -; RV64ZBR-NEXT: crc32.b a0, a0 -; RV64ZBR-NEXT: ret - %tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a) - ret i64 %tmp -} - -declare i64 @llvm.riscv.crc32.h.i64(i64) - -define i64 @crc32h(i64 %a) nounwind { -; RV64ZBR-LABEL: crc32h: -; RV64ZBR: # %bb.0: -; RV64ZBR-NEXT: crc32.h a0, a0 -; RV64ZBR-NEXT: ret - %tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a) - ret i64 %tmp -} - -declare i64 @llvm.riscv.crc32.w.i64(i64) - -define i64 @crc32w(i64 %a) nounwind { -; RV64ZBR-LABEL: crc32w: -; RV64ZBR: # %bb.0: -; RV64ZBR-NEXT: crc32.w a0, a0 -; RV64ZBR-NEXT: ret - %tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a) - ret i64 %tmp -} - -declare i64 @llvm.riscv.crc32c.b.i64(i64) - -define i64 @crc32cb(i64 %a) nounwind { -; RV64ZBR-LABEL: crc32cb: -; RV64ZBR: # %bb.0: -; RV64ZBR-NEXT: crc32c.b a0, a0 -; RV64ZBR-NEXT: ret - %tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a) - ret i64 %tmp -} - -declare i64 @llvm.riscv.crc32c.h.i64(i64) - -define i64 @crc32ch(i64 %a) nounwind { -; RV64ZBR-LABEL: crc32ch: -; RV64ZBR: # %bb.0: -; RV64ZBR-NEXT: crc32c.h a0, a0 -; RV64ZBR-NEXT: ret - %tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a) - ret i64 %tmp -} - -declare i64 @llvm.riscv.crc32c.w.i64(i64) - -define i64 @crc32cw(i64 %a) nounwind { -; RV64ZBR-LABEL: crc32cw: -; RV64ZBR: # %bb.0: -; RV64ZBR-NEXT: crc32c.w a0, a0 -; RV64ZBR-NEXT: ret - %tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a) - ret i64 %tmp -} - -declare i64 @llvm.riscv.crc32.d.i64(i64) - -define i64 @crc32d(i64 %a) nounwind { -; RV64ZBR-LABEL: crc32d: -; RV64ZBR: # %bb.0: -; RV64ZBR-NEXT: crc32.d a0, a0 -; RV64ZBR-NEXT: ret - %tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a) - ret i64 %tmp -} - -declare i64 @llvm.riscv.crc32c.d.i64(i64) - -define i64 @crc32cd(i64 %a) nounwind { -; RV64ZBR-LABEL: crc32cd: -; RV64ZBR: # %bb.0: -; RV64ZBR-NEXT: crc32c.d a0, a0 -; RV64ZBR-NEXT: ret - %tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a) - ret i64 %tmp -} diff --git a/llvm/test/MC/RISCV/attribute-arch-invalid.s b/llvm/test/MC/RISCV/attribute-arch-invalid.s index f6ad5ff..5f9a439 100644 --- a/llvm/test/MC/RISCV/attribute-arch-invalid.s +++ b/llvm/test/MC/RISCV/attribute-arch-invalid.s @@ -5,17 +5,5 @@ ## Version strings are required for experimental extensions -.attribute arch, "rv32izbe" -# CHECK: error: invalid arch name 'rv32izbe', experimental extension requires explicit version number `zbe` - -.attribute arch, "rv32izbf" -# CHECK: error: invalid arch name 'rv32izbf', experimental extension requires explicit version number `zbf` - -.attribute arch, "rv32izbm" -# CHECK: error: invalid arch name 'rv32izbm', experimental extension requires explicit version number `zbm` - -.attribute arch, "rv32izbr" -# CHECK: error: invalid arch name 'rv32izbr', experimental extension requires explicit version number `zbr` - .attribute arch, "rv32izvfh" # CHECK: error: invalid arch name 'rv32izvfh', experimental extension requires explicit version number `zvfh` diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index ade362c..af34567 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -107,24 +107,9 @@ .attribute arch, "rv32izbc1p0" # CHECK: attribute 5, "rv32i2p0_zbc1p0" -.attribute arch, "rv32izbe0p93" -# CHECK: attribute 5, "rv32i2p0_zbe0p93" - -.attribute arch, "rv32izbf0p93" -# CHECK: attribute 5, "rv32i2p0_zbf0p93" - -.attribute arch, "rv32izbm0p93" -# CHECK: attribute 5, "rv32i2p0_zbm0p93" - -.attribute arch, "rv32izbr0p93" -# CHECK: attribute 5, "rv32i2p0_zbr0p93" - .attribute arch, "rv32izbs1p0" # CHECK: attribute 5, "rv32i2p0_zbs1p0" -.attribute arch, "rv32izbt0p93" -# CHECK: attribute 5, "rv32i2p0_zbt0p93" - .attribute arch, "rv32ifzfhmin1p0" # CHECK: attribute 5, "rv32i2p0_f2p0_zfhmin1p0" diff --git a/llvm/test/MC/RISCV/rv32zbe-invalid.s b/llvm/test/MC/RISCV/rv32zbe-invalid.s deleted file mode 100644 index b3407f5..0000000 --- a/llvm/test/MC/RISCV/rv32zbe-invalid.s +++ /dev/null @@ -1,8 +0,0 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbe < %s 2>&1 | FileCheck %s - -# Too few operands -bdecompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -bcompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -bdecompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} -bcompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zbe-valid.s b/llvm/test/MC/RISCV/rv32zbe-valid.s deleted file mode 100644 index 5b0aefd..0000000 --- a/llvm/test/MC/RISCV/rv32zbe-valid.s +++ /dev/null @@ -1,18 +0,0 @@ -# With Bitmanip extract/deposit extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbe -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbe -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbe < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbe -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbe < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbe -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: bdecompress t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x48] -bdecompress t0, t1, t2 -# CHECK-ASM-AND-OBJ: bcompress t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x08] -bcompress t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv32zbf-invalid.s b/llvm/test/MC/RISCV/rv32zbf-invalid.s deleted file mode 100644 index 9e78e56..0000000 --- a/llvm/test/MC/RISCV/rv32zbf-invalid.s +++ /dev/null @@ -1,5 +0,0 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbf < %s 2>&1 | FileCheck %s - -# Too few operands -bfp t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -bfpw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zbf-valid.s b/llvm/test/MC/RISCV/rv32zbf-valid.s deleted file mode 100644 index 4542fc0..0000000 --- a/llvm/test/MC/RISCV/rv32zbf-valid.s +++ /dev/null @@ -1,15 +0,0 @@ -# With Bit-Field extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbf -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbf -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbf < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbf -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbf < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbf -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: bfp t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x48] -bfp t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv32zbr-invalid.s b/llvm/test/MC/RISCV/rv32zbr-invalid.s deleted file mode 100644 index c886887..0000000 --- a/llvm/test/MC/RISCV/rv32zbr-invalid.s +++ /dev/null @@ -1,16 +0,0 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbr < %s 2>&1 | FileCheck %s - -# Too many operands -crc32.b t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction -# Too many operands -crc32.h t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction -# Too many operands -crc32.w t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction -# Too many operands -crc32c.b t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction -# Too many operands -crc32c.h t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction -# Too many operands -crc32c.w t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction -crc32.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} -crc32c.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zbr-valid.s b/llvm/test/MC/RISCV/rv32zbr-valid.s deleted file mode 100644 index 4e32da5..0000000 --- a/llvm/test/MC/RISCV/rv32zbr-valid.s +++ /dev/null @@ -1,25 +0,0 @@ -# With Bitmanip CRC extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbr -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbr < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbr -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: crc32.b t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x03,0x61] -crc32.b t0, t1 -# CHECK-ASM-AND-OBJ: crc32.h t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x13,0x61] -crc32.h t0, t1 -# CHECK-ASM-AND-OBJ: crc32.w t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x23,0x61] -crc32.w t0, t1 -# CHECK-ASM-AND-OBJ: crc32c.b t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x83,0x61] -crc32c.b t0, t1 -# CHECK-ASM-AND-OBJ: crc32c.h t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x93,0x61] -crc32c.h t0, t1 -# CHECK-ASM-AND-OBJ: crc32c.w t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0xa3,0x61] -crc32c.w t0, t1 diff --git a/llvm/test/MC/RISCV/rv64zbe-invalid.s b/llvm/test/MC/RISCV/rv64zbe-invalid.s deleted file mode 100644 index 003f421..0000000 --- a/llvm/test/MC/RISCV/rv64zbe-invalid.s +++ /dev/null @@ -1,6 +0,0 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbe < %s 2>&1 | FileCheck %s - -# Too few operands -bdecompressw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -bcompressw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64zbe-valid.s b/llvm/test/MC/RISCV/rv64zbe-valid.s deleted file mode 100644 index 0a5c725..0000000 --- a/llvm/test/MC/RISCV/rv64zbe-valid.s +++ /dev/null @@ -1,13 +0,0 @@ -# With Bitmanip extract/deposit extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbe -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbe < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbe -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: bdecompressw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x48] -bdecompressw t0, t1, t2 -# CHECK-ASM-AND-OBJ: bcompressw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x08] -bcompressw t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64zbf-invalid.s b/llvm/test/MC/RISCV/rv64zbf-invalid.s deleted file mode 100644 index 97ea8a9..0000000 --- a/llvm/test/MC/RISCV/rv64zbf-invalid.s +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbf < %s 2>&1 | FileCheck %s - -# Too few operands -bfpw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64zbf-valid.s b/llvm/test/MC/RISCV/rv64zbf-valid.s deleted file mode 100644 index 758a926..0000000 --- a/llvm/test/MC/RISCV/rv64zbf-valid.s +++ /dev/null @@ -1,10 +0,0 @@ -# With Bit-Field extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbf -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbf < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbf -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: bfpw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x72,0x73,0x48] -bfpw t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64zbm-invalid.s b/llvm/test/MC/RISCV/rv64zbm-invalid.s deleted file mode 100644 index ef78001..0000000 --- a/llvm/test/MC/RISCV/rv64zbm-invalid.s +++ /dev/null @@ -1,8 +0,0 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbm < %s 2>&1 | FileCheck %s - -# Too many operands -bmatflip t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction -# Too few operands -bmator t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -bmatxor t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64zbm-valid.s b/llvm/test/MC/RISCV/rv64zbm-valid.s deleted file mode 100644 index 0418b60..0000000 --- a/llvm/test/MC/RISCV/rv64zbm-valid.s +++ /dev/null @@ -1,16 +0,0 @@ -# With Bitmanip matix extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbm -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbm < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbm -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: bmatflip t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x33,0x60] -bmatflip t0, t1 -# CHECK-ASM-AND-OBJ: bmator t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x08] -bmator t0, t1, t2 -# CHECK-ASM-AND-OBJ: bmatxor t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x48] -bmatxor t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64zbr-invalid.s b/llvm/test/MC/RISCV/rv64zbr-invalid.s deleted file mode 100644 index ee383d4..0000000 --- a/llvm/test/MC/RISCV/rv64zbr-invalid.s +++ /dev/null @@ -1,6 +0,0 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbr < %s 2>&1 | FileCheck %s - -# Too many operands -crc32.d t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction -# Too many operands -crc32c.d t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64zbr-valid.s b/llvm/test/MC/RISCV/rv64zbr-valid.s deleted file mode 100644 index e271f287..0000000 --- a/llvm/test/MC/RISCV/rv64zbr-valid.s +++ /dev/null @@ -1,31 +0,0 @@ -# With Bitmanip CRC extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbr -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbr < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbr -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: crc32.b t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x03,0x61] -crc32.b t0, t1 -# CHECK-ASM-AND-OBJ: crc32.h t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x13,0x61] -crc32.h t0, t1 -# CHECK-ASM-AND-OBJ: crc32.w t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x23,0x61] -crc32.w t0, t1 -# CHECK-ASM-AND-OBJ: crc32c.b t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x83,0x61] -crc32c.b t0, t1 -# CHECK-ASM-AND-OBJ: crc32c.h t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x93,0x61] -crc32c.h t0, t1 -# CHECK-ASM-AND-OBJ: crc32c.w t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0xa3,0x61] -crc32c.w t0, t1 -# CHECK-ASM-AND-OBJ: crc32.d t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x33,0x61] -crc32.d t0, t1 -# CHECK-ASM-AND-OBJ: crc32c.d t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0xb3,0x61] -crc32c.d t0, t1 -- 2.7.4